TW201810384A - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TW201810384A
TW201810384A TW105123962A TW105123962A TW201810384A TW 201810384 A TW201810384 A TW 201810384A TW 105123962 A TW105123962 A TW 105123962A TW 105123962 A TW105123962 A TW 105123962A TW 201810384 A TW201810384 A TW 201810384A
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semiconductor structure
forming
source
doping
epitaxial layer
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肖德元
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上海新昇半導體科技有限公司
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Abstract

本發明揭示了一種半導體結構及其形成方法。該半導體結構的形成方法，包括提供一具有假閘極的基板；在該基板上假閘極進行升高源汲極磊晶區域的第一次同位摻雜以形成淡摻雜的源/汲磊晶層；在該基板上假閘極進行升高源汲極磊晶區域的第二次同位摻雜以形成濃摻雜的源/汲磊晶層。

Description

半導體結構及其形成方法
本發明涉及半導體製造領域，尤其涉及一種三維半導體結構及其形成方法。
隨著可攜式電子產品不斷的推陳出新，其製程技術也不斷的在進步，而產品尺寸的微小化為目前最受關注的技術，如金氧半場效應電晶體(MOSFET)不斷的被微小化，然而電晶體的微小化衍生出許多物理上的限制以及問題，例如熱載子注入、漏電流、絕緣、短通道效應(Short-Channel Effects，SCEs)及通道長度控制等，使得電晶體之閘極對於通道內的控制能力逐漸降低。
特別是，在閘極正下方的離子佈植劑量容易隨著微小化而增加。此外，源汲極延伸區域所造成的傷害也會隨著微小化而包含了更多的通道區域。而這些離子佈植的傷害也進一步提供更多協助解緩應力或是雜質(例如稼)自底層向上擴散的點缺陷。
而且，於退火之後仍存在的離子佈植傷害或許會做為載子散射中心。在例如是離子佈植後熱退火的應變矽薄膜的熱製程中可以造成失配位錯的缺陷而導致應力釋放以及雜質過度擴散等問題，最終造成載子遷移率降低的問題。
於是，為了解決電晶體因微小化所產生的問題，多重閘極三維(Multi-Gate 3D)電晶體被提出以改善閘極對於通道之控制能力。常見之多重閘極電晶體為在矽基板上製造三閘極(tri-gate)電晶體或環繞式閘極(gate-all-around)電晶體，然而，該類三維度隔離通道裝置之遷移率以及製程上仍然存在許多問題。
然而，在習知的多重閘極三維(Multi-Gate 3D)電晶體結構中，升高的源汲極很難利用傳統的離子佈植進行摻雜。而且在狹窄的鰭形結構中，傳統離子佈植所造成的非晶結構也很難藉由熱退火來完全恢復，甚至因此會造成升高的源汲極重新聚集在一起，從而影響所形成的半導體元件的性能。因此，需要提供一種新的雜質摻雜方式以及後續的熱退火製程，以改善上述的諸多缺點。
本發明的目的在於提供一種半導體結構及其形成方法，以改善傳統三維(Multi-Gate 3D)電晶體所面對的問題。
為解決上述技術問題，本發明提供一種半導體結構的形成方法，包括：提供一具有假閘極的基板；在該基板上假閘極進行升高源汲極磊晶區域的第一次同位摻雜以形成淡摻雜的源/汲磊晶層；在該基板上假閘極進行升高源汲極磊晶區域的第二次同位摻雜以形成濃摻雜的源/汲磊晶層。
本發明可選擇性地變化，在此舉例而不限制於：在完成所述升高源/汲磊晶層的兩次摻雜之後，更包含進行脈衝雷射退火的步驟；其中所述升高源/汲磊晶層於所述脈衝雷射退火之後其形狀仍保持不變且不 會有所接觸。
進一步的，其中所述基板包含矽、絕緣層覆矽(SOI)、SixGe1-x(0<x<1)於絕緣層覆矽上、SixGe1-x(0<x<1)於矽上、鍺(Ge)、砷化鎵(GaAs)、InP、InSb、InGaAs、AlGaAs、InAlAs及其組合。
進一步的，其中所述摻雜是植入N型，是選自砷化氫(AsH3),磷化氫(PH3)及其組合。
進一步的，其中所述摻雜是植入P型，可以是選自乙硼烷(diborane)。
進一步的，其中所述第一次同位摻雜的濃度係介於1.0E17原子/cm3至5.0E18原子/cm3之間。
進一步的，其中所述第二次同位摻雜的濃度係介於5.0E18原子/cm3至2.0E19原子/cm3之間。
相應的，本發明還提供一種由如上所述的半導體結構的形成方法獲得的半導體結構，包括：半導體基板，一鰭型半導體結構形成於該半導體基板上；淡摻雜的源/汲磊晶層；及濃摻雜的源/汲磊晶層。
10‧‧‧基板
15‧‧‧鰭型半導體
20‧‧‧假閘極
25‧‧‧淺溝渠隔離(STI)
30‧‧‧淡摻雜的源/汲磊晶層
35‧‧‧濃摻雜的源/汲磊晶層
第1圖為本發明的半導體結構的形成方法的流程圖；第2圖-第4圖為本發明的半導體結構在形成過程中的結構示意圖。
下面將結合示意圖對本發明的半導體結構及其形成方法進 行更詳細的描述，其中表示了本發明的優選實施例，應該理解本領域技術人員可以修改在此描述的本發明，而仍然實現本發明的有益效果。因此，下列描述應當被理解為對於本領域技術人員的廣泛知道，而並不作為對本發明的限制。
在下列段落中參照附圖以舉例方式更具體地描述本發明。根據下面說明和權利要求書，本發明的優點和特徵將更清楚。需說明的是，附圖均採用非常簡化的形式且均使用非精准的比例，僅用以方便、明晰地輔助說明本發明實施例的目的。
在此說明書中，此名詞"半導體"是用來代表可包括選自至少一III族元素及一至少V族元素所構成的III-V族化合物。通常而言，此III-V族化合物半導體是包含III-V族元素的二元、三元或四元合金。舉例而言，可以用於本發明中的範例III-V族化合物半導體包括GaAs,InP,InSb,InGaAs,AlGaAs,InAlAs,InAlAsSb,以及InGaAsP等，但是並不局限於上述的例子而已。
首先，請參考第1圖，在本實施例的一方面，提出了一種非平面(或可稱為應變)半導體元件的製造方法，包括步驟：S100：提供一基板，其上具有一通道區域之鰭狀半導體，且形成假閘極於所述鰭狀半導體之上；S200：進行升高源汲極磊晶區域的第一次摻雜以形成淡摻雜的源/汲磊晶層；S300：進行升高源汲極磊晶區域的第二次摻雜以形成濃摻雜的源/汲磊晶層； S400：(可選的)進行脈衝雷射退火。
具體的，請參考第2到第4圖，對本發明的非平面(或可稱為應變)半導體元件之形成方法進行詳細說明。
首先，請參考第2圖：執行步驟S101，提供具有假閘極20的基板10；在一實施例中，基板10為矽基板，其上具有鰭型半導體15和淺溝渠隔離(STI)25等結構。以提供後續升高源汲極磊晶區域的生長，該假閘極20可以參考現有技術中的後閘極(gate last)製程中的常見選擇。在其他的實施例中，基板10可以是絕緣層覆矽(SOI)、SixGe1-x(0<x<1)於絕緣層覆矽上、SixGe1-x(0<x<l)於矽上、鍺(Ge)、砷化鎵(GaAs)、InP、InSb、InGaAs、AlGaAs、InAlAs及其組合。
在本步驟之後，例如還包括對基板進行清洗等常規過程，此處不進行詳述。
接著，如第3圖所示，執行步驟S102，在該基板10上假閘極20進行升高源汲極磊晶區域的第一次摻雜以形成淡摻雜的源/汲磊晶層30；具體的，該第一次摻雜可以使用同位(in-situ)氣相磊晶沉積製程。在一實施例中，此摻雜的雜質是N型，可以是選自砷化氫(AsH3),磷化氫(PH3)及其組合。而在另一實施例中，此摻雜的雜質是P型，可以是選自乙硼烷(diborane)。該第一次摻雜的濃度較佳但不限於是介在1.0E17原子/cm3至5.0E18原子/cm3之間。
在該氣相磊晶沉積製程中，優選的，反應溫度為800℃-1100℃，持續時間為10-2000mins。從而獲得厚度為10-5000nm的淡摻雜源/汲磊晶層30。
依據實際需求，可以對反應氣體的種類、反應溫度及時間進行靈活調整，以獲得符合製程需求的淡摻雜源/汲磊晶層30。
之後，請參考第4圖，執行步驟S103，在該基板10上假閘極20進行升高源汲極磊晶區域的第二次摻雜以形成濃摻雜的源/汲磊晶層35於之前形成的淡摻雜的源/汲磊晶層30之外側；具體的，該第二次摻雜也可以使用同位(in-situ)氣相磊晶沉積製程。類似地，在一實施例中，此摻雜的雜質是N型，可以是選自砷化氫(AsH3),磷化氫(PH3)及其組合。而在另一實施例中，此摻雜的雜質是P型，可以是選自乙硼烷(diborane)。該第二次摻雜的濃度較佳但不限於是介在5.0E18原子/cm3至2.0E19原子/cm3之間。
在該氣相磊晶沉積製程中，優選的，反應溫度為800℃-1100℃，持續時間為10-2000mins。從而獲得厚度為10-5000nm的濃摻雜源/汲磊晶層35，且此濃摻雜源/汲磊晶層35的厚度是小於淡摻雜源/汲磊晶層30的厚度。
依據實際需求，可以對反應氣體的種類、反應溫度及時間進行靈活調整，以獲得符合製程需求的濃摻雜源/汲磊晶層35。
最後，執行步驟S104，在完成升高源/汲磊晶層的摻雜步驟之後，還可以選擇性地進行脈衝雷射退火步驟以進一步活化雜質並且不會改變原本形成之升高源/汲磊晶層的形狀。前述脈衝雷射退火是在介於1200℃至1400℃之間的溫度進行，持續時間為0.0001-10秒。
顯然，本領域的技術人員可以對本發明進行各種修改和變型而不脫離本發明的精神和範圍。這樣，倘若本發明的這些修改和變型屬於本發明權利要求及其等同技術的範圍之內，則本發明也意圖包含這些修改 和變型在內。

Claims (10)

  1. 一種半導體結構的形成方法，包括：提供一具有假閘極的基板；在該基板上假閘極進行升高源汲極磊晶區域的第一次同位摻雜以形成淡摻雜的源/汲磊晶層；在該基板上假閘極進行升高源汲極磊晶區域的第二次同位摻雜以形成濃摻雜的源/汲磊晶層。
  2. 如申請專利範圍第1項所述的半導體結構的形成方法，在完成所述升高源/汲磊晶層的兩次摻雜之後，更包含進行脈衝雷射退火的步驟。
  3. 如申請專利範圍第2項所述的半導體結構的形成方法，其中所述升高源/汲磊晶層於所述脈衝雷射退火之後其形狀仍保持不變且不會有所接觸。
  4. 如申請專利範圍第1項所述的半導體結構的形成方法，其中所述基板包含矽、絕緣層覆矽(SOI)、SixGe1-x(0<x<1)於絕緣層覆矽上、SixGe1-x(0<x<1)於矽上、鍺(Ge)、砷化鎵(GaAs)、InP、InSb、InGaAs、AlGaAs、InAlAs及其組合。
  5. 如申請專利範圍第1項所述的半導體結構的形成方法，其中所述摻雜是植入N型，是選自砷化氫(AsH3),磷化氫(PH3)及其組合。
  6. 如申請專利範圍第1項所述的半導體結構的形成方法，其中所述摻雜是植入P型，可以是選自乙硼烷(diborane)。
  7. 如申請專利範圍第1項所述的半導體結構的形成方法，其中所述第一次同位摻雜的濃度係介於1.0E17原子/cm3至5.0E18原子/cm3之間。
  8. 如申請專利範圍第1項所述的半導體結構的形成方法，其中所述第二次同位摻雜的濃度係介於5.0E18原子/cm3至2.0E19原子/cm3之間。
  9. 如申請專利範圍第2項所述的半導體結構的形成方法，其中所述脈衝雷射退火的溫度為1200℃-1400℃。
  10. 一種由申請專利範圍第1項到第9項之任一項所述的半導體結構的形成方法獲得的半導體結構，包括：一半導體基板，一鰭型半導體結構形成於該半導體基板上；淡摻雜的源/汲磊晶層；及濃摻雜的源/汲磊晶層。
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