CN107369712A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN107369712A
CN107369712A CN201610319775.4A CN201610319775A CN107369712A CN 107369712 A CN107369712 A CN 107369712A CN 201610319775 A CN201610319775 A CN 201610319775A CN 107369712 A CN107369712 A CN 107369712A
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肖德元
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Zing Semiconductor Corp
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Abstract

本发明揭示了一种半导体结构及其形成方法，该半导体结构的形成方法包括：提供一具有假栅极的基板；在该基板的假栅极进行升高源漏极外延区域的第一次原位掺杂以形成淡掺杂的源漏外延层；以及在该基板的假栅极进行升高源漏极外延区域的第二次原位掺杂以形成浓掺杂的源漏外延层。

Description

半导体结构及其形成方法
技术领域
本发明涉及半导体技术领域，特别涉及一种半导体结构及其形成方法。
背景技术
随着可携式电子产品不断的推陈出新，其工艺技术也不断的在进步，而产品尺寸的微小化为目前最受关注的技术，如金属氧化物半导体场效应晶体管(MOSFET)不断的被微小化，然而晶体管的微小化衍生出许多物理上的限制以及问题，例如载流子注入、漏电流、绝缘、短通道效应(Short-ChannelEffects，SCEs)及通道长度控制等，使得晶体管之栅极对于通道内的控制能力逐渐降低。
特别是，在栅极正下方的离子注入剂量容易随着微小化而增加。此外，源漏极延伸区域所造成的伤害也会随着微小化而包含了更多的通道区域。而这些离子注入的伤害也进一步提供更多协助解缓应力或是杂质(例如稼)自底层向上扩散的点缺陷。
而且，于退火之后仍存在的离子注入伤害或许会做为载流子散射中心。例如，离子注入后热退火的应变硅薄膜的热工艺中可以造成失配位错的缺陷而导致应力释放以及杂质过度扩散等问题，最终造成载流子迁移率降低的问题。
于是，为了解决晶体管因微小化所产生的问题，多重栅极三维(Multi-Gate3D)晶体管被提出以改善栅极对于通道之控制能力。常见之多重栅极晶体管为在硅基板上制造三栅极(tri-gate)晶体管或环绕式栅极(gate-all-around)晶体管，然而，该类三维度隔离通道装置之迁移率以及制造工艺上仍然存在许多问题。
然而，在现有的多重栅极三维(Multi-Gate 3D)晶体管结构中，升高的源漏极很难利用传统的离子注入进行掺杂。而且在狭窄的鳍形结构中，传统离子注入所造成的非晶结构也很难藉由热退火来完全恢复，甚至因此会造成升高的源漏极重新聚集在一起，从而影响所形成的半导体元件的性能。因此，需要提供一种新的杂质掺杂方式以及后续的热退火工艺，以改善上述的诸多缺点。
发明内容
本发明的目的在于提供一种半导体结构及其形成方法，以改善现有技术改善传统中三维晶体管的性能。
为解决上述问题，本发明提供一种半导体结构的形成方法，所述半导体结构的形成方法包括：
提供一具有假栅极的基板；
在该基板上的假栅极进行升高源漏极外延区域的第一次原位掺杂以形成淡掺杂的源漏外延层；以及
在该基板上的假栅极进行升高源漏极外延区域的第二次原位掺杂以形成浓掺杂的源漏外延层。
本发明可选择性地变化，在此举例而不限制于：在完成所述升高源漏极外延区域的两次掺杂之后，还包括：对所述升高源漏极外延区域进行脉冲雷射退火的步骤；
其中，所述源漏外延层的形状于所述脉冲雷射退火之后保持不变。
可选的，在所述的半导体结构的形成方法中，所述基板包含硅、绝缘层覆硅、锗硅于绝缘层覆硅上、锗硅于硅上、锗、砷化镓、磷化铟、锑化铟、铟镓砷、铝镓砷或铟铝砷中的任意一种或其任意组合。
可选的，在所述的半导体结构的形成方法中，所述第一次原位掺杂和第二次原位掺杂是植入N型杂质，所述N型杂质是砷化氢或磷化氢的任意一种或其组合。
可选的，在所述的半导体结构的形成方法中，其中所述第一次原位掺杂和第二次原位掺杂是植入P型杂质，所述P型杂质是乙硼烷。
可选的，在所述的半导体结构的形成方法中，所述第一次原位掺杂的浓度范围在1.0E17原子/cm3至5.0E18原子/cm3之间。
可选的，在所述的半导体结构的形成方法中，其中所述第二次原位掺杂的浓度范围在5.0E18原子/cm3至2.0E19原子/cm3之间
相应的，本发明还提供一种由如上所述的半导体结构的形成方法获得的半导体结构，所述导体结构包括：半导体基板，一鳍型半导体结构形成于该半导体基板上；淡掺杂的源漏外延层；及浓掺杂的源漏外延层。
附图说明
图1为本发明的半导体结构的形成方法的流程图；
图2-图4为本发明的半导体结构在形成过程中的结构示意图。
具体实施方式
以下结合附图和具体实施例对本发明提出的半导体结构及其形成方法作进一步详细说明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
下面将结合示意图对本发明的半导体结构及其形成方法进行更详细的描述，其中表示了本发明的优选实施例，应该理解本领域技术人员可以修改在此描述的本发明，而仍然实现本发明的有益效果。因此，下列描述应当被理解为对于本领域技术人员的广泛知道，而并不作为对本发明的限制。
在下列段落中参照附图以举例方式更具体地描述本发明。根据下面说明和权利要求书，本发明的优点和特征将更清楚。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
在此说明书中，此名词"半导体"是用来代表可包括选自至少一III族元素及一至少V族元素所构成的III-V族化合物。通常而言，此III-V族化合物半导体是包含III-V族元素的二元、三元或四元合金。举例而言，可以用于本发明中的范例III-V族化合物半导体包括GaAs、InP、InSb、InGaAs、AlGaAs、InAlAs、InAlAsSb以及InGaAsP等，但是并不局限于上述的例子而已。
本发明提供了一种非平面(或可称为应变)半导体结构的形成方法。请参考图1，其为本发明的半导体结构的形成方法的流程图。如图1所示，所述半导体元件的制造方法，包括步骤：
S101：提供一基板，其上具有一通道区域之鳍状半导体，且形成假栅极于所述鳍状半导体之上；
S102：进行升高源漏极外延区域的第一次掺杂以形成淡掺杂的源漏外延层；
S103：进行升高源漏极外延区域的第二次掺杂以形成浓掺杂的源漏外延层；
S104：对所述升高源漏极外延区域进行脉冲雷射退火。
下面通过附图2至附图4详细说明本实施例的半导体元件的制造方法。
首先，如图2所示，执行步骤S101，提供具有假栅极20的基板10。
本实施例中，所述基板10为硅基板，其上具有鳍型半导体15和浅沟渠隔离(STI)25等结构。以提供后续升高源漏极外延区域的生长，该假栅极20可以参考现有技术中的后栅极(gate last)工艺中的常见选择。
在其他的实施例中，所述基板10可以是绝缘层覆硅(SOI)、SixGe1-x(0<x<1)于绝缘层覆硅上、SixGe1-x(0<x<1)于硅上、锗(Ge)、砷化镓(GaAs)、磷化铟(InP)、锑化铟(InSb)、铟镓砷(InGaAs)、铝镓砷(AlGaAs)或铟铝砷(InAlAs)中的任意一种或其任意组合。
在本步骤之后，还包括对所述基板10进行清洗等常规过程，此处不进行详述。
接着，如图3所示，执行步骤S102，在该基板10上假栅极20进行升高源漏极外延区域的第一次掺杂以形成淡掺杂的源漏外延层30。
具体的，该第一次掺杂可以使用原位(in-situ)气相外延沉积工艺。本实施例中，所述第一次掺杂的杂质是N型杂质，所述N型杂质可以是砷化氢(AsH3)、磷化氢(PH3)或者其组合。而在另一实施例中，所述第一次掺杂的杂质是P型杂质，所述P型杂质可以是乙硼烷(diborane)。优选的，该第一次掺杂的浓度范围在1.0E17原子/cm3至5.0E18原子/cm3之间。
优选的，该气相外延沉积工艺的反应温度范围为800℃-1100℃，持续时间为10分钟-2000分钟，获得淡掺杂源漏外延层30的厚度范围为10nm-5000nm。
依据实际需求，可以对反应气体的种类、反应温度及时间进行灵活调整，以获得符合工艺需求的淡掺杂源漏外延层30。
之后，如图4所示，执行步骤S103，在该基板10上假栅极20进行升高源漏极外延区域的第二次掺杂以形成浓掺杂的源漏外延层35于之前形成的淡掺杂的源漏外延层30之外侧。
具体的，该第二次掺杂也可以使用原位(in-situ)气相外延沉积工艺。类似地，本实施例中，所述第二次掺杂的杂质是N型杂质，所述N型杂质可以是砷化氢(AsH3)、磷化氢(PH3)或者其组合。而在另一实施例中，所述第二次掺杂的杂质是P型杂质，所述P型杂质可以是乙硼烷(diborane)。优选的，该第二次掺杂的浓度范围在5.0E18原子/cm3至2.0E19原子/cm3之间。
优选的，在该气相外延沉积工艺的反应温度范围为800℃-1100℃，持续时间为10分钟-2000分钟，获得的浓掺杂源漏外延层35的厚度范围为10nm-5000nm，且此浓掺杂源漏外延层35的厚度小于淡掺杂源漏外延层30的厚度。
依据实际需求，可以对反应气体的种类、反应温度及时间进行灵活调整，以获得符合工艺需求的浓掺杂源漏外延层35。
最后，执行步骤S104，在完成升高源漏外延层的掺杂步骤之后，还可以选择性地进行脉冲雷射退火步骤，以进一步活化杂质并且不会改变原本形成之源漏外延层的形状。所述脉冲雷射退火的温度范围介于1200℃至1400℃之间，持续时间为0.0001秒-10秒。
显然，本领域的技术人员可以对本发明进行各种修改和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些修改和变型在内。

Claims (10)

1.一种半导体结构的形成方法，其特征在于，包括：
提供一具有假栅极的基板；
在该基板的假栅极进行升高源漏极外延区域的第一次原位掺杂以形成淡掺杂的源漏外延层；以及
在该基板的假栅极进行升高源漏极外延区域的第二次原位掺杂以形成浓掺杂的源漏外延层。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，在完成所述升高源漏极外延区域的两次掺杂之后，还包括：对所述升高源漏极外延区域进行脉冲雷射退火。
3.如申请专利范围第2项所述的半导体结构的形成方法，其特征在于，所述源漏外延层的形状在所述脉冲雷射退火之后保持不变。
4.如权利要求1所述的半导体结构的形成方法，其特征在于，所述基板包含硅、绝缘层覆硅、锗硅于绝缘层覆硅上、锗硅于硅上、锗、砷化镓、磷化铟、锑化铟、铟镓砷、铝镓砷或铟铝砷中的任意一种或其任意组合。
5.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一次原位掺杂和第二次原位掺杂是植入N型杂质，所述N型杂质是砷化氢或磷化氢的任意一种或其组合。
6.如权利要求1所述的半导体结构的形成方法，其特征在于，其中所述第一次原位掺杂和第二次原位掺杂是植入P型杂质，所述P型杂质是乙硼烷。
7.如权利要求1所述的半导体结构的形成方法，其特征在于，所述第一次原位掺杂的浓度范围在1.0E17原子/cm3至5.0E18原子/cm3之间。
8.如权利要求1所述的半导体结构的形成方法，其特征在于，其中所述第二次原位掺杂的浓度范围在5.0E18原子/cm3至2.0E19原子/cm3之间。
9.如权利要求2所述的半导体结构的形成方法，其特征在于，所述脉冲雷射退火的温度范围在1200℃到1400℃之间。
10.一种由权利要求1至9中任一项所述的半导体结构的形成方法获得的半导体结构，其特征在于，包括：
一半导体基板，一鳍型半导体结构形成于该半导体基板上；
淡掺杂的源漏外延层；以及
浓掺杂的源漏外延层。
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