TW201803417A - Printed circuit board and mthod for manufacturing same - Google Patents

Abstract

A printed circuit board (PCB) includes a first sub PCB and a second sub PCB. The second sub PCB is bonded to the first sub PCB via an adhesive layer. The first sub PCB includes a first wire layer. The second sub PCB includes a second wire layer corresponding to the first wire layer. A plurality of conductive particles is distributed in the adhesive layer. Each of the conductive particles is electrical insulation from other. The conductive particles prick the adhesive layer and itself rupture to electrically connect the first wire layer and the second wire layer. The first wire layer and the second wire layer cooperatively form a wire layer of the PCB. A thickness of the wire layer of the PCB is equal to a combine of a thickness of the first wire layer, a thickness of the adhesive layer, and a thickness of the second wire layer.

Description

Circuit board and circuit board manufacturing method

The invention relates to a circuit board and a method for manufacturing a circuit board.

With the development of electronic technology, electronic products are gradually miniaturized, the wiring density of circuit boards is gradually increased, and the space between the wires of the circuit board (line distance) is gradually reduced. Overload current, the thickness of the conductors (wire thickness) of the circuit board gradually increases. In the prior art, due to the limitation of manufacturing accuracy, the ratio of the line thickness to the line pitch of the circuit board is constant. When the line pitch is constant, increasing the ratio of the line thickness to the line pitch can easily cause a short circuit due to incomplete etching.

In view of this, it is necessary to provide a circuit board and a circuit board manufacturing method capable of solving the above technical problems.

A circuit board includes a first sub-circuit board and a second sub-circuit board bonded to the first sub-circuit board by an adhesive layer, the first sub-circuit board includes a first circuit pattern, and the second The sub circuit board includes a second circuit pattern corresponding to the first circuit pattern. The adhesive layer is dispersed with electrically independent conductive particles. The conductive particles pierce the adhesive layer and rupture. The circuit pattern and the second circuit pattern are electrically connected to form a circuit pattern of the circuit board by the conductive particles that are broken in the adhesive layer. The thickness of the circuit pattern of the circuit board is equal to the thickness of the first circuit pattern, The sum of the thicknesses of the adhesive layer and the second circuit pattern.

A method for making a circuit board includes steps:

Making a first sub-circuit board and a second sub-circuit board, the first sub-circuit board including a first circuit pattern, and the second sub-circuit board including a second circuit pattern corresponding to the first circuit pattern;

Providing an adhesive layer, in which electrically independent conductive particles are dispersed;

Stacking the first sub circuit board, the adhesive layer, and the second sub circuit board, the adhesive layer is disposed between the first sub circuit board and the second sub circuit board, the A first line pattern corresponding to the second line pattern; and

Applying pressure causes the first sub-circuit board to adhere to the second sub-circuit board through the adhesive layer, the conductive particles pierce the adhesive layer and break, and the first circuit pattern and the The second circuit pattern is electrically connected to the circuit pattern of the circuit board by the electrically conductive cracked conductive particles in the adhesive layer. The thickness of the circuit pattern of the circuit board is equal to the thickness of the first circuit pattern and the adhesive. The sum of the thickness of the adhesive layer and the second circuit pattern.

Compared with the prior art, the circuit board and the circuit board manufacturing method provided by the present invention, because the first sub circuit board includes a first circuit pattern, and the second sub circuit board includes a first circuit pattern corresponding to the first circuit pattern. Two circuit patterns so that the line spacing of the circuit board is constant, and the first circuit pattern and the second circuit pattern are bonded by an adhesive layer, and are electrically conductive by conductive particles in the adhesive layer. Because the first sub-circuit board and the second sub-circuit board can be connected under the limitation of the manufacturing accuracy of the prior art, so that the line thickness of the circuit board can be increased while avoiding endless etching. The ratio of the line thickness to the line pitch of the circuit board can be further increased.

FIG. 1 is a schematic partial perspective view of a circuit board provided by a specific embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a first sub-circuit board and a second sub-circuit board manufactured by the present invention.

FIG. 3 is a schematic cross-sectional view of a substrate provided by the present invention.

FIG. 4 is a schematic cross-sectional view of the copper foil layer of FIG. 3 after forming the first original copper layer of the first circuit pattern.

5 is a schematic cross-sectional view after a photosensitive material layer is formed on the first original copper layer of FIG. 4.

6 is a schematic cross-sectional view of the photosensitive material layer of FIG. 5 after forming the first dielectric layer and removing a portion of the photosensitive material layer corresponding to the first original copper layer.

FIG. 7 is a schematic cross-sectional view after a first copper plating layer is formed on the first original copper layer of FIG. 6.

FIG. 8 is a schematic cross-sectional view of an adhesive layer provided by the present invention.

9 is a schematic cross-sectional view of the first sub-circuit board and the second sub-circuit board in FIG. 2 after being stacked with the adhesive layer in FIG. 8.

FIG. 10 is a schematic cross-sectional view of the first sub-circuit board, the adhesive layer, and the second sub-circuit board stacked in FIG. 9 after pressure is applied.

FIG. 11 is a schematic cross-sectional view of forming a first solder resist layer and a second solder resist layer on the first sub circuit board and the second sub circuit board of FIG. 10, respectively.

The circuit board and the method for manufacturing the circuit board provided by the present invention are further described below in combination with specific embodiments.

Referring to FIG. 1, a circuit board 100 provided by a specific embodiment of the present invention includes a first sub-circuit board 11, an adhesive layer 14, and a second sub-circuit board 17. The circuit board 100 can be used for a rigid-flex board.

The first sub-circuit board 11 includes a first dielectric layer 111 and a first circuit pattern 115.

The first dielectric layer 111 includes a first surface 112 and a second surface 113 that are parallel and opposite to each other. The first circuit pattern 115 is embedded in the first dielectric layer 111. Opposite sides of the first circuit pattern 115 are exposed from the first dielectric layer 111. In this embodiment, the first circuit pattern 115 includes a first original copper layer 116 and a first copper plating layer 117. The first original copper layer 116 is exposed from the first surface 112. The first copper-plated layer 116 is exposed from the second surface 113. In this embodiment, a surface of the first original copper layer 116 far from the first copper plating layer 117 is coplanar with the first surface 112. A surface of the first copper plating layer 117 far from the first original copper layer 116 is coplanar with the second surface 113. The distance between the conductive lines of the first circuit pattern 115 is less than or equal to 50 microns. The line width of the conductive lines of the first line pattern 115 is substantially equal to the interval between the conductive lines of the first line pattern 115. In this embodiment, the distance between the wires of the first line pattern 115 and the line width of the wires of the first line pattern 115 are both equal to 50 microns. The thickness of the first circuit pattern 115 ranges from 9 to 90 microns. In this embodiment, the thickness of the first circuit pattern 115 is 35 micrometers.

The adhesive layer 14 is disposed between the first sub-circuit board 11 and the second sub-circuit board 17. Conductive particles 141 are dispersed in the adhesive layer 14. The conductive particles 141 are electrically independent from each other, so as not to cause a short circuit between the lines. A portion of the conductive particles 141 connected to the first circuit pattern 115 pierces the adhesive layer 14 and breaks. In this embodiment, the particle diameter of each of the conductive particles 141 is equal. A particle size range of the conductive particles 141 is 2-20 microns.

The second sub-circuit board 17 is bonded to the first sub-circuit board 11 through the adhesive layer 14. The second sub-circuit board 17 includes a second dielectric layer 171 and a second circuit pattern 175. The second line pattern 175 corresponds to the first line pattern 115. In this embodiment, the projection of the second circuit pattern 175 on the first sub-circuit board 11 overlaps the first circuit pattern 115. In this embodiment, the projection of the second circuit pattern 175 on the first sub-circuit board 11 completely overlaps with the first circuit pattern 115. The second circuit pattern 175 is electrically connected to the first circuit pattern 115 through the broken conductive particles 141 in the adhesive layer 14 to form a circuit pattern of the circuit board 100.

It can be understood that, in other embodiments, due to the misalignment, the projection of the second circuit pattern 175 on the first sub-circuit board 11 and the first circuit pattern 115 may be offset from 0-20 micrometers.

The second dielectric layer 171 includes a third surface 172 and a fourth surface 173 that are parallel and opposite to each other. The second circuit pattern 175 is embedded in the second dielectric layer 171. Opposite sides of the second circuit pattern 175 are exposed from the second dielectric layer 171. In this embodiment, the second circuit pattern 175 includes a second original copper layer 176 and a second copper plating layer 177. The second original copper layer 176 is exposed from the third surface 171. The second copper-plated layer 176 is exposed from the fourth surface 173. In this embodiment, a surface of the second original copper layer 176 far from the second copper plating layer 177 is coplanar with the third surface 172. A surface of the second copper plating layer 177 far from the second original copper layer 176 is coplanar with the fourth surface 173. In this embodiment, the first surface 112 of the first dielectric layer 111 and the third surface 172 of the second dielectric layer 171 are opposite to each other, and the second original copper layer 176 and the first original copper The layers 116 are opposite to each other. The first surface 112 is bonded to the third surface 172 through the adhesive layer 14. The second original copper layer 176 is bonded to the first original copper layer 116 through the adhesive layer 14, and the conductive particles 141 and the first original copper are broken in the adhesive layer 14. The layer 116 is electrically connected. The spacing between the conductive lines of the second circuit pattern 175 is less than or equal to 50 microns. The line width of the conductive lines of the second line pattern 175 is substantially the same as the spacing between the conductive lines of the second line pattern 175. In this embodiment, the distance between the wires of the second circuit pattern 175 and the line width of the wires of the second circuit pattern 175 are both equal to 50 microns. The thickness of the second circuit pattern 175 ranges from 9 to 90 microns. In this embodiment, the thickness of the second circuit pattern 175 is 35 micrometers. The thickness of the circuit pattern of the circuit board 100 is equal to the sum of the thicknesses of the first circuit pattern 115, the adhesive layer 14, and the second circuit pattern 175 after being laminated. In this embodiment, the thickness of the circuit pattern of the circuit board 100 is about 70 microns. The line width of the wires of the circuit pattern of the circuit board 100 is the same as the line width of the wires of the first circuit pattern 115 and the second circuit pattern 175, which is equal to 50 microns. A resistance value of each of the wires of the circuit pattern of the circuit board 100 having a length of 1002960 micrometers ranges from 4.18Ω to 8.26Ω. In this embodiment, the resistance value of the wires of the circuit pattern of the circuit board 100 with a length of 1002960 microns is 5.01Ω.

It can be understood that, in other embodiments, the second surface 113 of the first dielectric layer 111 and the fourth surface 173 of the second dielectric layer 171 are opposite to each other, and the first copper-plated layer 117 and the first The two copper plating layers 177 are opposite to each other. The second surface 113 is bonded to the fourth surface 173 through the adhesive layer 14. The second copper-plated layer 177 is bonded to the first copper-plated layer 117 through the adhesive layer 14, and the conductive particles 141 and the first copper-plated layer are broken in the adhesive layer 14. The layer 117 is electrically connected.

In this embodiment, the circuit board 100 further includes a first solder resist layer 18 and a second solder resist layer 19. The first solder resist layer 18 is formed on the first sub-circuit board 11. The first solder mask layer 18 covers the first dielectric layer 111 and a part of the first circuit pattern 115. An opening 181 is defined in the first solder resist layer 18. Part of the first circuit pattern 115 is exposed from the opening 181 to form an electrical connection pad 182. In this embodiment, the first solder mask layer 18 covers the second surface 113 of the first dielectric layer 111 and part of the first copper plating layer 117, and part of the first copper plating layer 117 The opening 181 is exposed. The second solder mask layer 19 is formed on the second sub-circuit board 17. The second solder mask layer 19 covers the second dielectric layer 171 and the second circuit pattern 175. In this embodiment, the second solder mask layer 19 covers the fourth surface 173 of the second dielectric layer 171 and the second copper-plated layer 177.

It can be understood that, in other embodiments, the circuit board 100 may include a plurality of sub-circuit boards and a plurality of the adhesive layers 14. The structure of each of the sub circuit boards is the same as that of the first sub circuit board 11. The sub-circuit boards are adhered to each other by the adhesive layer 14, and the circuit patterns of the sub-circuit boards correspond to each other. Preferably, the original copper layers or copper plating layers of two adjacent sub-circuit boards are arranged opposite to each other and bonded and electrically conducted by the adhesive layer 14.

A specific embodiment of the present invention also provides a method for manufacturing a circuit board. The method for manufacturing a circuit board includes the following steps.

In the first step, referring to FIG. 2, a first sub-circuit board 11 and a second sub-circuit board 17 are formed.

The first sub-circuit board 11 includes a first dielectric layer 111 and a first circuit pattern 115.

The first dielectric layer 111 includes a first surface 112 and a second surface 113 that are parallel and opposite to each other. The first circuit pattern 115 is embedded in the first dielectric layer 111. Opposite sides of the first circuit pattern 115 are exposed from the first dielectric layer 111. In this embodiment, the first circuit pattern 115 includes a first original copper layer 116 and a first copper plating layer 117. The first original copper layer 116 is exposed from the first surface 112. The first copper-plated layer 116 is exposed from the second surface 113. In this embodiment, a surface of the first original copper layer 116 far from the first copper plating layer 117 is coplanar with the first surface 112. A surface of the first copper plating layer 117 far from the first original copper layer 116 is coplanar with the second surface 113.

The structure of the second sub-circuit board 17 is substantially the same as the structure of the first sub-circuit board 11. In this embodiment, the second sub-circuit board 17 includes a second dielectric layer 171 and a second circuit pattern 175. The second line pattern 175 corresponds to the first line pattern 115.

The second dielectric layer 171 includes a third surface 172 and a fourth surface 173 that are parallel and opposite to each other. The second circuit pattern 175 is embedded in the second dielectric layer 171. Opposite sides of the second circuit pattern 175 are exposed from the second dielectric layer 171. In this embodiment, the second circuit pattern 175 includes a second original copper layer 176 and a second copper plating layer 177. The second original copper layer 176 is exposed from the third surface 171. The second copper-plated layer 176 is exposed from the fourth surface 173. In this embodiment, a surface of the second original copper layer 176 far from the second copper plating layer 177 is coplanar with the third surface 172. A surface of the second copper plating layer 177 far from the second original copper layer 176 is coplanar with the fourth surface 173.

In this embodiment, the first sub-circuit board 11 and the second sub-circuit board 17 are obtained by the same method. The method for manufacturing the first sub-circuit board 11 and the second sub-circuit board 17 is described below by taking the manufacturing of the first sub-circuit board 11 as an example.

First, referring to FIG. 3, a substrate 101 is provided.

The substrate 101 includes an insulating layer 102 and a copper foil layer 103. The insulating layer 102 may be polyimide or polyester material. In this embodiment, the thickness of the copper foil layer 103 is 18 micrometers.

It can be understood that, in other embodiments, the thickness of the copper foil layer 103 can be adjusted accordingly according to design requirements.

Next, referring to FIG. 2, FIG. 3, and FIG. 4 together, the copper foil layer 103 is fabricated to form a first original copper layer 116 of the first circuit pattern 115.

In this embodiment, a first original copper layer 116 is formed from the copper foil layer 103 to form the first circuit pattern 115 by image transfer and etching.

Next, referring to FIG. 5, a photosensitive material layer 104 is formed on the first original copper layer 116 and the insulating layer 102.

The photosensitive material layer 104 covers the first original copper layer 116 and fills a gap between the first original copper layers 116 to cover the insulation layer 102 from the gap of the first original copper layer 116.

Next, referring to FIG. 5 and FIG. 6 together, fabricating the photosensitive material layer 104 to form a first dielectric layer 111, and removing a portion of the photosensitive material layer 104 corresponding to the first original copper layer 116, To expose the first original copper layer 116.

In this embodiment, the photosensitive material layer 104 is formed into a first dielectric layer 111 by exposure and development, and a part of the photosensitive material layer 104 corresponding to the first original copper layer 116 is removed.

Next, referring to FIG. 7, a first copper plating layer 117 of the first circuit pattern 115 is formed on the exposed first original copper layer 116. In this embodiment, a surface of the first copper plating layer 117 far from the first original copper layer 116 and a surface of the first dielectric layer 111 far from the insulating layer 102 are coplanar. Since the first dielectric layer 111 is formed by exposing and developing the photosensitive material layer 104, and the sidewall of the opening of the photosensitive material layer 104 during exposure and development has good flatness, it is formed on the exposed A sidewall of the first copper plating layer 117 on the first original copper layer 116 is substantially perpendicular to the first original copper layer 116.

Next, referring to FIG. 2 again, the insulating layer 102 is removed to obtain the first sub-circuit board 11.

In this embodiment, the insulating layer 102 is removed by chemical dissolution.

The second step, referring to FIG. 8, provides an adhesive layer 14.

Conductive particles 141 are dispersed in the adhesive layer 14. The conductive particles 141 are electrically independent from each other. In this embodiment, the particle diameter of each of the conductive particles 141 is equal. A particle size range of the conductive particles 141 is 2-20 microns.

Third step, referring to FIG. 9, the first sub-circuit board 11, the adhesive layer 14 and the second sub-circuit board 17 are stacked, and the adhesive layer 14 is disposed on the first sub-circuit board. Between 11 and the second sub-circuit board 17, the first line pattern 115 corresponds to the second line pattern 175.

In this embodiment, during stacking, the first original copper layer 116 of the first circuit pattern 115 and the second original copper layer 176 of the second circuit pattern 175 are opposite to each other. The adhesive layer 14 is sandwiched between the first original copper layer 116 and the second original copper layer 176.

It can be understood that, in other embodiments, when stacked, the first copper plating layer 117 of the first circuit pattern 115 and the second copper plating layer 177 of the second circuit pattern 175 are opposite to each other. The adhesive layer 14 is sandwiched between the first copper-plated layer 117 and the second copper-plated layer 177.

The fourth step, referring to FIG. 10, pressurize the first sub-circuit board 11 to the second sub-circuit board 17 through the adhesive layer 14, and the conductive particles 141 pierce the adhesive The adhesive layer 14 is broken under pressure. The first circuit pattern 115 and the second circuit pattern 175 are electrically connected to form the circuit pattern of the circuit board 100 through the conductive particles 141 in the adhesive layer 14 that are broken. The thickness of the circuit pattern of the circuit board is equal to the sum of the thicknesses of the first circuit pattern 115, the adhesive layer 14, and the second circuit pattern 175.

In this embodiment, the first original copper layer 116 of the first circuit pattern 115 and the second original copper layer 176 of the second circuit pattern 175 are electrically connected through the conductive particles 141 in the adhesive layer 14. . Since the conductive particles 141 in the adhesive layer 14 are electrically independent from each other, a short circuit between the lines is not caused.

Fifth step, referring to FIG. 11, a first solder resist layer 18 is formed on the first sub circuit board 11 and a second solder resist layer 19 is formed on the second sub circuit board 17.

The first solder mask layer 18 covers the first dielectric layer 111 and a part of the first circuit pattern 115. An opening 181 is defined in the first solder resist layer 18. Part of the first circuit pattern 115 is exposed from the opening 181 to form an electrical connection pad 182. In this embodiment, the first solder mask layer 18 covers the second surface 113 of the first dielectric layer 111 and part of the first copper plating layer 117, and part of the first copper plating layer 117 The opening 181 is exposed. The second solder mask layer 19 covers the second dielectric layer 171 and the second circuit pattern 175. In this embodiment, the second solder mask layer 19 covers the fourth surface 173 of the second dielectric layer 171 and the second copper-plated layer 177.

It can be understood that after the first sub-circuit board 11 is bonded to the second sub-circuit board 17 by the adhesive layer 14 under pressure, a first is formed on the first sub-circuit board 11 Before the solder resist layer 18 and the second solder resist layer 19 are formed on the second sub-circuit board 17, the method further includes forming alternate bonding on the first sub-circuit board 11 or the second sub-circuit board 17. A plurality of sub-circuit boards and a plurality of adhesive layers 14. The structure of each of the sub circuit boards is the same as that of the first sub circuit board 11. The original copper layers or copper plating layers of two adjacent sub-circuit boards are disposed opposite to each other and bonded by the adhesive layer 14, and are electrically connected by the conductive particles 141 in the adhesive layer 14.

Compared with the prior art, the circuit board and the circuit board manufacturing method provided by the present invention, because the first sub circuit board includes a first circuit pattern, and the second sub circuit board includes a first circuit pattern corresponding to the first circuit pattern. Two circuit patterns so that the line spacing of the circuit board is constant, and the first circuit pattern and the second circuit pattern are bonded by an adhesive layer, and are electrically conductive by conductive particles in the adhesive layer. Because the first sub-circuit board and the second sub-circuit board can be connected under the limitation of the manufacturing accuracy of the prior art, so that the line thickness of the circuit board can be increased while avoiding endless etching. The ratio of the line thickness to the line pitch of the circuit board can be further increased.

In addition, the first original copper layer is bonded to the second original copper layer through the adhesive layer or the first copper plating layer is bonded to the second copper plating layer through the adhesive layer. Therefore, the warping direction of the circuit board can be consistent, and the problem that the stability of the circuit board product is reduced due to the inconsistent warping direction can be avoided.

In summary, the present invention has indeed met the requirements for an invention patent, and a patent application was filed in accordance with the law. However, the above are only for the preferred embodiments of the present invention and the data listed are for testing and reference, and cannot be used to limit the scope of patent application in this case. For example, those who are familiar with the skills of this case and equivalent modifications or changes made in accordance with the spirit of the present invention should be covered by the following patent applications.

100‧‧‧Circuit Board

11‧‧‧First daughter board

14‧‧‧ Adhesive layer

17‧‧‧Second daughter board

111‧‧‧first dielectric layer

115‧‧‧ the first line graphics

112‧‧‧first surface

113‧‧‧ second surface

116‧‧‧The first original copper layer

117‧‧‧The first copper plating

141‧‧‧ conductive particles

171‧‧‧second dielectric layer

175‧‧‧second line graphics

172‧‧‧ Third surface

173‧‧‧ Fourth surface

176‧‧‧Second primary copper layer

177‧‧‧Second copper plating

18‧‧‧The first solder mask

19‧‧‧Second solder mask

181‧‧‧ opening

182‧‧‧electrical connection pad

101‧‧‧ substrate

102‧‧‧ Insulation

103‧‧‧ Copper foil layer

104‧‧‧Photosensitive material layer

no

100‧‧‧Circuit Board

11‧‧‧First daughter board

14‧‧‧ Adhesive layer

17‧‧‧Second daughter board

111‧‧‧first dielectric layer

115‧‧‧ the first line graphics

112‧‧‧first surface

113‧‧‧ second surface

116‧‧‧The first original copper layer

117‧‧‧The first copper plating

141‧‧‧ conductive particles

171‧‧‧second dielectric layer

175‧‧‧second line graphics

172‧‧‧ Third surface

173‧‧‧ Fourth surface

176‧‧‧Second primary copper layer

177‧‧‧Second copper plating

18‧‧‧The first solder mask

19‧‧‧Second solder mask

181‧‧‧ opening

182‧‧‧electrical connection pad

Claims (10)

A circuit board includes a first sub-circuit board and a second sub-circuit board bonded to the first sub-circuit board by an adhesive layer, the first sub-circuit board includes a first circuit pattern, and the second The sub circuit board includes a second circuit pattern corresponding to the first circuit pattern. The adhesive layer is dispersed with electrically independent conductive particles. The conductive particles pierce the adhesive layer and rupture. The circuit pattern and the second circuit pattern are electrically connected to form a circuit pattern of the circuit board by the conductive particles that are broken in the adhesive layer. The thickness of the circuit pattern of the circuit board is equal to the thickness of the first circuit pattern, The sum of the thicknesses of the adhesive layer and the second circuit pattern. The circuit board according to claim 1, wherein the first circuit pattern includes a first original copper layer, the second circuit pattern includes a second original copper layer, and the second original copper layer is passed through the adhesive layer. The conductive particles in the adhesive layer that pierce the adhesive layer are electrically connected to the first original copper layer. The circuit board according to claim 1, wherein the first circuit pattern includes a first copper plating layer, the second circuit pattern includes a second copper plating layer, and the second copper plating layer is passed through the adhesive The conductive particles in the adhesive layer that pierce the adhesive layer are electrically connected to the first copper-plated layer. The circuit board according to claim 1, wherein the first sub-circuit board further includes a first dielectric layer, the first circuit pattern is embedded in the first dielectric layer, and the first circuit Opposite sides of the pattern are exposed from the first dielectric layer, the second sub-circuit board further includes a second dielectric layer, and the second circuit pattern is embedded in the second dielectric layer, Opposite sides of the second circuit pattern are exposed from the second dielectric layer. The circuit board according to claim 1, wherein the circuit board further includes a first solder resist layer and a second solder resist layer, the first solder resist layer is formed on the first circuit pattern, and the first Two solder resist layers are formed on the second circuit pattern. A method for making a circuit board includes steps:
Making a first sub-circuit board and a second sub-circuit board, the first sub-circuit board including a first circuit pattern, and the second sub-circuit board including a second circuit pattern corresponding to the first circuit pattern;
Providing an adhesive layer, in which electrically independent conductive particles are dispersed;
Stacking the first sub circuit board, the adhesive layer, and the second sub circuit board, the adhesive layer is disposed between the first sub circuit board and the second sub circuit board, the A first circuit pattern corresponding to the second circuit pattern; and applying pressure to make the first sub-circuit board adhere to the second sub-circuit board through the adhesive layer, and the conductive particles pierce the The adhesive layer is broken under pressure, and the first circuit pattern and the second circuit pattern are electrically connected to form a circuit pattern of the circuit board by the electrically conductive cracked particles in the adhesive layer. The thickness of the line pattern is equal to the sum of the thicknesses of the first line pattern, the adhesive layer, and the second line pattern. The method of manufacturing a circuit board according to claim 6, wherein the first sub-circuit board further includes a first dielectric layer, the first circuit pattern is embedded in the first dielectric layer, and the first Opposite sides of a circuit pattern are exposed from the first dielectric layer, the first circuit pattern includes a first original copper layer and a first copper plating layer, and the second sub circuit board further includes a second A dielectric layer, the second circuit pattern is embedded in the second dielectric layer, opposite sides of the second circuit pattern are exposed from the second dielectric layer, and the second circuit pattern It includes a second original copper layer and a second copper-plated layer. The method for manufacturing a circuit board according to claim 7, wherein the steps of manufacturing the first sub-circuit board and the second sub-circuit board include the following steps:
Provide a substrate, including a copper foil layer;
Forming the original copper layer of the circuit pattern by the copper foil layer through image transfer and etching treatment;
Forming a photosensitive material layer on the original copper layer of the circuit pattern, the photosensitive material layer covering the original copper layer of the circuit pattern and filling a gap between the original copper layer of the circuit pattern;
Fabricating the photosensitive material layer to form a dielectric layer, and removing a portion of the photosensitive material layer corresponding to the original copper layer of the circuit pattern to expose the original copper layer of the circuit pattern; and A plating layer is formed on the original copper layer of the circuit pattern to obtain the circuit pattern. The method for manufacturing a circuit board according to claim 7, wherein when the first sub-circuit board, the adhesive layer, and the second sub-circuit board are stacked, the first original copper layer and the first sub-circuit board are stacked. The two original copper layers are opposite to each other, and the adhesive layer is sandwiched between the first original copper layer and the second original copper layer. The method for manufacturing a circuit board according to claim 7, wherein when the first sub-circuit board, the adhesive layer, and the second sub-circuit board are stacked, the first original copper layer and the first sub-circuit board are stacked. The two original copper layers are opposite to each other, and the adhesive layer is sandwiched between the first original copper layer and the second original copper layer.