TW201801267A - Chip package and manufacturing method thereof - Google Patents

Abstract

A chip package including a substrate, a chip, a thermal diffusion layer and a conductive wire is provided in the present disclosure. A surface of the chip is attached with a surface of the substrate. The thermal diffusion layer covers the other surface of the chip, and a peripheral of the thermal diffusion layer is extended to a peripheral of the chip. A notch through the thermal diffusion layer is provided on the thermal diffusion layer. The conductive wire is connected between the substrate and the chip through the notch. Thereby, heat generated by the chip can be uniformly spread to the entire chip package.

Description

Chip package and manufacturing method thereof

The invention relates to a chip package, especially a chip package with a thermal diffusion layer and a manufacturing method thereof.

Existing chip packages, such as CPUs (Central Processing Units) or GPUs (Graphics Processing Units), generate a lot of heat energy when they work, so it is necessary to install heat dissipation devices on the chip packages Cool the chip package. The general heat dissipation system absorbs the heat energy generated by the chip package into the heat dissipation system by means of heat conduction, and then dissipates the heat energy into the air by means of heat convection. In order to optimize the heat transfer efficiency between the chip package and the heat dissipation system, the heat dissipation system is generally configured with a flat surface, and can be attached to another flat surface of the chip package, and then conduct heat conduction through this contact surface.

Generally speaking, the chip is not a uniform heating body, and there is usually a point of heat generation. The contact surface of the heat dissipation system and the chip package often deviates from the heat point. Between the heat transfer efficiency.

In view of this, the present inventors have made great efforts to study the above-mentioned prior art and cooperate with the application of academic principles, and try their best to solve the above-mentioned problems, which becomes the improvement goal of the present inventors.

The invention provides a wafer package with a thermal diffusion layer and a manufacturing method thereof.

The invention provides a chip package including a substrate, a chip, a thermal diffusion layer and a wire. One side of the wafer is attached to one side of the substrate; the thermal diffusion layer covers the other side of the wafer, and the edge of the thermal diffusion layer extends to the edge of the wafer, and the thermal diffusion layer has a gap therethrough. The wire is connected between the substrate and the wafer through the gap.

Preferably, the thermal diffusion layer contains a heat conductive material. The thermally conductive material is sheet-like graphene. One side of the thermal diffusion layer is provided with adhesive and attached to the wafer. The chip package further includes a packaging structure, and the packaging structure covers the chip. The thermal diffusion layer is thermally connected to the packaging structure. The chip package further includes a protective layer covering the thermal diffusion layer. The notch extends from the thermal diffusion layer through the protective layer.

The invention also provides a method for manufacturing a chip package, which includes the steps of: providing a first wafer and a thermal diffusion layer, and attaching one side of the thermal diffusion film to one side of the first wafer; Multiple notches are formed on the film; a second wafer is provided, and the other side of the thermal diffusion film is attached to one side of the second wafer; the second wafer is cut to form a plurality of chips, and the thermal diffusion film is cut at the same time Cut to form a plurality of thermal diffusion layers attached to each wafer; provide a substrate and set the wafer on the substrate; provide a plurality of wires corresponding to the notches, and connect each wire between the substrate and the wafer through the corresponding notches.

Preferably, the manufacturing method of the chip package further includes: providing a packaging structure, and covering the chip with the packaging structure. The thermal diffusion film contains a thermally conductive material. The thermally conductive material is sheet-like graphene. An adhesive is placed on the thermal diffusion film and the second wafer is attached. The manufacturing method of the chip package further includes: removing the first wafer from the thermal diffusion film. The manufacturing method of the chip package includes: simultaneously cutting the first wafer to form a plurality of protective layers attached to each thermal diffusion layer.

The chip package of the present invention is provided with a thermal diffusion layer made of sheet-like graphene on the chip, so heat concentration can be avoided and the heat transfer efficiency of the chip package to the outside can be reduced. The manufacturing method is to attach the thermal diffusion film to the second wafer before cutting the second wafer to form a wafer, so there is no need to separately attach each thermal diffusion layer to each wafer.

Referring to FIG. 1, a first embodiment of the present invention provides a chip package including a substrate 100, a chip 200, a thermal diffusion layer 300, at least one wire 400, and a packaging structure 500.

In this embodiment, the substrate 100 is preferably a circuit board. The wafer 200 is disposed on one side of the substrate 100 of the wafer 200, and this side of the substrate 100 is preferably attached to one side of the wafer 200.

In this example, the thermal diffusion layer 300 is preferably in the form of a thin film, and the thermal diffusion layer 300 has a heat conductive material inside. The thermally conductive material is sheet-like graphene, which has good planar thermal conductivity characteristics. An adhesive 310 is preferably disposed on one side of the thermal diffusion layer 300, and the thermal diffusion layer 300 can be attached to the other side of the wafer 200 by the adhesive 310 so that the thermal diffusion layer 300 covers the wafer 200. The edge of the thermal diffusion layer 300 extends to the edge of the wafer 200, and at least one notch 301 is formed through the thermal diffusion layer 300. In this embodiment, the thermal diffusion layer 300 is preferably provided with a plurality of notches 301, and the structure of each notch 301 is the same. The notch 301 may be in the form of a hole, or may be in the form of a groove extending to the edge of the thermal diffusion layer 300, and the type is limited by the present invention.

In this embodiment, a protective layer 320 is preferably attached to the other surface of the thermal diffusion layer 300, and the notch 301 extends from the thermal diffusion layer 300 through the protective layer 320.

The wires 400 are disposed corresponding to the notches 301. In this embodiment, the chip package of the present invention preferably includes a plurality of wires 400 corresponding to the notches 301. One end of each wire 400 is connected to the substrate 100, and the other end of the wire 400 is connected to the chip 200 through the corresponding notch 301. Therefore, the wires 400 can be used to electrically connect the chip 200 to the substrate 100.

The packaging structure 500 covers the wafer 200 to protect the wafer 200. In the present embodiment, the packaging structure 500 is molded on the substrate 100 to cover the wafer 200, and at the same time, the thermal diffusion layer 300 is covered to heat the thermal diffusion layer 300 connection. The protective layer 320 can prevent the sheet-shaped graphene in the thermal diffusion layer 300 from being damaged during the molding process of the packaging structure 500.

Referring to FIG. 2, a second embodiment of the present invention provides a chip package including a substrate 100, a chip 200, a thermal diffusion layer 300, at least one wire 400, and a packaging structure 500. The structure of the chip package of this embodiment is as large as that of the foregoing first embodiment, so the same will not be repeated here. The differences between this embodiment and the first embodiment will be described in detail later.

In this embodiment, the protective layer 320 is not provided on the thermal diffusion layer 300. The packaging structure 500 is a cover covering the substrate 100, and the packaging structure 500 covers the wafer 200. The thermal diffusion layer 300 is thermally connected to the packaging structure 500. The thermal diffusion layer 300 and the packaging structure 500 may be directly attached and thermally connected or filled with a thermally conductive medium 510 (such as thermally conductive adhesive or Thermal pad) and thermal connection.

Referring to FIG. 3, a third embodiment of the present invention provides a method for manufacturing a chip package, which is used to manufacture the chip package as described in the foregoing first embodiment. In this embodiment, the steps of the manufacturing method of the chip package of the present invention are described as follows:

Referring to FIGS. 3 to 5, in step a of this embodiment, a second wafer 10 and a thermal diffusion film 20 are first provided, and one side of the thermal diffusion film 20 is attached to the second wafer 10 one side;

Referring to FIGS. 3 and 6, in step b following step a, a plurality of notches 301 are formed in the thermal diffusion film 20. The notches 301 in this step are preferably hole-shaped, and preferably can be directly processed by a processing tool Processing through the second wafer 10 and the thermal diffusion film 20 facilitates processing to form the notch 301.

Referring to FIGS. 3 and 7, in step c following step b, a second wafer 30 is provided. Then, an adhesive 310 is laid on the other surface of the thermal diffusion film 20, and the surface is attached to one surface of the second wafer 30 by the adhesive 310. Thereby, the thermal diffusion film 20 is covered and disposed on the second wafer 30.

3 and 8, in step d following step c, the positions corresponding to the notches 301 are cut, the second wafer 30 is cut to form a plurality of wafers 200, and the thermal diffusion film 20 is also cut to form A plurality of thermal diffusion layers 300 attached to each wafer 200, and each thermal diffusion layer 300 has at least one notch 301, respectively. According to different cutting positions, the gaps 301 on each thermal diffusion layer 300 have different shapes. When the gaps 301 on the thermal diffusion film 20 are not cut, the gaps 301 on each thermal diffusion layer 300 are hole-shaped; When the gap 301 on the thermal diffusion film 20 is cut, the gap 301 on each thermal diffusion layer 300 is a groove shape extending to the edge of the thermal diffusion layer 300, the present invention does not limit the gap 301 on each thermal diffusion layer 300 Type. Furthermore, preferably, the first wafer 10 is also cut to form a plurality of protective layers 320 covering each thermal diffusion layer 300.

Referring to FIGS. 3 and 9, in step e following step d, at least one substrate 100 is provided and the wafer 200 is disposed on the substrate 100. The present invention does not limit the arrangement method. A wafer 200 can be disposed on a substrate 100 Alternatively, a plurality of wafers 200 may be provided on the same substrate 100.

Referring to FIG. 3 and FIG. 10, in step f following step e, a plurality of wires 400 are provided corresponding to each notch 301, one end of each wire 400 is connected to the substrate 100, and the other end of each wire 400 is passed through the corresponding notch 301 is connected to the wafer 200, thereby electrically connecting the wafer 200 to the substrate 100.

Referring to FIGS. 3 and 1, in step g following step f, a packaging structure 500 is provided, and the packaging structure 500 is coated on the wafer 200. In this embodiment, the substrate 100 and the wafer 200 are preferably placed in a mold to mold the packaging structure 500 on the substrate 100 to cover the wafer 200. During the molding process, the protective layer 320 can protect the thermal diffusion layer 300 to prevent the high-pressure plastic injected into the mold from damaging the structure of the sheet-like graphene in the thermal diffusion layer 300.

The fourth embodiment of the present invention provides a method for manufacturing a chip package, which is used to manufacture the chip package as described in the foregoing second embodiment. The steps in this embodiment are as large as those in the foregoing third embodiment, so the same will not be repeated here. The differences between this embodiment and the third embodiment will be described in detail later.

Referring to FIGS. 3 and 11, in this embodiment, after step c is completed, step h may be selectively performed to remove the second wafer 10 from the thermal diffusion film 20. In step d of the subsequent step h, the positions corresponding to the notches 301 are cut, and the second wafer 30 is cut to form a plurality of wafers 200, and at the same time, the thermal diffusion film 20 is cut to form a plurality of sticking to each wafer 200 The thermal diffusion layer 300, and each thermal diffusion layer 300 has at least one notch 301.

Referring to FIGS. 3 and 12, in step e following step d, at least one substrate 100 is provided and the wafer 200 is disposed on the substrate 100. The present invention does not limit the arrangement method. A wafer 200 may be disposed on a substrate 100 Alternatively, a plurality of wafers 200 may be provided on the same substrate 100.

Referring to FIGS. 3 and 13, in step f following step e, a plurality of wires 400 are provided corresponding to each notch 301, one end of each wire 400 is connected to the substrate 100, and the other end of each wire 400 is passed through the corresponding notch 301 is connected to the wafer 200, thereby electrically connecting the wafer 200 to the substrate 100.

Referring to FIGS. 3 and 2, in step g following step f, a packaging structure 500 is provided, and the packaging structure 500 is coated on the wafer 200. In this embodiment, the packaging structure 500 is in the form of a cover. In this step, the packaging structure 500 is covered on the substrate 100 to cover the wafer 200, and the thermal diffusion layer 300 and the packaging structure 500 may be directly attached The thermal connection is also achieved by filling a thermally conductive medium 510 (such as thermally conductive adhesive or thermally conductive pad) between the thermal diffusion layer 300 and the packaging structure 500.

In the chip package of the present invention, the wafer 200 is provided with a thermal diffusion layer 300 made of sheet-like graphene. Therefore, the heat of the wafer 200 can be uniformly diffused to the entire chip package, so the concentration of heat energy can be avoided and the chip package can be reduced. External heat transfer efficiency.

The manufacturing method of the chip package of the present invention attaches the thermal diffusion film 20 to the second wafer 30 before cutting the second wafer 30 to form the wafer 200, so there is no need to separately attach each thermal diffusion layer 300 to the Each wafer 200. The thermal diffusion layer 300 made by this method will extend to the edge of each wafer 200 to completely cover the surface of the wafer 200, so that the wire 400 cannot be connected to the wafer 200. Therefore, a gap 301 needs to be provided in the thermal diffusion layer 300 for the wire 400 to pass through. Therefore, the manufacturing method of the chip package of the present invention can form the notch 301 in the plurality of thermal diffusion layers 300 at a time by means of presetting the thermal diffusion film 20 on the first wafer 10.

The above are only preferred embodiments of the present invention and are not intended to limit the patent scope of the present invention. Other equivalent changes using the patent spirit of the present invention should all fall within the patent scope of the present invention.

10‧‧‧First wafer

20‧‧‧Diffusion film

30‧‧‧Second wafer

100‧‧‧ substrate

200‧‧‧chip

300‧‧‧thermal diffusion layer

301‧‧‧Notch

310‧‧‧ Adhesive

320‧‧‧Protection layer

400‧‧‧Wire

500‧‧‧Package structure

510‧‧‧Heat conduction medium

FIG. 1 is a schematic diagram of a chip package according to a first embodiment of the invention.

2 is a schematic diagram of a chip package according to a second embodiment of the invention.

FIG. 3 is a flow chart of the manufacturing method of the chip package of the present invention.

4 to 7 are schematic steps of the method for manufacturing the chip package of the present invention.

8 to 10 are schematic steps of a method for manufacturing a chip package according to a third embodiment of the invention.

FIG. 11 to FIG. 13 are schematic steps of a method for manufacturing a chip package according to a fourth embodiment of the invention.

100‧‧‧ substrate

200‧‧‧chip

300‧‧‧thermal diffusion layer

301‧‧‧Notch

310‧‧‧ Adhesive

320‧‧‧Protection layer

400‧‧‧Wire

500‧‧‧Package structure

Claims (15)

A chip package includes: a substrate; a chip, one side of the chip is attached to one side of the substrate; a thermal diffusion layer covering the other side of the chip and the edge of the thermal diffusion layer extends to the chip At the edge of the heat dissipation layer, a notch is provided through; and a wire is connected between the substrate and the chip through the notch. The chip package as claimed in claim 1, wherein the thermal diffusion layer contains a heat conductive material. The chip package as claimed in claim 2, wherein the thermally conductive material is sheet-like graphene. The chip package according to claim 1, wherein an adhesive is applied to one side of the thermal diffusion layer and the chip is attached. The chip package as claimed in claim 1, further comprising a packaging structure, which encapsulates the chip. The chip package as claimed in claim 5, wherein the thermal diffusion layer is thermally connected to the package structure. The chip package as claimed in claim 1, further comprising a protective layer covering the thermal diffusion layer. The chip package as claimed in claim 7, wherein the notch extends from the thermal diffusion layer through the protective layer. A method for manufacturing a chip package includes: a) providing a first wafer and a thermal diffusion layer, and attaching one side of the thermal diffusion film to one side of the first wafer; b) at the heat A plurality of notches are formed on the diffusion film; c) a second wafer is provided, and the other side of the thermal diffusion film is attached to one side of the second wafer; d) the second wafer is cut to form a plurality of chips , And at the same time cutting the thermal diffusion film to form a plurality of thermal diffusion layers attached to each wafer; e) providing a substrate and placing the wafer on the substrate; and f) providing a plurality of wires corresponding to the notches, and Each of the wires is connected between the substrate and the wafer through the corresponding notches. The method for manufacturing a chip package as described in claim 9, further includes step g: providing a package structure, and covering the chip with the package structure. The method for manufacturing a chip package as described in claim 9, wherein the thermal diffusion film contains a thermally conductive material. The method for manufacturing a chip package according to claim 11, wherein the thermally conductive material is sheet graphene. The method for manufacturing a chip package according to claim 9, wherein in step c, an adhesive is placed on the thermal diffusion film and the second wafer is attached. The method for manufacturing a chip package according to claim 9, wherein after step c, step h is further included: removing the first wafer from the thermal diffusion film. The method for manufacturing a chip package according to claim 9, wherein in step d, the first wafer is simultaneously cut to form a plurality of protective layers attached to each of the thermal diffusion layers.