TWM529273U - Chip package - Google Patents

Abstract

A chip package including a substrate, a chip, a thermal diffusion layer and a conductive wire is provided in the present disclosure. A surface of the chip is attached with a surface of the substrate. The thermal diffusion layer covers the other surface of the chip, and a peripheral of the thermal diffusion layer is extended to a peripheral of the chip. A notch through the thermal diffusion layer is provided on the thermal diffusion layer. The conductive wire is connected between the substrate and the chip through the notch. Thereby, heat generated by the chip can be uniformly spread to the entire chip package.

Description

Chip package

The present invention relates to a chip package, particularly a chip package having a thermal diffusion layer.

The existing chip package, such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit), generates a large amount of heat during operation, so it is necessary to provide a heat sink on the chip package. Cool the chip package. The general heat dissipation system absorbs the heat energy generated by the chip package into the heat dissipation system by means of heat conduction, and then radiates the heat energy into the air by means of heat convection. In order to optimize the heat transfer efficiency between the chip package and the heat dissipation system, the heat dissipation system is generally provided with a flat surface and can be bonded to another plane of the outer surface of the wafer package, and heat conduction is performed through the contact surface.

In general, the wafer is not a uniform heating element, and there is usually a point of heat generation. The contact surface between the heat dissipation system and the chip package is often offset from the heating point. Therefore, the chip package and the heat dissipation system cannot be improved anyway by improving the heat dissipation system. The heat transfer efficiency between.

In view of this, the creator has made great efforts to solve the above problems by focusing on the above-mentioned prior art, and has devoted himself to the application of the theory, that is, the goal of the creator's improvement.

The present invention provides a chip package having a thermal diffusion layer.

The present invention provides a chip package including a substrate, a wafer, a thermal diffusion layer, and a wire. One side of the wafer is attached to one side of the substrate; the thermal diffusion layer covers the other side of the wafer, and the edge of the thermal diffusion layer extends to the edge of the wafer, and the thermal diffusion layer is provided with a notch therethrough. The wire is connected between the substrate and the wafer through the gap.

Preferably, a thermally conductive material is contained within the thermal diffusion layer. The heat conductive material is flake graphene. An adhesive is disposed on one side of the thermal diffusion layer and the wafer is attached. The chip package further includes a package structure that encapsulates the wafer. The thermal diffusion layer thermally connects the package structure. The chip package further includes a protective layer covering the thermal diffusion layer. The notch extends from the thermal diffusion layer through the protective layer.

In the chip package of the present invention, a thermal diffusion layer made of flake graphene is provided on the wafer, so that heat concentration can be avoided and the external heat transfer efficiency of the chip package can be reduced. The manufacturing method attaches the thermal diffusion film to the second wafer before the wafer is formed by cutting the second wafer, so that it is not necessary to attach the respective thermal diffusion layers to the respective wafers.

Referring to FIG. 1 , a first embodiment of the present invention provides a chip package including a substrate 100 , a wafer 200 , a thermal diffusion layer 300 , at least one wire 400 , and a package structure 500 .

In the embodiment, the substrate 100 is preferably a circuit board. The wafer 200 is disposed on one side of the substrate 100 of the wafer 200, and the face of the substrate 100 preferably conforms to one side of the wafer 200.

In the present example, the thermal diffusion layer 300 is preferably in the form of a film having a thermally conductive material within the thermal diffusion layer 300. The heat conductive material is flake graphene, and the flake graphene has good planar heat conduction characteristics. One side of the thermal diffusion layer 300 is preferably provided with an adhesive 310, and the thermal diffusion layer 300 can be attached to the other side of the wafer 200 by the adhesive 310 so that the thermal diffusion layer 300 covers the wafer 200. The edge of the thermal diffusion layer 300 extends to the edge of the wafer 200, and at least one notch 301 is formed through the thermal diffusion layer 300. In the embodiment, the thermal diffusion layer 300 is preferably provided with a plurality of notches 301, and the structures of the notches 301 are the same. The notch 301 may be in the shape of a hole or a notch extending to the edge of the thermal diffusion layer 300, and the present invention defines its pattern.

In the present embodiment, a protective layer 320 is preferably attached to the other surface of the thermal diffusion layer 300, and the notch 301 extends from the thermal diffusion layer 300 through the protective layer 320.

The wire 400 is disposed corresponding to the notch 301. In the embodiment, the chip package of the present invention preferably includes a plurality of wires 400 corresponding to the notches 301. One end of each of the wires 400 is connected to the substrate 100, and the other end of the wire 400 is connected to the wafer 200 through the corresponding notch 301. Therefore, the wires 200 can be electrically connected to the substrate 100 by the wires 400.

The package structure 500 covers the wafer 200 to protect the wafer 200. In the embodiment, the package structure 500 is molded on the substrate 100 to coat the wafer 200, and simultaneously coats the thermal diffusion layer 300 and is thermally heated with the thermal diffusion layer 300. connection. The protective layer 320 can prevent the flake graphene in the thermal diffusion layer 300 from being damaged in the molding process of the package structure 500.

Referring to FIG. 2 , a second embodiment of the present invention provides a chip package including a substrate 100 , a wafer 200 , a thermal diffusion layer 300 , at least one wire 400 , and a package structure 500 . The configuration of the chip package of the present embodiment is as large as the first embodiment described above, and therefore the same points are not described herein again. The differences between the present embodiment and the first embodiment are described in detail below.

In the present embodiment, the protective layer 320 is not disposed on the thermal diffusion layer 300. The package structure 500 is a cover that covers the substrate 100, and the package structure 500 covers the wafer 200. The thermal diffusion layer 300 is thermally connected to the package structure 500. The thermal diffusion layer 300 and the package structure 500 may be directly attached and thermally connected or may be filled with a heat conductive medium 510 (for example, thermal paste or between the thermal diffusion layer 300 and the package structure 500). Thermal pad) and hot connection.

Referring to FIG. 3, the steps of the method for fabricating the chip package described in the foregoing first embodiment are respectively described as follows:

Referring to FIG. 3 to FIG. 5, in step a of the embodiment, a second wafer 10 and a thermal diffusion film 20 are first provided, and one side of the thermal diffusion film 20 is attached to the second wafer 10. one side;

Referring to FIG. 3 and FIG. 6, in step b of the subsequent step a, a plurality of notches 301 are formed in the thermal diffusion film 20. The notches 301 in this step are preferably hole-shaped, and preferably can be directly processed by the processing tool. The second wafer 10 and the thermal diffusion film 20 are processed to form a notch 301.

Referring to FIG. 3 and FIG. 7, in the step c of the subsequent step b, a second wafer 30 is provided. Then, an adhesive 310 is disposed on the other surface of the thermal diffusion film 20, and the surface is attached to one surface of the second wafer 30 by the adhesive 310. Thereby, the thermal diffusion film 20 is covered and disposed on the second wafer 30.

Referring to FIG. 3 and FIG. 8 , in step d of the subsequent step c, the positions of the notches 301 are cut, the second wafer 30 is cut to form a plurality of wafers 200, and the thermal diffusion film 20 is also cut. The plurality of thermal diffusion layers 300 are attached to each of the wafers 200, and each of the thermal diffusion layers 300 has at least one notch 301. The notch 301 on each of the thermal diffusion layers 300 has a different shape depending on the cutting position. When the notch 301 on the thermal diffusion film 20 is not cut, the notch 301 on each thermal diffusion layer 300 is in the shape of a hole; When the notch 301 is cut into the thermal diffusion film 20, the notch 301 on each of the thermal diffusion layers 300 is a notch extending to the edge of the thermal diffusion layer 300. The present invention does not limit the notch 301 on each thermal diffusion layer 300. The type. Moreover, it is preferable that the first wafer 10 is also cut to form a plurality of protective layers 320 covering the respective heat diffusion layers 300.

Referring to FIG. 3 and FIG. 9, in step e of the subsequent step d, at least one substrate 100 is provided and the wafer 200 is disposed on the substrate 100. The present invention does not limit the arrangement thereof, and a wafer 200 can be disposed on a substrate 100. It is also possible to arrange a plurality of wafers 200 on the same substrate 100.

Referring to FIG. 3 and FIG. 10, in step f of the subsequent step e, a plurality of wires 400 are provided corresponding to the notches 301, one end of each wire 400 is connected to the substrate 100, and the other end of each wire 400 is passed through a corresponding gap. The 301 is connected to the wafer 200, whereby the wafer 200 is electrically connected to the substrate 100.

Referring to FIG. 3 and FIG. 1, in a step g following the step f, a package structure 500 is provided, and the package structure 500 is wrapped around the wafer 200. In the present embodiment, the substrate 100 and the wafer 200 are preferably placed in a mold to mold the package structure 500 on the substrate 100 to coat the wafer 200. In the molding process, the protective layer 320 can protect the thermal diffusion layer 300 from the high-pressure plastic injected into the mold to damage the structure of the flake graphene in the thermal diffusion layer 300.

The method of manufacturing the chip package described in the foregoing second embodiment is as large as the method of manufacturing the chip package of the first embodiment described above, and the differences are detailed later.

Referring to FIG. 3 and FIG. 11 , in the embodiment, after step c is completed, step h may be selectively performed to remove the second wafer 10 from the thermal diffusion film 20 . In the step d following the step h, the positions of the notches 301 are cut, the second wafer 30 is cut to form a plurality of wafers 200, and the thermal diffusion film 20 is cut to form a plurality of wafers 200 attached to each wafer 200. The heat diffusion layer 300, and each of the heat diffusion layers 300 has at least one notch 301.

Referring to FIG. 3 and FIG. 12, in step e of the subsequent step d, at least one substrate 100 is provided and the wafer 200 is disposed on the substrate 100. The present invention is not limited to the arrangement thereof, and a wafer 200 may be disposed on a substrate 100. It is also possible to arrange a plurality of wafers 200 on the same substrate 100.

Referring to FIG. 3 and FIG. 13, in step f of the subsequent step e, a plurality of wires 400 are provided corresponding to the notches 301, one end of each wire 400 is connected to the substrate 100, and the other end of each wire 400 is passed through a corresponding gap. The 301 is connected to the wafer 200, whereby the wafer 200 is electrically connected to the substrate 100.

Referring to FIGS. 3 and 2, in a step g following the step f, a package structure 500 is provided, and the package structure 500 is wrapped around the wafer 200. In this embodiment, the package structure 500 is in the form of a cover. In this step, the package structure 500 is covered on the substrate 100 to cover the wafer 200, and the thermal diffusion layer 300 and the package structure 500 may be directly attached. The thermal connection is also thermally connected by filling a thermally conductive medium 510 (eg, a thermally conductive paste or a thermal pad) between the thermal diffusion layer 300 and the package structure 500.

In the wafer package of the present invention, the wafer 200 is provided with a thermal diffusion layer 300 made of flake graphene, so that the heat generated by the wafer 200 can be uniformly diffused to the entire chip package, so that the thermal energy concentration can be avoided and the chip package can be reduced. External heat transfer efficiency.

In the method of manufacturing the chip package of the present invention, the thermal diffusion film 20 is attached to the second wafer 30 before the wafer 200 is formed by cutting the second wafer 30, so that it is not necessary to attach the respective thermal diffusion layers 300 to Each wafer 200. The thermal diffusion layer 300 formed in this way extends to the edge of each wafer 200 to completely cover the surface of the wafer 200, so that the wire 400 cannot be connected to the wafer 200, so that a gap 301 is required to be provided in the thermal diffusion layer 300 for the wire 400 to pass. Therefore, the manufacturing method of the chip package of the present invention can form the notch 301 on the plurality of thermal diffusion layers 300 at a time by means of presetting the thermal diffusion film 20 on the first wafer 10.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the patents of the present invention. Other equivalent variations of the patent spirit using the present invention are all within the scope of the patent.

10‧‧‧First wafer

20‧‧‧ Thermal diffusion film

30‧‧‧second wafer

100‧‧‧Substrate

200‧‧‧ wafer

300‧‧‧ Thermal diffusion layer

301‧‧‧ gap

310‧‧‧Adhesive

320‧‧‧Protective layer

400‧‧‧ wire

500‧‧‧Package structure

510‧‧‧ Thermal medium

1 is a schematic view of a chip package of the first embodiment of the present invention.

2 is a schematic view of a chip package of the second embodiment of the present invention.

3 is a flow chart of a method of fabricating the chip package of the present invention.

4 to 7 are schematic diagrams showing the steps of a method of manufacturing the chip package of the present invention.

8 to 10 are schematic diagrams showing the steps of a method of manufacturing a chip package in the first embodiment of the present invention.

11 to 13 are schematic diagrams showing the steps of a method of manufacturing a chip package in the second embodiment of the present invention.

100‧‧‧Substrate

200‧‧‧ wafer

300‧‧‧ Thermal diffusion layer

301‧‧‧ gap

310‧‧‧Adhesive

320‧‧‧Protective layer

400‧‧‧ wire

500‧‧‧Package structure

Claims (8)

A chip package comprising: a substrate; a wafer having one side of the wafer attached to one side of the substrate; a thermal diffusion layer covering the other side of the wafer and an edge of the thermal diffusion layer extending to the wafer An edge of the thermal diffusion layer is provided with a notch; and a wire is connected between the substrate and the wafer through the notch. The chip package of claim 1, wherein the heat diffusion layer contains a heat conductive material. The chip package of claim 2, wherein the heat conductive material is flake graphene. The chip package of claim 1, wherein an adhesive is disposed on one side of the thermal diffusion layer and the wafer is attached. The chip package of claim 1, further comprising a package structure that encapsulates the wafer. The chip package of claim 5, wherein the thermal diffusion layer is thermally coupled to the package structure. The chip package of claim 1, further comprising a protective layer covering the thermal diffusion layer. The chip package of claim 7, wherein the notch extends from the thermal diffusion layer through the protective layer.