TW201742802A - Disk-like semiconductor package structure and combination thereof with tray - Google Patents
Disk-like semiconductor package structure and combination thereof with tray Download PDFInfo
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- TW201742802A TW201742802A TW105117420A TW105117420A TW201742802A TW 201742802 A TW201742802 A TW 201742802A TW 105117420 A TW105117420 A TW 105117420A TW 105117420 A TW105117420 A TW 105117420A TW 201742802 A TW201742802 A TW 201742802A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67766—Mechanical parts of transfer devices
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Abstract
Description
本發明是有關於一種半導體封裝結構及半導體封裝結構與載盤的組合，且特別是有關於一種圓餅狀的半導體封裝結構及圓餅狀的半導體封裝結構與載盤的組合。The present invention relates to a semiconductor package structure and a combination of a semiconductor package structure and a carrier, and more particularly to a combination of a wafer-shaped semiconductor package structure and a wafer-shaped semiconductor package structure and a carrier.
在半導體產業中，積體電路(IC)的生產主要可分為三個階段：積體電路的設計、積體電路的製作以及積體電路的封裝。在晶圓的積體電路製作完成之後，晶圓的主動面配置有多個接墊。接著，預定切割線切割晶圓以得到多個晶片。接著，這些晶片可透過接墊電性連接於承載器(carrier)。通常而言，承載器可為導線架(lead frame)或基板(substrate)，而這些晶片可透過打線接合(wire bonding)或覆晶接合(flip chip bonding)等方式電性連接於承載器。接著，進行封膠步驟，使封裝膠體形成於承載器上，並覆蓋這些晶片。之後，進行單體化製程，以得到多個晶片封裝體。In the semiconductor industry, the production of integrated circuits (ICs) can be divided into three stages: the design of integrated circuits, the fabrication of integrated circuits, and the packaging of integrated circuits. After the fabrication of the integrated circuit of the wafer is completed, the active surface of the wafer is provided with a plurality of pads. Next, the predetermined dicing line cuts the wafer to obtain a plurality of wafers. Then, the wafers are electrically connected to the carrier through the pads. Generally, the carrier may be a lead frame or a substrate, and the chips may be electrically connected to the carrier by wire bonding or flip chip bonding. Next, a sealing step is performed to form an encapsulant on the carrier and cover the wafers. Thereafter, a singulation process is performed to obtain a plurality of chip packages.
在供貨至客戶端或進行後續製程，例如：測試或SMT上板時，這些晶片封裝體會分別置放到載盤上，以避免於運送過程中造成晶片封裝體的損傷。因此，如何使設置於載盤上的這些晶片封裝體不會任意地相對於載盤移動或轉動，進而避免晶片封裝體之方位無法辨識而影響後續製程的效率的情況發生，便成為當前亟待解決的問題之一。When supplied to the client or for subsequent processes, such as testing or SMT board, these chip packages are placed on the carrier, respectively, to avoid damage to the chip package during shipping. Therefore, how to prevent the wafer package disposed on the carrier from being arbitrarily moved or rotated relative to the carrier, thereby preventing the orientation of the chip package from being recognized and affecting the efficiency of subsequent processes, has become an urgent problem to be solved. One of the problems.
本發明提供一種圓餅狀半導體封裝結構及圓餅狀半導體封裝結構與載盤的組合，有助於固定圓餅狀半導體封裝結構於載盤中的方位，以提高後續製程(例如：測試或SMT上板)的效率。The invention provides a combination of a wafer-shaped semiconductor package structure and a wafer-shaped semiconductor package structure and a carrier, which helps to fix the orientation of the wafer-shaped semiconductor package structure in the carrier to improve subsequent processes (for example, testing or SMT) The efficiency of the board).
本發明的一種圓餅狀半導體封裝結構，包括一圓餅狀線路基板、一晶片及一圓餅狀封裝膠體。圓餅狀線路基板包括相對的一第一表面及一第二表面、連接第一表面與第二表面的一側壁、多個外接點及一導磁部。這些外接點位於第二表面，導磁部設置於圓餅狀線路基板內且鄰近側壁，導磁部對應其中一個外接點。晶片設置於第一表面上且電性連接圓餅狀線路基板。圓餅狀封裝膠體設置於第一表面上且覆蓋晶片。A wafer-shaped semiconductor package structure of the present invention comprises a wafer-shaped circuit substrate, a wafer and a wafer-shaped encapsulant. The wafer-shaped circuit substrate includes a first surface and a second surface, a sidewall connecting the first surface and the second surface, a plurality of external contacts, and a magnetic conductive portion. The external contacts are located on the second surface, and the magnetic conductive portion is disposed in the wafer-shaped circuit substrate adjacent to the sidewall, and the magnetic conductive portion corresponds to one of the external contacts. The wafer is disposed on the first surface and electrically connected to the wafer-shaped circuit substrate. A wafer-shaped encapsulant is disposed on the first surface and covers the wafer.
在本發明的一實施例中，上述的導磁部外露於側壁。In an embodiment of the invention, the magnetic conductive portion is exposed to the side wall.
在本發明的一實施例中，上述的圓餅狀線路基板具有位於第一表面的一基板凹槽，導磁部位於基板凹槽內。In an embodiment of the invention, the wafer-shaped circuit substrate has a substrate recess on the first surface, and the magnetic conductive portion is located in the substrate recess.
在本發明的一實施例中，上述的導磁部外露於第一表面。In an embodiment of the invention, the magnetic conductive portion is exposed on the first surface.
在本發明的一實施例中，上述的圓餅狀線路基板更包括一保護層，保護層設置於基板凹槽內且覆蓋導磁部。In an embodiment of the invention, the wafer-shaped circuit substrate further includes a protective layer disposed in the substrate recess and covering the magnetic conductive portion.
在本發明的一實施例中，上述的導磁部包括磁性金屬鍍層。In an embodiment of the invention, the magnetic conductive portion includes a magnetic metal plating layer.
在本發明的一實施例中，上述的導磁部的厚度介於圓餅狀線路基板的厚度的1/3至2/3之間。In an embodiment of the invention, the thickness of the magnetic conductive portion is between 1/3 and 2/3 of the thickness of the wafer-shaped circuit substrate.
本發明的一種圓餅狀半導體封裝結構與載盤的組合包括一圓餅狀半導體封裝結構及一載盤。圓餅狀半導體封裝結構包括一圓餅狀線路基板、一晶片及一圓餅狀封裝膠體。圓餅狀線路基板包括相對的一第一表面及一第二表面、連接第一表面與第二表面的一側壁、多個外接點及一導磁部。這些外接點位於第二表面，導磁部設置於圓餅狀線路基板內且鄰近側壁，導磁部對應其中一個外接點。晶片設置於第一表面上且電性連接圓餅狀線路基板。圓餅狀封裝膠體設置於第一表面上且覆蓋晶片。載盤包括至少一載盤凹槽以及位於至少一載盤凹槽旁的至少一磁吸件。圓餅狀半導體封裝結構設置於載盤凹槽內，且載盤的磁吸件吸引圓餅狀線路基板的導磁部。The combination of a wafer-shaped semiconductor package structure and a carrier of the present invention comprises a wafer-shaped semiconductor package structure and a carrier. The wafer-shaped semiconductor package structure includes a wafer-shaped circuit substrate, a wafer, and a wafer-shaped encapsulant. The wafer-shaped circuit substrate includes a first surface and a second surface, a sidewall connecting the first surface and the second surface, a plurality of external contacts, and a magnetic conductive portion. The external contacts are located on the second surface, and the magnetic conductive portion is disposed in the wafer-shaped circuit substrate adjacent to the sidewall, and the magnetic conductive portion corresponds to one of the external contacts. The wafer is disposed on the first surface and electrically connected to the wafer-shaped circuit substrate. A wafer-shaped encapsulant is disposed on the first surface and covers the wafer. The carrier includes at least one carrier disk recess and at least one magnetic member located adjacent the at least one carrier disk recess. The wafer-shaped semiconductor package structure is disposed in the groove of the carrier, and the magnetic member of the carrier attracts the magnetic conductive portion of the wafer-shaped circuit substrate.
在本發明的一實施例中，上述的導磁部外露於側壁。In an embodiment of the invention, the magnetic conductive portion is exposed to the side wall.
在本發明的一實施例中，上述的圓餅狀線路基板具有位於第一表面的一基板凹槽，導磁部位於基板凹槽內。In an embodiment of the invention, the wafer-shaped circuit substrate has a substrate recess on the first surface, and the magnetic conductive portion is located in the substrate recess.
在本發明的一實施例中，上述的導磁部外露於第一表面。In an embodiment of the invention, the magnetic conductive portion is exposed on the first surface.
在本發明的一實施例中，上述的圓餅狀線路基板更包括一保護層，保護層設置於基板凹槽內且覆蓋導磁部。In an embodiment of the invention, the wafer-shaped circuit substrate further includes a protective layer disposed in the substrate recess and covering the magnetic conductive portion.
在本發明的一實施例中，上述的導磁部包括磁性金屬鍍層。In an embodiment of the invention, the magnetic conductive portion includes a magnetic metal plating layer.
在本發明的一實施例中，上述的導磁部的厚度介於圓餅狀線路基板的厚度的1/3至2/3之間。In an embodiment of the invention, the thickness of the magnetic conductive portion is between 1/3 and 2/3 of the thickness of the wafer-shaped circuit substrate.
基於上述，本發明的圓餅狀半導體封裝結構與載盤的組合透過於圓餅狀半導體封裝結構的圓餅狀線路基板內鄰近其側壁處且對應其中一個外接點的位置設置導磁部，以及於載盤的載盤凹槽旁配置磁吸件，當圓餅狀半導體封裝結構設置於載盤凹槽內時，載盤的磁吸件吸引圓餅狀線路基板的導磁部，使得圓餅狀半導體封裝結構不會在載盤的載盤凹槽內任意地移動或轉動，避免圓餅狀半導體封裝結構與載盤碰撞而產生損傷。此外，由於本發明的圓餅狀半導體封裝結構的導磁部可對應特定外接點，因此設置於載盤中的圓餅狀半導體封裝結構的方位為固定的。如此一來，相關的技術人員或機台在後續製程中可快速地判斷圓餅狀半導體封裝結構中的電性接點的位置，有助於提高後續製程(例如：測試或SMT上板)的效率。Based on the above, the combination of the wafer-shaped semiconductor package structure and the carrier of the present invention is disposed through a magnetic conductive portion disposed at a position adjacent to a sidewall of the wafer-shaped circuit substrate of the wafer-shaped semiconductor package structure corresponding to one of the external contacts, and A magnetic member is disposed beside the groove of the carrier disk of the carrier. When the wafer-shaped semiconductor package structure is disposed in the groove of the carrier, the magnetic member of the carrier attracts the magnetic conductive portion of the wafer-shaped circuit substrate, so that the round cake The semiconductor package structure does not arbitrarily move or rotate within the carrier groove of the carrier, thereby preventing the wafer-shaped semiconductor package structure from colliding with the carrier and causing damage. In addition, since the magnetic conductive portion of the wafer-shaped semiconductor package structure of the present invention can correspond to a specific external contact, the orientation of the wafer-shaped semiconductor package structure disposed in the carrier is fixed. In this way, the relevant technician or machine can quickly determine the position of the electrical contacts in the wafer-shaped semiconductor package structure in subsequent processes, which helps to improve the subsequent processes (for example, testing or SMT upper board). effectiveness.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1是依照本發明的一實施例的一種圓餅狀半導體封裝結構的示意圖。圖2是圖1的圓餅狀半導體封裝結構的仰視示意圖。圖3是圖1的圓餅狀半導體封裝結構的圓餅狀線路基板的側視示意圖。請參閱圖1至圖3，本實施例的圓餅狀半導體封裝結構100包括一圓餅狀線路基板110、一晶片120及一圓餅狀封裝膠體130。1 is a schematic view of a wafer-shaped semiconductor package structure in accordance with an embodiment of the present invention. 2 is a bottom plan view of the wafer-shaped semiconductor package structure of FIG. 1. 3 is a side elevational view of a wafer-shaped circuit substrate of the wafer-shaped semiconductor package structure of FIG. 1. Referring to FIG. 1 to FIG. 3 , the wafer-shaped semiconductor package structure 100 of the present embodiment includes a wafer-shaped circuit substrate 110 , a wafer 120 , and a wafer-shaped encapsulant 130 .
圓餅狀線路基板110可以是由硬式基材或可撓性基材所構成。圓餅狀線路基板110包括相對的一第一表面112及一第二表面114、連接第一表面112與第二表面114的一側壁116、多個外接點118及一導磁部119。The wafer-shaped circuit substrate 110 may be composed of a hard substrate or a flexible substrate. The wafer-shaped circuit substrate 110 includes a first surface 112 and a second surface 114 , a sidewall 116 connecting the first surface 112 and the second surface 114 , a plurality of external contacts 118 , and a magnetic conductive portion 119 .
導磁部119設置於圓餅狀線路基板110內且鄰近側壁116，在本實施例中，導磁部119外露於側壁116，當然，在其他實施例中，導磁部119也可以是接近但不外露於側壁116。導磁部119包括磁性金屬鍍層，例如是鐵或是鎳等金屬鍍層，但導磁部119的種類並不以上述為限制。導磁部119可以是在製作圓餅狀線路基板110的線路(未繪示)的時候一起被製作、在線路(未繪示)已被形成於圓餅狀線路基板110之後另外以類似製程(例如：電鍍)形成於圓餅狀線路基板110內，或者導磁部119也可以是額外被製作後放入圓餅狀線路基板110內。此外，導磁部119的厚度介於圓餅狀線路基板110的厚度的1/3至2/3之間，以具有足夠的導磁能力。如圖2所示，圓餅狀線路基板110的這些外接點118位於第二表面114，且導磁部119在第二表面114的投影位置對應其中一個外接點118的位置。The magnetic conductive portion 119 is disposed in the wafer-shaped circuit substrate 110 and adjacent to the sidewall 116. In this embodiment, the magnetic conductive portion 119 is exposed to the sidewall 116. Of course, in other embodiments, the magnetic conductive portion 119 may be close to Not exposed to the sidewall 116. The magnetic conductive portion 119 includes a magnetic metal plating layer, for example, a metal plating layer such as iron or nickel, but the type of the magnetic conductive portion 119 is not limited to the above. The magnetic conductive portion 119 may be fabricated together at the time of making a circuit (not shown) of the wafer-shaped circuit substrate 110, and after a circuit (not shown) has been formed on the wafer-shaped circuit substrate 110, a similar process is additionally performed ( For example, electroplating may be formed in the wafer-shaped circuit substrate 110, or the magnetic conductive portion 119 may be additionally formed and placed in the wafer-shaped circuit substrate 110. Further, the thickness of the magnetic conductive portion 119 is between 1/3 and 2/3 of the thickness of the wafer-shaped wiring substrate 110 to have sufficient magnetic permeability. As shown in FIG. 2, the external contacts 118 of the wafer-shaped circuit substrate 110 are located on the second surface 114, and the projected position of the magnetic conductive portion 119 at the second surface 114 corresponds to the position of one of the external contacts 118.
晶片120設置於第一表面112上且電性連接圓餅狀線路基板110。詳細而言，晶片120可透過打線方式或覆晶接合方式以銲線或凸塊電性連接位於圓餅狀線路基板110的第一表面112上的接墊(未繪示)。圓餅狀封裝膠體130設置於第一表面112上且覆蓋晶片120。圓餅狀封裝膠體130可為環氧樹脂，用以避免晶片120與電性接點受到外界水氣或異物的影響。The wafer 120 is disposed on the first surface 112 and electrically connected to the wafer-shaped circuit substrate 110. In detail, the wafer 120 can be electrically connected to the pads (not shown) on the first surface 112 of the wafer-shaped circuit substrate 110 by wire bonding or bumping through wire bonding or flip chip bonding. The wafer-shaped encapsulant 130 is disposed on the first surface 112 and covers the wafer 120. The wafer-shaped encapsulant 130 may be an epoxy resin to prevent the wafer 120 and the electrical contacts from being affected by external moisture or foreign matter.
圖4是圖1的圓餅狀半導體封裝結構與其中一種載盤的組合示意圖。請參閱圖4，圖1的圓餅狀半導體封裝結構100被放置入一載盤10中。載盤10包括至少一載盤凹槽12以及位於至少一載盤凹槽12旁的至少一磁吸件14。磁吸件14例如是永久磁鐵。當圓餅狀半導體封裝結構100設置於載盤凹槽12內時，載盤10的磁吸件14會吸引圓餅狀線路基板110的導磁部119，而使得圓餅狀半導體封裝結構100在載盤凹槽12內的位置固定，不會在載盤10的載盤凹槽12內任意地移動或轉動，避免圓餅狀半導體封裝結構100與載盤10碰撞而產生損傷。值得一提的是，載盤凹槽12的形狀不限制是方形，在其他實施例中，載盤凹槽12也可為圓型或其他適合的形狀，磁吸件14也可以是電磁鐵等其他種磁鐵。4 is a schematic view showing the combination of the wafer-shaped semiconductor package structure of FIG. 1 and one of the carriers. Referring to FIG. 4, the wafer-shaped semiconductor package structure 100 of FIG. 1 is placed in a carrier 10. The carrier 10 includes at least one carrier groove 12 and at least one magnetic member 14 positioned adjacent to at least one of the carrier grooves 12. The magnetic member 14 is, for example, a permanent magnet. When the wafer-shaped semiconductor package structure 100 is disposed in the carrier groove 12, the magnetic member 14 of the carrier 10 attracts the magnetic conductive portion 119 of the wafer-shaped circuit substrate 110, so that the wafer-shaped semiconductor package structure 100 is The position in the carrier groove 12 is fixed and does not arbitrarily move or rotate within the carrier groove 12 of the carrier 10, thereby preventing damage of the wafer-shaped semiconductor package structure 100 from colliding with the carrier 10. It should be noted that the shape of the carrier groove 12 is not limited to a square shape. In other embodiments, the carrier groove 12 may also be a circular shape or other suitable shape, and the magnetic member 14 may also be an electromagnet or the like. Other kinds of magnets.
並且，由於圓餅狀半導體封裝結構100的圓餅狀線路基板110的導磁部119對應到特定的外接點118(例如是pin 1)，而使得圓餅狀半導體封裝結構100的外接點118在載盤凹槽12內的位置固定，相關的技術人員或機台在後續製程中可快速地判斷圓餅狀半導體封裝結構100中的電性接點的方向及位置，有助於提高後續製程(例如：測試或SMT上板)的效率。Moreover, since the magnetic conductive portion 119 of the wafer-shaped circuit substrate 110 of the wafer-shaped semiconductor package structure 100 corresponds to a specific external contact 118 (for example, pin 1), the external contact 118 of the wafer-shaped semiconductor package structure 100 is The position in the carrier groove 12 is fixed, and the relevant technician or machine can quickly determine the direction and position of the electrical contacts in the wafer-shaped semiconductor package structure 100 in subsequent processes, which helps to improve the subsequent process ( For example: the efficiency of the test or SMT board).
需說明的是，在圖4中僅是示意性地繪示出具有一個載盤凹槽12的載盤10，在一未繪示的實施例中，載盤10可能會有多個陣列排列的載盤凹槽12，這些磁吸件14也以陣列的形式排列在這些載盤凹槽12旁，也就是說，各載盤凹槽12與其對應的磁吸件14之間的相對位置固定。當放入載盤10中的這些圓餅狀半導體封裝結構100的導磁部119皆是位在對應於相同編號的外接點118(例如是pin 1)的位置，則這些圓餅狀半導體封裝結構100在放入載盤10中的這些載盤凹槽12時，這些導磁部119便會被載盤10中的這些磁吸件14吸引，而使這些圓餅狀半導體封裝結構100中的這些外接點118相對於載盤凹槽12的位置一致，以方便相關的技術人員或機台在後續製程中可快速地判斷圓餅狀半導體封裝結構100中的電性接點的位置。It should be noted that, in FIG. 4, only the carrier 10 having one carrier groove 12 is schematically illustrated. In an unillustrated embodiment, the carrier 10 may have multiple arrays arranged. The carrier recesses 12, which are also arranged in the form of an array, are positioned adjacent to the carrier recesses 12, that is, the relative positions between the respective carrier recesses 12 and their corresponding magnetic members 14 are fixed. When the magnetic conductive portions 119 of the wafer-shaped semiconductor package structures 100 placed in the carrier 10 are located at positions corresponding to the same number of external contacts 118 (for example, pins 1), the wafer-shaped semiconductor package structures When the carrier grooves 12 are placed in the carrier 10, the magnetically permeable portions 119 are attracted by the magnetic members 14 in the carrier 10, and these are in the wafer-shaped semiconductor package structure 100. The position of the external contact 118 relative to the carrier groove 12 is uniform to facilitate the relevant technician or machine to quickly determine the position of the electrical contacts in the wafer-shaped semiconductor package structure 100 in subsequent processes.
此外，雖然在圖4中磁吸件14是位在載盤凹槽12的其中一個邊旁的位置，但磁吸件14在載盤凹槽12旁的相對位置並不以圖4為限制。圖5是圖1的圓餅狀半導體封裝結構與另一種載盤的組合示意圖。在圖5的實施例中與圖4的實施例相同或相似的元件以相同或相似的編號表示，不再多加贅述。請參閱圖5，載盤10a的磁吸件14也可以位在載盤凹槽12的角落，磁吸件14在載盤凹槽12旁的相對位置並不以上述為限制。Further, although the magnetic member 14 is positioned at one side of the carrier groove 12 in FIG. 4, the relative position of the magnetic member 14 beside the carrier groove 12 is not limited to FIG. FIG. 5 is a schematic view showing the combination of the wafer-shaped semiconductor package structure of FIG. 1 and another carrier. The same or similar elements in the embodiment of FIG. 5 as those of the embodiment of FIG. 4 are denoted by the same or similar reference numerals and will not be described again. Referring to FIG. 5, the magnetic member 14 of the carrier 10a may also be located at a corner of the carrier groove 12. The relative position of the magnetic member 14 beside the carrier groove 12 is not limited to the above.
此外，導磁部119相對於圓餅狀線路基板110的位置並不以圖1的實施例為限制。圖6與圖7分別是依照本發明的其他實施例的一種圓餅狀半導體封裝結構的圓餅狀線路基板的示意圖。需說明的是，圖6與圖7的實施例中，與圖3中相同或相似的元件以相同或相似的編號表示，不再多加贅述。Further, the position of the magnetic conductive portion 119 with respect to the wafer-shaped circuit substrate 110 is not limited to the embodiment of FIG. 6 and 7 are schematic views respectively showing a wafer-shaped circuit substrate of a wafer-shaped semiconductor package structure according to other embodiments of the present invention. It should be noted that in the embodiment of FIG. 6 and FIG. 7, the same or similar elements as those in FIG. 3 are denoted by the same or similar reference numerals and will not be described again.
請先參閱圖6，圖6的圓餅狀線路基板110a與圖3的圓餅狀線路基板110的主要差異在於，在圖3中，導磁部119並未外露於圓餅狀線路基板110的第一表面112。在本實施例中，圓餅狀線路基板110a具有位於第一表面112的一基板凹槽113a，導磁部119a位於基板凹槽113a內且外露於第一表面112。在本實施例中，導磁部119a的製作可以不與圓餅狀線路基板110a的線路(未繪示)同時進行，而是在線路(未繪示)已被形成於圓餅狀線路基板110a之後另外以類似製程形成於基板凹槽113a內。Referring to FIG. 6, the main difference between the wafer-shaped circuit substrate 110a of FIG. 6 and the wafer-shaped circuit substrate 110 of FIG. 3 is that, in FIG. 3, the magnetic conductive portion 119 is not exposed to the wafer-shaped circuit substrate 110. First surface 112. In the present embodiment, the wafer-shaped circuit substrate 110a has a substrate recess 113a on the first surface 112, and the magnetic conductive portion 119a is located in the substrate recess 113a and exposed on the first surface 112. In this embodiment, the magnetic conductive portion 119a may be formed not simultaneously with the wiring (not shown) of the wafer-shaped circuit substrate 110a, but may be formed on the wafer-shaped circuit substrate 110a in a line (not shown). Thereafter, it is additionally formed in the substrate recess 113a in a similar process.
當然，導磁部119a在圓餅狀線路基板110a的相對位置並不限制，只要導磁部119a的位置對應於其中一個外接點118即可。此外，在本實施例中，基板凹槽113a也被側壁116所暴露出，使得導磁部119a外露於側壁116，然而，在其他實施例中，基板凹槽113a也可不被側壁116暴露出，使得導磁部119a接近但不外露於側壁116。Of course, the relative position of the magnetic conductive portion 119a on the wafer-shaped circuit substrate 110a is not limited as long as the position of the magnetic conductive portion 119a corresponds to one of the external contacts 118. In addition, in the present embodiment, the substrate recess 113a is also exposed by the sidewall 116 such that the magnetic conductive portion 119a is exposed to the sidewall 116. However, in other embodiments, the substrate recess 113a may not be exposed by the sidewall 116. The magnetic conductive portion 119a is brought close to but not exposed to the side wall 116.
請參閱圖7，圖7的圓餅狀線路基板110b與圖6的圓餅狀線路基板110a的主要差異在於，在本實施例中，圓餅狀線路基板110b更包括一保護層115b，保護層115b設置於基板凹槽113b內且覆蓋導磁部119b，而使導磁部119b不外露於第一表面112。製作上，可以是在圓餅狀線路基板110b上先製作出基板凹槽113b，再形成導磁部119b於基板凹槽113b，接著再形成保護層115b在導磁部119b上。導磁部119b上的保護層115b與圓餅狀線路基板110b上的介電層可以是一起製作或是分開製作，且導磁部119b上的保護層115b可與第一表面112齊平。當然，在其他實施例中，導磁部119b上的保護層115b也可略高或略低於第一表面112。Referring to FIG. 7, the main difference between the wafer-shaped circuit substrate 110b of FIG. 7 and the wafer-shaped circuit substrate 110a of FIG. 6 is that, in the embodiment, the wafer-shaped circuit substrate 110b further includes a protective layer 115b, and a protective layer. 115b is disposed in the substrate recess 113b and covers the magnetic conductive portion 119b such that the magnetic conductive portion 119b is not exposed on the first surface 112. In the fabrication, the substrate recess 113b may be formed on the wafer-shaped circuit substrate 110b, and the magnetic conductive portion 119b may be formed on the substrate recess 113b, and then the protective layer 115b may be formed on the magnetic conductive portion 119b. The protective layer 115b on the magnetic conductive portion 119b and the dielectric layer on the wafer-shaped circuit substrate 110b may be fabricated together or separately, and the protective layer 115b on the magnetic conductive portion 119b may be flush with the first surface 112. Of course, in other embodiments, the protective layer 115b on the magnetic conductive portion 119b may also be slightly higher or slightly lower than the first surface 112.
綜上所述，本發明的圓餅狀半導體封裝結構與載盤的組合透過於圓餅狀半導體封裝結構的圓餅狀線路基板內鄰近其側壁處且對應其中一個外接點的位置設置導磁部，以及於載盤的載盤凹槽旁配置磁吸件，當圓餅狀半導體封裝結構設置於載盤凹槽內時，載盤的磁吸件吸引圓餅狀線路基板的導磁部，使得圓餅狀半導體封裝結構不會在載盤的載盤凹槽內任意地移動或轉動，避免圓餅狀半導體封裝結構與載盤碰撞而產生損傷。此外，由於本發明的圓餅狀半導體封裝結構的導磁部可對應特定外接點，因此設置於載盤中的圓餅狀半導體封裝結構的方位為固定的。如此一來，相關的技術人員或機台在後續製程中可快速地判斷圓餅狀半導體封裝結構中的電性接點的位置，有助於提高後續製程(例如：測試或SMT上板)的效率。In summary, the combination of the wafer-shaped semiconductor package structure and the carrier of the present invention is disposed through the position of the conductive portion of the wafer-shaped circuit substrate of the wafer-shaped semiconductor package adjacent to the sidewall thereof and corresponding to one of the external contacts. And arranging a magnetic member beside the carrier groove of the carrier, when the wafer-shaped semiconductor package structure is disposed in the groove of the carrier, the magnetic member of the carrier attracts the magnetic conductive portion of the wafer-shaped circuit substrate, so that The wafer-shaped semiconductor package structure does not arbitrarily move or rotate within the carrier groove of the carrier, thereby preventing damage of the wafer-shaped semiconductor package structure from collision with the carrier. In addition, since the magnetic conductive portion of the wafer-shaped semiconductor package structure of the present invention can correspond to a specific external contact, the orientation of the wafer-shaped semiconductor package structure disposed in the carrier is fixed. In this way, the relevant technician or machine can quickly determine the position of the electrical contacts in the wafer-shaped semiconductor package structure in subsequent processes, which helps to improve the subsequent processes (for example, testing or SMT upper board). effectiveness.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10、10a‧‧‧載盤
12‧‧‧載盤凹槽
14‧‧‧磁吸件
100‧‧‧圓餅狀半導體封裝結構
110、110a、110b‧‧‧圓餅狀線路基板
112‧‧‧第一表面
113a、113b‧‧‧基板凹槽
114‧‧‧第二表面
115b‧‧‧保護層
116‧‧‧側壁
118‧‧‧外接點
119、119a、119b‧‧‧導磁部
120‧‧‧晶片
130‧‧‧圓餅狀封裝膠體10, 10a‧‧‧ Carrier
12‧‧‧Loader groove
14‧‧‧Magnetic parts
100‧‧‧Row-shaped semiconductor package structure
110, 110a, 110b‧‧‧ round cake circuit board
112‧‧‧ first surface
113a, 113b‧‧‧ substrate recess
114‧‧‧ second surface
115b‧‧‧Protective layer
116‧‧‧ side wall
118‧‧‧External points
119, 119a, 119b‧‧‧ magnetic guide
120‧‧‧ wafer
130‧‧‧ Round cake encapsulant
圖1是依照本發明的一實施例的一種圓餅狀半導體封裝結構的示意圖。 圖2是圖1的圓餅狀半導體封裝結構的仰視示意圖。 圖3是圖1的圓餅狀半導體封裝結構的圓餅狀線路基板的側視示意圖。 圖4是圖1的圓餅狀半導體封裝結構與其中一種載盤的組合的示意圖。 圖5是圖1的圓餅狀半導體封裝結構與其中一種載盤的組合的示意圖。 圖6與圖7分別是依照本發明的其他實施例的多種圓餅狀半導體封裝結構的圓餅狀線路基板的示意圖。1 is a schematic view of a wafer-shaped semiconductor package structure in accordance with an embodiment of the present invention. 2 is a bottom plan view of the wafer-shaped semiconductor package structure of FIG. 1. 3 is a side elevational view of a wafer-shaped circuit substrate of the wafer-shaped semiconductor package structure of FIG. 1. 4 is a schematic view of the combination of the wafer-shaped semiconductor package structure of FIG. 1 and one of the carriers. Figure 5 is a schematic illustration of the combination of the wafer-shaped semiconductor package structure of Figure 1 and one of the carriers. 6 and 7 are schematic views respectively showing a wafer-shaped circuit substrate of a plurality of wafer-shaped semiconductor package structures according to other embodiments of the present invention.
100‧‧‧圓餅狀半導體封裝結構 100‧‧‧Row-shaped semiconductor package structure
110‧‧‧圓餅狀線路基板 110‧‧‧ Round cake circuit board
112‧‧‧第一表面 112‧‧‧ first surface
114‧‧‧第二表面 114‧‧‧ second surface
116‧‧‧側壁 116‧‧‧ side wall
119‧‧‧導磁部 119‧‧‧Magnetic Department
120‧‧‧晶片 120‧‧‧ wafer
130‧‧‧圓餅狀封裝膠體 130‧‧‧ Round cake encapsulant
Claims (14)
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| TW105117420A TWI560123B (en) | 2016-06-02 | 2016-06-02 | Disk-like semiconductor package structure and combination thereof with tray |
| CN201610585978.8A CN107464787B (en) | 2016-06-02 | 2016-07-25 | Cake-shaped semiconductor packaging structure and combination of wafer-shaped semiconductor packaging structure and carrying disc |
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| TW105117420A TWI560123B (en) | 2016-06-02 | 2016-06-02 | Disk-like semiconductor package structure and combination thereof with tray |
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| US7615836B2 (en) * | 2005-03-07 | 2009-11-10 | Sensormatic Electronics Corporation | Magnetic self-assembly for integrated circuit packages |
| JP5606021B2 (en) * | 2009-07-31 | 2014-10-15 | 日置電機株式会社 | Manufacturing method of current sensor |
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