CN107464787B - Cake-shaped semiconductor packaging structure and combination of wafer-shaped semiconductor packaging structure and carrying disc - Google Patents
Cake-shaped semiconductor packaging structure and combination of wafer-shaped semiconductor packaging structure and carrying disc Download PDFInfo
- Publication number
- CN107464787B CN107464787B CN201610585978.8A CN201610585978A CN107464787B CN 107464787 B CN107464787 B CN 107464787B CN 201610585978 A CN201610585978 A CN 201610585978A CN 107464787 B CN107464787 B CN 107464787B
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- round pie
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- semiconductor package
- base plate
- conductance portion
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000004806 packaging method and process Methods 0.000 title abstract 7
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000000084 colloidal system Substances 0.000 claims abstract description 12
- 238000010521 absorption reaction Methods 0.000 claims description 20
- 239000011241 protective layer Substances 0.000 claims description 15
- 238000012856 packing Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 8
- 238000012360 testing method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
- H01L21/67766—Mechanical parts of transfer devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Robotics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention provides a cake-shaped semiconductor packaging structure and a combination of the cake-shaped semiconductor packaging structure and a carrying disc. The pie-shaped circuit substrate comprises a first surface, a second surface, a side wall, a plurality of external contacts and a magnetic conduction part, wherein the first surface and the second surface are opposite to each other, the side wall is used for connecting the first surface with the second surface, and the magnetic conduction part is arranged on the side wall. The outer contacts are located on the second surface, the magnetic conduction part is arranged in the round cake-shaped circuit substrate and is adjacent to the side wall, and the magnetic conduction part corresponds to one of the outer contacts. The chip is arranged on the first surface and electrically connected with the cake-shaped circuit substrate. The cake-shaped packaging colloid is arranged on the first surface and covers the chip. The magnetic conduction part of the cake-shaped semiconductor packaging structure can correspond to a specific external contact, and cannot move or rotate freely in the groove of the carrying disc, so that the cake-shaped semiconductor packaging structure is prevented from being damaged due to collision with the carrying disc.
Description
Technical field
The invention relates to the combinations of a kind of semiconductor package and semiconductor package and load plate, and especially
About the combination of a kind of semiconductor package of round pie and the semiconductor package of round pie and load plate.
Background technique
In semiconductor industry, the production of integrated circuit (IC) can be divided mainly into three phases: design, the product of integrated circuit
The production of body circuit and the encapsulation of integrated circuit.After the integrated circuit of wafer completes, the active surface of wafer is configured
There are multiple connection pads.Then, predetermined cuts wire cutting wafer is to obtain multiple chips.Then, these chips can pass through connection pad electrical property
It is connected to carrier (carrier).Typically, carrier can be lead frame (lead frame) or substrate (substrate),
And these chips can engage the modes electrical property such as (wire bonding) or chip bonding (flip chip bonding) by routing
It is connected to carrier.Then, sealing step is carried out, is formed in packing colloid on carrier, and cover these chips.Later,
Singulation processing procedure is carried out, to obtain multiple chip packing-bodies.
In the supply of material to client or follow-up process is carried out, such as: when test or SMT upper plate, these chip packages, which are known from experience, to be divided
It is not placed on load plate, to avoid the damage for causing chip packing-body during transporting.Therefore, how to make to be set on load plate
These chip packing-bodies will not arbitrarily mobile relative to load plate or rotation, and then avoid the orientation of chip packing-body that from can not distinguishing
The case where knowing and influencing the efficiency of follow-up process generation becomes as one of current urgent problem to be solved.
Summary of the invention
The present invention provides the combination of a kind of round pie semiconductor package and round pie semiconductor package and load plate,
Facilitate fixed orientation of the round pie semiconductor package in load plate, with improve follow-up process (such as: on test or SMT
Plate) efficiency.
A kind of round pie semiconductor package of the invention, including round pie circuit base plate, chip and round pie encapsulation
Colloid.Round pie circuit base plate include opposite first surface and second surface, connection first surface and second surface side wall,
Multiple outer contacts and magnetic-conductance portion.These external points are located at second surface, and magnetic-conductance portion is set in round pie circuit base plate and neighbouring
Side wall, magnetic-conductance portion correspond to one of them outer contact.Chip is set on first surface and is electrically connected round pie circuit base plate.Circle
Pie packing colloid is set on first surface and covers chip.
In one embodiment of this invention, above-mentioned magnetic-conductance portion exposes to side wall.
In one embodiment of this invention, above-mentioned round pie circuit base plate has the substrate recess positioned at first surface,
Magnetic-conductance portion is located in substrate recess.
In one embodiment of this invention, above-mentioned magnetic-conductance portion exposes to first surface.
In one embodiment of this invention, above-mentioned round pie circuit base plate further includes protective layer, and protective layer is set to base
In plate groove and cover magnetic-conductance portion.
In one embodiment of this invention, above-mentioned magnetic-conductance portion includes magnetic metal coating.
In one embodiment of this invention, the thickness of above-mentioned magnetic-conductance portion between round pie circuit base plate thickness 1/3
To between 2/3.
The combination of of the invention a kind of round pie semiconductor package and load plate includes round pie semiconductor package
And load plate.Round pie semiconductor package includes round pie circuit base plate, chip and round pie packing colloid.Round pie route
Substrate includes opposite first surface and second surface, the side wall of connection first surface and second surface, multiple outer contacts and leads
Magnetic portion.These external points are located at second surface, and magnetic-conductance portion is set in round pie circuit base plate and adjacent sidewall, and magnetic-conductance portion is corresponding
One of them outer contact.Chip is set on first surface and is electrically connected round pie circuit base plate.Round pie packing colloid is set
It is placed on first surface and covers chip.Load plate include an at least load plate groove and by an at least load plate groove at least
One magnetic absorption member.Round pie semiconductor package is set in load plate groove, and the magnetic absorption member of load plate attracts round pie route base
The magnetic-conductance portion of plate.
In one embodiment of this invention, above-mentioned magnetic-conductance portion exposes to side wall.
In one embodiment of this invention, above-mentioned round pie circuit base plate has the substrate recess positioned at first surface,
Magnetic-conductance portion is located in substrate recess.
In one embodiment of this invention, above-mentioned magnetic-conductance portion exposes to first surface.
In one embodiment of this invention, above-mentioned round pie circuit base plate further includes a protective layer, and protective layer is set to
In substrate recess and cover magnetic-conductance portion.
In one embodiment of this invention, above-mentioned magnetic-conductance portion includes magnetic metal coating.
In one embodiment of this invention, the thickness of above-mentioned magnetic-conductance portion between round pie circuit base plate thickness 1/3
To between 2/3.
Combination based on above-mentioned, of the invention round pie semiconductor package and load plate passes through in round pie semiconductor package
Magnetic-conductance portion is arranged in the position of its neighbouring side-walls and one of them corresponding outer contact in the round pie circuit base plate of assembling structure, and
Magnetic absorption member, when round pie semiconductor package is set in load plate groove, load plate are configured by the load plate groove of load plate
Magnetic absorption member attracts the magnetic-conductance portion of round pie circuit base plate, so that round pie semiconductor package will not be in the load plate groove of load plate
It inside arbitrarily moves or rotates, round pie semiconductor package and load plate is avoided to collide and generate damage.Further, since this hair
The magnetic-conductance portion of bright round pie semiconductor package can correspond to specific outer contact, therefore be set to the round pie in load plate and partly lead
The orientation of body encapsulating structure is fixed.In this way, which relevant technical staff or board can rapidly be sentenced in follow-up process
The position of electrical contact in disconnected round pie semiconductor package, help to improve follow-up process (such as: on test or SMT
Plate) efficiency.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is the schematic diagram according to a kind of round pie semiconductor package of one embodiment of the invention；
Fig. 2 is the elevational schematic view of the round pie semiconductor package of Fig. 1；
Fig. 3 is the schematic side view of the round pie circuit base plate of the round pie semiconductor package of Fig. 1；
Fig. 4 is the round pie semiconductor package of Fig. 1 and the combined schematic diagram of one of load plate；
Fig. 5 is the round pie semiconductor package of Fig. 1 and the combined schematic diagram of one of load plate；
Fig. 6 and Fig. 7 is the cake according to a variety of round pie semiconductor packages of the other embodiment of the present invention respectively
The schematic diagram of shape circuit base plate.
Description of symbols:
10,10a: load plate；
12: load plate groove；
14: magnetic absorption member；
100: round pie semiconductor package；
110,110a, 110b: round pie circuit base plate；
112: first surface；
113a, 113b: substrate recess；
114: second surface；
115b: protective layer；
116: side wall；
118: outer contact；
119,119a, 119b: magnetic-conductance portion；
120: chip；
130: round pie packing colloid.
Specific embodiment
Fig. 1 is the schematic diagram according to a kind of round pie semiconductor package of one embodiment of the invention.Fig. 2 is Fig. 1
Round pie semiconductor package elevational schematic view.Fig. 3 is the round pie route of the round pie semiconductor package of Fig. 1
The schematic side view of substrate.It please refers to Fig.1 to Fig.3, the round pie semiconductor package 100 of the present embodiment includes round pie line
Base board 110, chip 120 and round pie packing colloid 130.
Round pie circuit base plate 110 can be to be made of rigid substrate or flexible substrate.Round pie circuit base plate 110
Side wall 116, multiple including opposite first surface 112 and second surface 114, connection first surface 112 and second surface 114
Outer contact 118 and magnetic-conductance portion 119.
Magnetic-conductance portion 119 is set in round pie circuit base plate 110 and adjacent sidewall 116, in the present embodiment, magnetic-conductance portion
119 expose to side wall 116, and certainly, in other embodiments, magnetic-conductance portion 119 is also possible to close but does not expose to side wall 116.
Magnetic-conductance portion 119 include magnetic metal coating, the e.g. coats of metal such as iron or nickel, but the type of magnetic-conductance portion 119 not more than
It states as limitation.Magnetic-conductance portion 119 can be to be made together when making the route (not shown) of round pie circuit base plate 110
Make, in addition formed after route (not shown) has been formed on round pie circuit base plate 110 with similar processing procedure (such as: plating)
In in round pie circuit base plate 110 or magnetic-conductance portion 119 be also possible to additionally be produced after be put into round pie circuit base plate 110
It is interior.In addition, the thickness of magnetic-conductance portion 119 is between the 1/3 to 2/3 of the thickness of round pie circuit base plate 110, with enough
Magnetic conduction ability.As shown in Fig. 2, these outer contacts 118 of round pie circuit base plate 110 are located at second surface 114, and magnetic-conductance portion
119 correspond to the position of one of them outer contact 118 in the projected position of second surface 114.
Chip 120 is set on first surface 112 and is electrically connected round pie circuit base plate 110.Specifically, chip
120 can be electrically connected with bonding wire or convex block by routing mode or chip bonding mode and be located at the of round pie circuit base plate 110
Connection pad (not shown) on one surface 112.Round pie packing colloid 130 is set on first surface 112 and covers chip 120.
Round pie packing colloid 130 can be epoxy resin, with to avoid chip 120 and electrical contact by extraneous aqueous vapor or the shadow of foreign matter
It rings.
Fig. 4 is the round pie semiconductor package of Fig. 1 and the combination diagram of one of load plate.Referring to Fig. 4, figure
1 round pie semiconductor package 100 is placed into load plate 10.Load plate 10 includes an at least load plate groove 12 and is located at
An at least magnetic absorption member 14 on 12 side of an at least load plate groove.Magnetic absorption member 14 is, for example, permanent magnet.When round pie semiconductor packages
When structure 100 is set in load plate groove 12, the magnetic absorption member 14 of load plate 10 can attract the magnetic-conductance portion of round pie circuit base plate 110
119, and position of the round pie semiconductor package 100 in load plate groove 12 is fixed, it will not be in the load plate of load plate 10
It arbitrarily moves or rotates in groove 12, round pie semiconductor package 100 and load plate 10 is avoided to collide and generate damage.Value
One be mentioned that, the shape of load plate groove 12 do not limit be it is rectangular, in other embodiments, load plate groove 12 can also to be round or
Other suitable shapes, magnetic absorption member 14 are also possible to other kind of magnet such as electromagnet.
Also, since the magnetic-conductance portion 119 of the round pie circuit base plate 110 of round pie semiconductor package 100 corresponds to
Specific outer contact 118 (e.g. pin 1), and make the outer contact 118 of round pie semiconductor package 100 recessed in load plate
Position in slot 12 is fixed, and relevant technical staff or board can rapidly judge round pie semiconductor packages in follow-up process
The direction and position of electrical contact in structure 100 help to improve the efficiency of follow-up process (such as: test or SMT upper plate).
It should be noted that being only to schematically show the load plate 10 with a load plate groove 12 in Fig. 4, do not show one
In embodiment out, load plate 10 might have the load plate groove 12 of multiple array arrangements, these magnetic absorption members 14 are also with the shape of array
Formula is arranged in by these load plate grooves 12, that is to say, that the opposite position between the corresponding magnetic absorption member 14 of each load plate groove 12
Set fixation.When the magnetic-conductance portion 119 for these round pie semiconductor packages 100 being put into load plate 10 is all that position is corresponding to phase
With the position of the outer contact 118 (e.g. pin 1) of number, then these round pie semiconductor packages 100 are being put into load plate
When these load plate grooves 12 in 10, these magnetic-conductance portions 119 will be attracted by these magnetic absorption members 14 in load plate 10, and make these
These position consistencies of outer contact 118 relative to load plate groove 12 in round pie semiconductor package 100, to facilitate correlation
Technical staff or board the electrical contact in round pie semiconductor package 100 can be rapidly judged in follow-up process
Position.
Although in addition, magnetic absorption member 14 is position of the position by one of side of load plate groove 12, magnetic absorption member in Fig. 4
14 relative position by load plate groove 12 is not limitation with Fig. 4.Fig. 5 is the round pie semiconductor package of Fig. 1 and another
A kind of combination diagram of load plate.In the 5 embodiment of figure 5 with the same or similar element of the embodiment of Fig. 4 with same or similar
Number indicate, no longer add to repeat.Referring to Fig. 5, the magnetic absorption member 14 of load plate 10a also can be situated in the angle of load plate groove 12
It falls, relative position of the magnetic absorption member 14 by load plate groove 12 be not with the above-mentioned system that is limited.
In addition, magnetic-conductance portion 119 is not limitation with the embodiment of Fig. 1 relative to the position of round pie circuit base plate 110.Figure
6 and Fig. 7 is the round pie circuit base plate according to a kind of round pie semiconductor package of the other embodiment of the present invention respectively
Schematic diagram.It should be noted that in the embodiment of Fig. 6 and Fig. 7, with element the same or similar in Fig. 3 with the same or similar
Number indicates, no longer adds to repeat.
Please referring initially to Fig. 6, the main difference of the round pie circuit base plate 110 of round pie the circuit base plate 110a and Fig. 3 of Fig. 6
It is, in Fig. 3, magnetic-conductance portion 119 does not expose to the first surface 112 of round pie circuit base plate 110.In the present embodiment,
There is round pie circuit base plate 110a the substrate recess 113a positioned at first surface 112, magnetic-conductance portion 119a to be located at substrate recess
In 113a and expose to first surface 112.In the present embodiment, the production of magnetic-conductance portion 119a can not be with round pie circuit base plate
The route (not shown) of 110a carries out simultaneously, but after route (not shown) has been formed on round pie circuit base plate 110a
In addition it is formed in substrate recess 113a with similar processing procedure.
Certainly, magnetic-conductance portion 119a is not intended to limit in the relative position of round pie circuit base plate 110a, as long as magnetic-conductance portion 119a
Position correspond to one of them outer contact 118.In addition, in the present embodiment, substrate recess 113a is also by 116 institute of side wall
It exposes, so that magnetic-conductance portion 119a exposes to side wall 116, however, in other embodiments, substrate recess 113a can not also be by side
Wall 116 exposes, so that magnetic-conductance portion 119a is close but does not expose to side wall 116.
Referring to Fig. 7, the main difference of the round pie circuit base plate 110a of round pie the circuit base plate 110b and Fig. 6 of Fig. 7
It is, in the present embodiment, round pie circuit base plate 110b further includes protective layer 115b, and protective layer 115b is set to substrate recess
In 113b and magnetic-conductance portion 119b is covered, and magnetic-conductance portion 119b is made not expose to first surface 112.In production, it can be in cake
Substrate recess 113b is first produced on shape circuit base plate 110b, re-forms magnetic-conductance portion 119b in substrate recess 113b, then shape again
At protective layer 115b on magnetic-conductance portion 119b.Jie on protective layer 115b and round pie circuit base plate 110b on magnetic-conductance portion 119b
Electric layer, which can be, to be made together or is fabricated separately, and the protective layer 115b on magnetic-conductance portion 119b can be flushed with first surface 112.
Certainly, in other embodiments, the protective layer 115b on magnetic-conductance portion 119b can also slightly higher or slightly below first surface 112.
In conclusion the combination of round pie semiconductor package and load plate of the invention passes through in round pie semiconductor package
Magnetic-conductance portion is arranged in the position of its neighbouring side-walls and one of them corresponding outer contact in the round pie circuit base plate of assembling structure, and
Magnetic absorption member, when round pie semiconductor package is set in load plate groove, load plate are configured by the load plate groove of load plate
Magnetic absorption member attracts the magnetic-conductance portion of round pie circuit base plate, so that round pie semiconductor package will not be in the load plate groove of load plate
It inside arbitrarily moves or rotates, round pie semiconductor package and load plate is avoided to collide and generate damage.Further, since this hair
The magnetic-conductance portion of bright round pie semiconductor package can correspond to specific outer contact, therefore be set to the round pie in load plate and partly lead
The orientation of body encapsulating structure is fixed.In this way, which relevant technical staff or board can rapidly be sentenced in follow-up process
The position of electrical contact in disconnected round pie semiconductor package, help to improve follow-up process (such as: on test or SMT
Plate) efficiency.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (14)
1. a kind of round pie semiconductor package characterized by comprising
Round pie circuit base plate, including opposite first surface and second surface, the connection first surface and second table
The side wall in face, multiple outer contacts and magnetic-conductance portion, wherein the multiple external point is located at the second surface, the magnetic-conductance portion setting
In in the round pie circuit base plate and adjacent to the side wall, the magnetic-conductance portion corresponds to it in the projected position of the second surface
In an outer contact position；
Chip is set on the first surface, and is electrically connected the round pie circuit base plate；And
Round pie packing colloid is set on the first surface, and covers the chip.
2. round pie semiconductor package according to claim 1, which is characterized in that the magnetic-conductance portion exposes to described
Side wall.
3. round pie semiconductor package according to claim 1, which is characterized in that the round pie circuit base plate tool
There is the substrate recess positioned at the first surface, the magnetic-conductance portion is located in the substrate recess.
4. round pie semiconductor package according to claim 3, which is characterized in that the magnetic-conductance portion exposes to described
First surface.
5. round pie semiconductor package according to claim 3, which is characterized in that the round pie circuit base plate is also
Including protective layer, the protective layer is set in the substrate recess and the covering magnetic-conductance portion.
6. round pie semiconductor package according to claim 1, which is characterized in that the magnetic-conductance portion includes magnetic gold
Belong to coating.
7. round pie semiconductor package according to claim 1, which is characterized in that the thickness of the magnetic-conductance portion between
Between the 1/3 to 2/3 of the thickness of the round pie circuit base plate.
8. a kind of combination of round pie semiconductor package and load plate characterized by comprising
Round pie semiconductor package, comprising:
Round pie circuit base plate, including opposite first surface and second surface, the connection first surface and second table
The side wall in face, multiple outer contacts and magnetic-conductance portion, wherein the multiple external point is located at the second surface, the magnetic-conductance portion setting
In in the round pie circuit base plate and adjacent to the side wall, the magnetic-conductance portion corresponds to it in the projected position of the second surface
In an outer contact position；
Chip is set on the first surface, and is electrically connected the round pie circuit base plate；And
Round pie packing colloid is set on the first surface, and covers the chip；And
Load plate, at least magnetic absorption member including an at least load plate groove and by an at least load plate groove, the circle
Pie semiconductor package is set in the load plate groove, and the magnetic absorption member of the load plate attracts the round pie line
The magnetic-conductance portion of base board.
9. the combination of round pie semiconductor package and load plate according to claim 8, which is characterized in that the magnetic conduction
Portion exposes to the side wall.
10. the combination of round pie semiconductor package and load plate according to claim 8, which is characterized in that the circle
Pie circuit base plate has the substrate recess positioned at the first surface, and the magnetic-conductance portion is located in the substrate recess.
11. the combination of round pie semiconductor package and load plate according to claim 10, which is characterized in that described to lead
Magnetic portion exposes to the first surface.
12. the combination of round pie semiconductor package and load plate according to claim 10, which is characterized in that the circle
Pie circuit base plate further includes protective layer, and the protective layer is set in the substrate recess and the covering magnetic-conductance portion.
13. the combination of round pie semiconductor package and load plate according to claim 8, which is characterized in that described to lead
Magnetic portion includes magnetic metal coating.
14. the combination of round pie semiconductor package and load plate according to claim 8, which is characterized in that described to lead
The thickness in magnetic portion is between the 1/3 to 2/3 of the thickness of the round pie circuit base plate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105117420 | 2016-06-02 | ||
| TW105117420A TWI560123B (en) | 2016-06-02 | 2016-06-02 | Disk-like semiconductor package structure and combination thereof with tray |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107464787A CN107464787A (en) | 2017-12-12 |
| CN107464787B true CN107464787B (en) | 2019-10-11 |
Family
ID=58227129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610585978.8A Active CN107464787B (en) | 2016-06-02 | 2016-07-25 | Cake-shaped semiconductor packaging structure and combination of wafer-shaped semiconductor packaging structure and carrying disc |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107464787B (en) |
| TW (1) | TWI560123B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1421922A (en) * | 2001-11-30 | 2003-06-04 | 株式会社东芝 | Semiconductor device |
| CN102479728A (en) * | 2010-11-23 | 2012-05-30 | 罗伯特·博世有限公司 | Method for manufacturing semiconductor chips, mounting method and semiconductor chip for vertical mounting onto circuit substrates |
| TW201613028A (en) * | 2014-09-25 | 2016-04-01 | Nippon Electric Glass Co | Supporting glass substrate and laminate using same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7615836B2 (en) * | 2005-03-07 | 2009-11-10 | Sensormatic Electronics Corporation | Magnetic self-assembly for integrated circuit packages |
| JP5606021B2 (en) * | 2009-07-31 | 2014-10-15 | 日置電機株式会社 | Manufacturing method of current sensor |
| TWM521376U (en) * | 2015-12-02 | 2016-05-11 | Libo Cosmetics Co Ltd | Magnetic button positioned powder case |
-
2016
- 2016-06-02 TW TW105117420A patent/TWI560123B/en active
- 2016-07-25 CN CN201610585978.8A patent/CN107464787B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1421922A (en) * | 2001-11-30 | 2003-06-04 | 株式会社东芝 | Semiconductor device |
| CN102479728A (en) * | 2010-11-23 | 2012-05-30 | 罗伯特·博世有限公司 | Method for manufacturing semiconductor chips, mounting method and semiconductor chip for vertical mounting onto circuit substrates |
| TW201613028A (en) * | 2014-09-25 | 2016-04-01 | Nippon Electric Glass Co | Supporting glass substrate and laminate using same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201742802A (en) | 2017-12-16 |
| TWI560123B (en) | 2016-12-01 |
| CN107464787A (en) | 2017-12-12 |
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