TW201737254A - Writing method for resistive memory cell and resistive memory - Google Patents

Abstract

A writing method for a resistive memory cell and a resistive memory using thereof are provided. In the writing method, a group of RESET signals is provided to the resistive memory cell, so as to do a writing operation. A current of the resistive memory cell is detected to determine whether the writing operation of the resistive memory cell is complete or not. When the writing operation of the resistive memory cell is not complete, it is determined that width of filament paths in the resistive memory cell are narrowed or not. The voltage of word line of the resistive memory cell in the second group of RESET signals is reduced when the width of the filament paths in the resistive memory cell are narrowed.

Description

Resistive memory cell writing method and resistive memory

The present invention relates to a resistive memory technology, and more particularly to a resistive memory cell writing method and a resistive memory using the same.

In the Resistive random-access memory (RRAM) technology, three operations of forming, setting, and reset are performed to ensure resistive memory cell characteristics and data retention. Three important steps. When performing a set/reset operation, it may be necessary to increase the input voltage step by step and multiple times to complete. For resistive memory, a successful reset operation increases the durability of the RRAM.

In general, a resistive memory can change the width of a filamentary conductive path depending on the magnitude and polarity of the applied pulse voltage. For example, when writing data logic 1, the width of the wire-shaped conductive path can be narrowed by applying a RESET pulse to form a high resistance state. When the data logic 0 is written, the width of the filament-shaped conductive path can be increased by applying a SET pulse of opposite polarity to form a low resistance state. However, when the resistive memory cell is set or reset by continuously or ramp-increasing the input voltage, the resistive memory cell that should be in a high current state may be reduced in its current, or The resistance of the resistive memory cell that should be in a low current state is increased, resulting in errors in the data stored in the resistive memory cell. This phenomenon is called a complementary switching phenomenon. In other words, when a set operation or reset operation of the resistive memory cell is performed, if an excessive input voltage is supplied, the resistive memory cell may be caused to be contrary to the expectation.

On the other hand, after the resistive memory cell is input with the reset signal/set signal several times, it is found that the resistive memory cell may always be between the high resistance state and the low resistance state, and this state is called a local high resistance state. / Local low resistance state. In order to remove the resistive memory cell from the local high resistance state/local low resistance state, it is necessary to additionally adjust the input voltage of the resistive memory cell.

Therefore, how to avoid the switching of the input voltage in the process of step-up, the voltage of the resistive memory cell is complementary, and the resistive memory cell is separated from the local high-resistance state. / Local low resistance state is one of the important topics.

The present invention provides a method of writing a resistive memory device that enables a resistive memory cell to be removed from a local high resistance state (reset operation) / a local low resistance state (setting operation).

The writing method of the resistive memory cell of the present invention comprises the following steps. A reset signal group is provided to the resistive memory cell for writing operations. The current of the resistive memory cell is detected to determine whether the resistive memory cell completes the write operation. When the resistive memory cell does not complete the writing operation, it is determined whether the width of the filament-shaped conductive path in the resistive memory cell is narrowed. When the width of the filament-shaped conductive path in the resistive memory cell has been narrowed, the word line voltage of the resistive memory cell in the reset signal group is lowered.

In an embodiment of the invention, the writing method further includes: when the width of the filament-shaped conductive path in the resistive memory cell is not narrowed, continuously providing the reset signal group to the Resistive memory cell.

In an embodiment of the invention, the step of continuously providing the reset signal group to the resistive memory cell further comprises: sequentially decreasing a source line of the resistive memory cell in the reset signal group Voltage.

In an embodiment of the invention, the writing method further includes: determining whether the resistive memory cell is written after the word line voltage of the resistive memory cell in the reset signal group is lowered operating.

In an embodiment of the invention, the step of determining whether the resistive memory cell completes the write operation comprises: detecting whether the current in the resistive memory cell is less than a first current threshold.

In an embodiment of the invention, the step of determining whether the width of the filament-shaped conductive path in the resistive memory cell is narrowed comprises: detecting whether a current in the resistive memory cell is greater than a second current threshold The second current threshold is greater than the first current threshold.

In an embodiment of the invention, the writing method is a data reset method of the resistive memory cell.

The resistive memory of the present invention includes a resistive memory cell array and a control circuit. The resistive memory cell array includes at least one resistive memory cell. A control circuit is coupled to the resistive memory cell. The control circuit provides a reset signal group to the resistive memory cell for performing a write operation, and detecting a current of the resistive memory cell to determine whether the resistive memory cell completes a write operation. When the resistive memory cell does not complete the write operation, the control circuit determines whether the width of the filament-shaped conductive path in the resistive memory cell is narrowed. The control circuit reduces the word line voltage of the resistive memory cell in the reset signal group when the width of the filamentary conductive path in the resistive memory cell has narrowed.

The writing method of the resistive memory cell of the present invention comprises the following steps. A reset signal group is provided to the resistive memory cell for writing operations. The current of the resistive memory cell is detected to determine whether the current is less than the first current threshold. Determining whether the current in the resistive memory cell is greater than a second current threshold when the current of the resistive memory cell is not less than the first current threshold, wherein the second current threshold is greater than the first A current threshold. When the current in the resistive memory cell is greater than the second current threshold, the word line voltage of the resistive memory cell in the reset signal group is reduced.

Based on the above, when performing a writing method (eg, a reset operation) of the resistive memory cell, the embodiment of the present invention determines whether the writing in the resistive memory cell is completed by the current of the resistive memory cell, and When the writing is completed, it is judged whether the width of the filament-shaped conductive path is still too wide or has been narrowed. When it is judged that the width of the filament-shaped conductive path in the resistive memory cell has been narrowed, the word line voltage of the resistive memory cell can be sequentially lowered and other reset voltages (eg, source line voltage and The bit line voltage) is such that the resistive memory cell is removed from the local high resistance state (reset operation) / local low resistance state (setting operation) and the data reset of the resistive memory cell is completed. In this way, the writing method extends the voltage window of the reset operation by gradually reducing the word line voltage of the resistive memory cell, thereby reducing the complementary switching phenomenon of the resistive memory cell due to the excessive input voltage. Probability.

The above described features and advantages of the invention will be apparent from the following description.

FIG. 1 is a block diagram of a resistive memory 100 in accordance with an embodiment of the present invention. Referring to FIG. 1 , the resistive memory 100 includes a resistive memory cell array and a control circuit 120 . To simplify the description, one of the resistive memory cells 110 in the resistive memory cell array is shown here. The resistive memory cell array can be provided with a plurality of resistive memory cells 110. In this embodiment, the resistive memory cell 110 includes a switching unit (eg, transistor T1) and a resistor R1. The resistor R1 can be realized by an excessive metal oxide layer, and is not limited thereto. The first end of the resistor R1 is a bit line BL, and the second end of the resistor R1 is coupled to the first end of the transistor T1. The second end of the transistor T1 is the source line SL. The word line signal providing circuit 130 is coupled to the control terminal of the transistor T1 in the resistive memory cell 110, and the control terminal of the transistor T1 may also be referred to as the word line WL of the resistive memory cell 110.

The control circuit in the embodiment of the present invention may be constituted by a plurality of circuit components. The control circuit 120 of this embodiment may include a word line signal providing circuit 130, a bit line signal providing circuit 140, a source line signal providing circuit 150, and a detecting circuit 160. The word line signal providing circuit 130 is coupled to the control terminal of the transistor T1 in the resistive memory cell 110, and the control terminal of the transistor T1 may also be referred to as the word line WL of the resistive memory cell 110. The word line signal providing circuit 130 is for supplying the voltage of the word line WL. The bit line signal supply circuit 140 is coupled to the bit line BL of the resistive memory cell 110 for providing the voltage of the bit line BL. The source line signal providing circuit 150 is coupled to the source line SL of the resistive memory cell 110 for providing the voltage of the source line SL. The detecting circuit 150 detects the current in the resistive memory cell 110 and determines whether the writing operation (eg, forming operation, setting operation or reset operation) is completed by the current in the resistive memory cell 110.

2 is a flow chart of a method of writing resistive memory cells 110 in accordance with an embodiment of the invention. The embodiment of the present invention is a data reset (RESET) method of a resistive memory cell as an example of a writing method. In other embodiments, the data setting (SET) method may also be used as an example of the writing method according to the disclosure of the embodiment. Referring to FIG. 1 and FIG. 2 simultaneously, in step S210, the control circuit 120 provides a reset signal group to the word line WL, the bit line BL, and the source line SL in the resistive memory cell 110 for performing a write operation. In detail, the word line signal providing circuit 130, the bit line signal providing circuit 140, and the source line signal providing circuit 150 in the control circuit 120 respectively provide the word line WL and the bit line BL for performing a write operation. And the voltage signal of the source line SL to the corresponding end point of the resistive memory cell 110. In the embodiment of the present invention, the voltage signals of the word line WL, the bit line BL, and the source line SL for performing the write operation are referred to as a reset signal group.

In step S215, the control circuit 120 detects/monitors the current flowing through the resistive memory cell 110 through the detecting circuit 160. Specifically, the control circuit 120 of the present embodiment continuously supplies the reset signal group to the resistive memory cell 110, and performs step S220 and step S230 while providing the reset signal group. In other words, the control circuit 120 of the embodiment of the present invention can continuously provide the respective voltage signals in the reset signal group to the resistive memory cell 110 instead of using the voltage pulse to perform the writing method. In some embodiments, this writing method can also be performed in the form of a voltage pulse.

Referring back to FIG. 1 and FIG. 2, in step S220, the detecting circuit 160 in the control circuit 120 determines whether the resistive memory cell 110 has completed the writing operation. The detecting circuit 160 of the embodiment determines whether the resistive memory cell 110 completes the writing operation by detecting whether the current flowing through the resistive memory cell 110 is less than a preset first current threshold. When the current in the resistive memory cell 110 has been less than the preset first current threshold, it indicates that the resistive memory cell 110 is already in the high resistance state, and proceeds from step S220 to step S260 to complete the writing method.

In contrast, when the current in the resistive memory cell 110 is greater than the preset first current threshold, it indicates that the resistive memory cell 110 is not yet in the high resistance state and the write operation is not completed. Therefore, the process proceeds from step S220 to step S230, and the control circuit 120 determines whether or not the width of the filament-shaped conductive path in the resistive memory cell 110 is narrowed. In the embodiment of the present invention, it is determined whether the width of the filament-shaped conductive path in the resistive memory cell 110 is narrowed by detecting whether the current in the resistive memory cell 110 is greater than a preset second current threshold (eg, 100 μA). If the current in the resistive memory cell 110 is less than or equal to the preset second current threshold (100 μA) (YES in step S230), it indicates that the width of the filamentary conductive path in the resistive memory cell 110 has been narrowed. In a local high resistance state. Thereby, the process proceeds from step S230 to step S250, and the control circuit 120 lowers the voltage of the word line WL supplied to the resistive memory cell 110 in the reset signal group. In step S250 of the embodiment, the control circuit 120 continues to maintain voltage signals other than the voltage of the word line WL (eg, the source line SL voltage and the bit line BL voltage) without turning off the source line SL voltage and Bit line BL voltage. By lowering the voltage of the word line WL, the resistive memory cell can be removed from the local high resistance state (reset operation) / local low resistance state (setting operation), and the data reset of the resistive memory cell 110 is completed, and the control is gradually reduced. The circuit 120 inputs the current to the resistive memory cell 110 to avoid a complementary switching phenomenon.

After step S250 is performed, the control circuit 120 returns to step S220 to again determine whether the resistive memory cell 110 has completed the write operation. If step S250 is performed continuously and multiple times, the control circuit 120 may successively lower the voltage of the word line WL supplied to the resistive memory cell 110 in the reset signal group, thereby gradually reducing the input from the control circuit 120 to the resistive memory. The current of cell 110.

Returning to step S230 of FIG. 2, if the current in the resistive memory cell 110 is greater than the preset second current threshold (100 μA) (NO in step S230), it indicates that the wire-like conductive in the resistive memory cell 110 The width of the path is not narrowed. Therefore, the process proceeds from step S230 to step S240, and the control circuit 120 continues to provide the reset signal group to the resistive memory cell 110. In the embodiment of the present invention, when continuously providing the reset signal group to the resistive memory cell 110, the control circuit 120 may also sequentially lower the source line SL voltage of the resistive memory cell 110 in the reset signal group. In order to reduce the probability of complementary switching phenomenon of the resistive memory cell 110. When step S240 is performed, it returns to step S230 to determine whether the width of the filament-shaped conductive path in the resistive memory cell 110 is narrowed.

In summary, in the method of writing a resistive memory cell (eg, a reset operation), the embodiment of the present invention determines whether the write of the resistive memory cell is completed by the current of the resistive memory cell, and When the writing is not completed, it is judged whether the width of the filament-shaped conductive path is still too wide or has been narrowed. Moreover, when it is judged that the width of the filament-shaped conductive path in the resistive memory cell has been narrowed, the resistive type can be completed by sequentially reducing the word line voltage of the resistive memory cell and maintaining other reset voltages. The data of the memory cell is reset, and the resistive memory cell is separated from the local high resistance state (reset operation) / local low resistance state (setting operation). In this way, the writing method extends the voltage window of the reset operation by gradually reducing the word line voltage of the resistive memory cell, thereby reducing the complementary switching phenomenon of the resistive memory cell due to the excessive input voltage. Probability.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Resistive memory
110‧‧‧Resistive memory cells
120‧‧‧Control circuit
130‧‧‧Word line signal providing circuit
140‧‧‧ bit line signal supply circuit
150‧‧‧Source line signal supply circuit
160‧‧‧Detection circuit
WL‧‧‧ character line
BL‧‧‧ bit line
SL‧‧‧ source line
R1‧‧‧ resistance
T1‧‧‧O crystal
S210~S260‧‧‧Steps

1 is a block diagram of a resistive memory according to an embodiment of the present invention. 2 is a flow chart of a method of writing a resistive memory cell according to an embodiment of the invention.

S210~S260‧‧‧Steps

Claims (15)

A method for writing a resistive memory cell, comprising: providing a reset signal group to a resistive memory cell for performing a write operation; detecting a current of the resistive memory cell to determine whether the resistive memory cell completes the write operation Determining whether the width of the filamentary conductive path in the resistive memory cell is narrowed when the resistive memory cell does not complete the writing operation; and when the width of the filamentary conductive path is narrow in the resistive memory cell During the conversion, the word line voltage of the resistive memory cell in the reset signal group is lowered. The writing method of claim 1, further comprising: continuously providing the reset signal group to the resistive memory cell when the width of the filamentary conductive path in the resistive memory cell is not narrowed . In the writing method of claim 2, the step of continuously providing the reset signal group to the resistive memory cell comprises: sequentially decreasing a source line of the resistive memory cell in the reset signal group Voltage. The writing method of claim 1, further comprising: after reducing a word line voltage of the resistive memory cell in the reset signal group, determining whether the resistive memory cell completes the writing operation. In the writing method of claim 1, the determining whether the resistive memory cell completes the writing operation comprises: detecting whether the current in the resistive memory cell is less than a first current threshold. The method for determining whether the width of the filament-shaped conductive path in the resistive memory cell is narrowed according to the writing method of claim 5 includes: detecting whether the current in the resistive memory cell is greater than the second a current threshold, wherein the second current threshold is greater than the first current threshold. The writing method of claim 1, wherein the writing method is a data resetting method of the resistive memory cell. A resistive memory comprising: a resistive memory cell array comprising at least one resistive memory cell; and a control circuit coupled to the at least one resistive memory cell, wherein the control circuit provides a reset signal group to the at least one The resistive memory cell performs a write operation to detect a current of the resistive memory cell to determine whether the at least one resistive memory cell completes the write operation, and when the resistive memory cell does not complete the write operation, The control circuit determines whether the width of the filiform conductive path in the at least one resistive memory cell is narrowed, and the control circuit reduces the reset when the width of the filiform conductive path in the at least one resistive memory cell is narrowed The word line voltage of the resistive memory cell in the signal group. The resistive memory of claim 8, wherein the control circuit determines that the width of the filiform conductive path in the at least one resistive memory cell is not narrowed, and continuously provides the reset signal group to the Resistive memory cell. The resistive memory of claim 9, wherein the control circuit sequentially decreases the resistive memory cell in the reset signal group while continuously providing the reset signal group to the resistive memory cell. Source line voltage. The resistive memory of claim 8, after the word line voltage of the resistive memory cell in the reset signal group is lowered, the control circuit determines whether the at least one resistive memory cell completes the write Into the operation. The resistive memory of claim 8, wherein the control circuit detects whether the current in the at least one resistive memory cell is less than a first current threshold to determine whether the at least one resistive memory cell is This write operation is completed. The resistive memory of claim 12, wherein the control circuit detects whether the current in the at least one resistive memory cell is greater than a second current threshold to determine the at least one resistive memory cell Whether the width of the wire-shaped conductive path is narrowed, wherein the second current threshold is greater than the first current threshold. The resistive memory of claim 8, wherein the writing operation is a data reset operation of the at least one resistive memory cell. A method for writing a resistive memory cell, comprising: providing a reset signal group to a resistive memory cell for performing a write operation; detecting a current of the resistive memory cell to determine whether the current of the resistive memory cell is less than a current threshold; determining whether the current of the resistive memory cell is greater than a second current threshold when the current of the resistive memory cell is not less than the first current threshold, wherein the second current threshold is greater than the first a current threshold; and decreasing a word line voltage of the resistive memory cell in the reset signal group when the current of the resistive memory cell is greater than the second current threshold.