TWI812094B - Filament forming method for resistive memory unit - Google Patents
Filament forming method for resistive memory unit Download PDFInfo
- Publication number
- TWI812094B TWI812094B TW111110468A TW111110468A TWI812094B TW I812094 B TWI812094 B TW I812094B TW 111110468 A TW111110468 A TW 111110468A TW 111110468 A TW111110468 A TW 111110468A TW I812094 B TWI812094 B TW I812094B
- Authority
- TW
- Taiwan
- Prior art keywords
- read current
- resistive memory
- saturated
- memory unit
- threshold
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 56
- 229920006395 saturated elastomer Polymers 0.000 claims abstract description 69
- 230000008569 process Effects 0.000 claims abstract description 15
- 238000000465 moulding Methods 0.000 claims description 12
- 230000003247 decreasing effect Effects 0.000 claims description 4
- 210000004027 cell Anatomy 0.000 claims 11
- 210000000352 storage cell Anatomy 0.000 claims 2
- 238000007493 shaping process Methods 0.000 claims 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- -1 oxygen ions Chemical class 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
本發明是有關於一種電阻式記憶體單元的阻絲成型方法。The invention relates to a resistance wire forming method of a resistive memory unit.
電阻式記憶體由於具備低功耗、高速運作、高密度以及相容於互補式金屬氧化物半導體製程技術之潛在優勢,因此非常適合作為下一世代之非揮發性記憶體元件。Resistive memory is very suitable as the next generation of non-volatile memory devices due to its potential advantages of low power consumption, high-speed operation, high density and compatibility with complementary metal oxide semiconductor process technology.
圖1繪示一般1T1R之電阻式記憶體的結構示意圖。如圖1所示,電阻式記憶體通常包括電阻元件R與開關元件T。電阻元件R包括相對配置的上電極14b與下電極14a以及位於上電極14b與下電極14a之間的介電層(例如,過渡金屬氧化物(Transition metal oxide,TMO) 12。在電阻式記憶體可反覆地在高低電阻狀態間切換以記憶資料前,首先需進行阻絲成型(filament forming)的程序。阻絲成型程序包括對電阻式記憶體施加一偏壓。例如在開關元件T之閘極施加閘極電壓Vg,在電阻元件R之上電極14b施加汲極電壓Vd。上述偏壓例如正偏壓,使得介電層中產生氧空缺和氧離子,並使氧離子脫離介電層(TMO)而在介電層中形成電流路徑(阻絲結構),進而使電阻式記憶體自高阻態變為低阻態。之後,可對電阻式記憶體進行重置(RESET)或設定(SET)程序,使電阻式記憶體分別切換為高阻態與低阻態,以完成資料的記憶。Figure 1 shows a schematic structural diagram of a general 1T1R resistive memory. As shown in Figure 1, a resistive memory usually includes a resistive element R and a switching element T. The resistive element R includes an upper electrode 14b and a lower electrode 14a arranged oppositely and a dielectric layer (for example, transition metal oxide (TMO)) 12 located between the upper electrode 14b and the lower electrode 14a. In a resistive memory Before being able to repeatedly switch between high and low resistance states to memorize data, the filament forming process must first be performed. The filament forming process involves applying a bias voltage to the resistive memory. For example, on the gate of the switching element T The gate voltage Vg is applied, and the drain voltage Vd is applied to the electrode 14b above the resistive element R. The bias voltage, such as a forward bias voltage, generates oxygen vacancies and oxygen ions in the dielectric layer, and causes the oxygen ions to escape from the dielectric layer (TMO ) to form a current path (resistance wire structure) in the dielectric layer, thereby changing the resistive memory from a high resistance state to a low resistance state. After that, the resistive memory can be reset (RESET) or set (SET) ) program to switch the resistive memory to a high-resistance state and a low-resistance state respectively to complete the memory of data.
圖2繪示阻絲成型過程中作用在介電層(如TMO)之電壓與成型電流(即成型程序完成後的讀取電流)之關係以及與閘極電壓的相關性。由圖2可以得知,當閘極電壓Vg在1.5V以上時,作用在TMO上的電壓會太小(如圖所示之0.3V以下),因而無足夠的電場推動氧離子脫離TMO。而當閘極電壓Vg太低(如Vg=0.65V)的話,雖然作用在TMO的電壓增加,但成型電流幾乎為0,代表TMO中未產生足夠的氧空缺以形成電流路徑。因此,難以選擇合適的閘極電壓Vg來進行阻絲成型,進而導致成型效率不佳。Figure 2 shows the relationship between the voltage acting on the dielectric layer (such as TMO) and the forming current (i.e., the read current after the forming process is completed) during the resistor wire forming process, as well as the correlation with the gate voltage. It can be seen from Figure 2 that when the gate voltage Vg is above 1.5V, the voltage acting on the TMO will be too small (below 0.3V as shown in the figure), so there is not enough electric field to push oxygen ions out of the TMO. When the gate voltage Vg is too low (such as Vg=0.65V), although the voltage acting on the TMO increases, the forming current is almost 0, which means that there are not enough oxygen vacancies in the TMO to form a current path. Therefore, it is difficult to select an appropriate gate voltage Vg for resistor wire molding, resulting in poor molding efficiency.
圖3繪示習知在阻絲成型後,進行初始(第一次)重置前後的電流變化圖,圖中x軸為初始重置前電流,y軸為初始重置後的電流。阻絲成型後當電流太早而初始重置被執行,重置後很多位元會增加電流而不是減少電流。亦即,成型的阻絲結構可能不夠穩定,而導致電阻式記憶體的可靠度退化。這也會關係到成型效率。Figure 3 shows the current change diagram before and after the initial (first) reset after the resistor wire is formed in the conventional art. The x-axis in the figure is the current before the initial reset, and the y-axis is the current after the initial reset. After the resistor is formed, when the current flows too early and the initial reset is performed, many bits will increase the current after the reset instead of decreasing the current. That is, the formed resistance wire structure may not be stable enough, resulting in degradation of the reliability of the resistive memory. This will also affect molding efficiency.
綜上所述,需要有一種更可靠的成型方式,使足夠的氧離子脫離TMO,形成穩定的阻絲結構,並降低電流尾的狀態產生。In summary, a more reliable molding method is needed to enable enough oxygen ions to escape from the TMO, form a stable resistor wire structure, and reduce the generation of current tails.
根據本發明一實施例,提供一種電阻式記憶體的阻絲成型方法,包括:對所述電阻式記憶體單元施加多次第一偏壓,直到所述電阻式記憶體單元的讀取電流達到第一飽和狀態,其中各次所述第一偏壓包括閘極電壓與汲極電壓;閂鎖所述第一飽和狀態的所述讀取電流作為飽和讀取電流,並判斷所述飽和讀取電流的增加率是否低於一第一閾值;在判斷出所述飽和讀取電流的增加率未低於一第一閾值時,對所述第一偏壓,增加所述閘極電壓並且降低所述汲極電壓,以作為第二偏壓;以所述第二偏壓施加至所述電阻式記憶體單元,直到所述電阻式記憶體單元的所述讀取電流達到第二飽和狀態;閂鎖所述第二飽和狀態的所述讀取電流作為所述飽和讀取電流,並再次判斷所述飽和讀取電流的增加率是否低於所述第一閾值;以及判斷所述飽和讀取電流是否達到目標電流值,並且在達到所述目標電流值的情況下,結束所述成型方法。According to an embodiment of the present invention, a resistance wire forming method for a resistive memory is provided, including: applying a first bias voltage to the resistive memory unit multiple times until the read current of the resistive memory unit reaches a first saturation state, wherein the first bias voltage each time includes a gate voltage and a drain voltage; latch the read current in the first saturation state as a saturated read current, and determine the saturated read Whether the increase rate of the current is lower than a first threshold; when it is determined that the increase rate of the saturated read current is not lower than a first threshold, the gate voltage is increased and the gate voltage is decreased for the first bias voltage. The drain voltage is used as a second bias voltage; the second bias voltage is applied to the resistive memory cell until the read current of the resistive memory cell reaches a second saturation state; latch lock the read current in the second saturated state as the saturated read current, and determine again whether the increase rate of the saturated read current is lower than the first threshold; and determine the saturated read current Whether the target current value is reached, and if the target current value is reached, the forming method is ended.
根據本發明另一實施例,提供一種電阻式記憶體單元的阻絲成型方法,包括:執行第一階段成型程序,以包括閘極電壓與汲極電壓的第一偏壓施加多次到所述電阻式記憶體單元,直到所述電阻式記憶體單元的讀取電流達到第一飽和狀態,閂鎖所述第一飽和狀態的所述讀取電流為飽和讀取電流,並判斷所述飽和讀取電流的增加率是否低於第一閾值;在所述飽和讀取電流的增加率未低於所述第一閾值時,執行第二階段成型程序,以第二偏壓施加多次到所述電阻式記憶體單元,直到所述電阻式記憶體單元的所述讀取電流達到第二飽和狀態,並判斷所述飽和讀取電流的增加率是否低於所述第一閾值,其中所述第二偏壓為增加所述閘極電壓並且降低所述汲極電壓;以及在所述所述飽和讀取電流的增加率低於第一閾值時,並且在所述飽和讀取電流達到目標電流值時,結束所述阻絲成型方法。According to another embodiment of the present invention, a resistance wire forming method of a resistive memory unit is provided, including: performing a first-stage forming process to apply a first bias voltage including a gate voltage and a drain voltage to the said resistive wire multiple times. The resistive memory unit, until the read current of the resistive memory unit reaches a first saturated state, the read current that latches the first saturated state is a saturated read current, and determines that the saturated read current Check whether the increase rate of the current is lower than the first threshold; when the increase rate of the saturated read current is not lower than the first threshold, execute the second stage molding process and apply a second bias voltage to the The resistive memory unit waits until the read current of the resistive memory unit reaches a second saturation state, and determines whether the increase rate of the saturated read current is lower than the first threshold, wherein the third The second bias voltage is to increase the gate voltage and reduce the drain voltage; and when the increase rate of the saturated read current is lower than the first threshold, and when the saturated read current reaches the target current value When, the blocking wire forming method ends.
最基本的電阻式記憶體單元是由一個開關元件(電晶體)和一個電阻元件(1T1R)所構成,電阻元件是由上下兩層金屬電極以及中間一層例如為過渡金屬氧化物(以下稱TMO)的介電層所組成(參考圖1之例子)。以下的實施例將以1T1R結構的電阻式記憶體單元來說明,但是並不局限於此結構,本實施例所揭示的方法也可應用於例如2T1R或2T2R的其他電阻式記憶體單元之結構。The most basic resistive memory unit is composed of a switching element (transistor) and a resistive element (1T1R). The resistive element is composed of upper and lower layers of metal electrodes and a middle layer such as a transition metal oxide (hereinafter referred to as TMO). composed of dielectric layers (refer to the example in Figure 1). The following embodiments will be described with a resistive memory cell of 1T1R structure, but it is not limited to this structure. The method disclosed in this embodiment can also be applied to other resistive memory cell structures such as 2T1R or 2T2R.
圖4繪示本實施例之電阻式記憶體之阻絲成型方法的流程示意圖。圖5A繪示本實施例之電阻式記憶體之阻絲成型方法的流程中的施加電壓的波形圖。FIG. 4 is a schematic flowchart of the resistance wire forming method of the resistive memory in this embodiment. FIG. 5A shows a waveform diagram of the applied voltage in the process of the resistance wire forming method of the resistive memory in this embodiment.
請參照圖4及圖5,首先,對起始高阻態的電阻式記憶體進行第一階段的阻絲成型。在步驟S100,對電阻式記憶體單元施加閘極電壓Vg與汲極電壓Vd (第一偏壓)。閘極電壓Vg與汲極電壓Vd例如是具有一定寬度的脈衝電壓。在此實施例中,第一偏壓的閘極電壓Vg例如是1V,且其脈衝寬度PW例如為50ns;第一偏壓的汲極電壓Vd例如是4V,且其脈衝寬度PW例如為50ns。Please refer to Figures 4 and 5. First, the resistive memory in the initial high-resistance state is subjected to the first stage of resistive wire molding. In step S100, gate voltage Vg and drain voltage Vd (first bias voltage) are applied to the resistive memory cell. The gate voltage Vg and the drain voltage Vd are, for example, pulse voltages with a certain width. In this embodiment, the gate voltage Vg of the first bias is, for example, 1V, and its pulse width PW is, for example, 50 ns; the drain voltage Vd of the first bias is, for example, 4V, and its pulse width PW is, for example, 50 ns.
接著,在步驟S102,對電阻式記憶體單元感測讀取電流Icell,並閂鎖住此讀取電流Icell。例如,在記憶體系統中可以設置暫存器(如移位暫存器)或類似功能的儲存單元來閂鎖住最新的讀取電流Icell。Next, in step S102, the read current Icell is sensed to the resistive memory cell and the read current Icell is latched. For example, a register (such as a shift register) or a storage unit with similar functions can be set up in the memory system to latch the latest read current Icell.
接著,在步驟S104,判斷讀取電流Icell的增加率是否低於第一閾值。當讀取電流Icell的增加率未低於第一閾值時,代表讀取電流Icell尚未達到飽和狀態,此時會持續進行步驟S100、S102、S104的循環,繼續對電阻式記憶體單元施加閘極電壓Vg與汲極電壓Vd(第一偏壓),直到讀取電流Icell的增加率低於第一閾值。Next, in step S104, it is determined whether the increase rate of the read current Icell is lower than the first threshold. When the increase rate of the read current Icell is not lower than the first threshold, it means that the read current Icell has not reached the saturation state. At this time, the cycle of steps S100, S102, and S104 will continue to apply the gate to the resistive memory cell. voltage Vg and drain voltage Vd (first bias voltage) until the increase rate of the read current Icell is lower than the first threshold.
在一實施例中,當透過N位元移位暫存器來儲存讀取電流Icell時,例如可以採用1/2 N作為第一閾值。舉例來說,當透過3位元移位暫存器來儲存讀取電流Icell時,例如可採用1/2 3=0.125作為第一閾值。 In one embodiment, when the read current Icell is stored through the N-bit shift register, for example, 1/2 N can be used as the first threshold. For example, when the read current Icell is stored through a 3-bit shift register, 1/2 3 =0.125 can be used as the first threshold.
在步驟S104中,當判斷出讀取電流Icell的增加率低於第一閾值時,代表讀取電流Icell達到飽和狀態,完成第一階段的阻絲成型。接著在步驟S106,對此讀取電流Icell閂鎖以做為飽和讀取電流。如圖5A所示,第一階段的讀取電流Icell在施加8次第一偏壓(脈衝電壓F1~F8)後達到飽和,此時對應脈衝電壓F8的讀取電流Icell被閂鎖為飽和讀取電流。In step S104, when it is determined that the increase rate of the read current Icell is lower than the first threshold, it means that the read current Icell has reached a saturated state, and the first stage of resistor wire forming is completed. Then in step S106, the read current Icell is latched as the saturated read current. As shown in Figure 5A, the read current Icell in the first stage reaches saturation after applying the first bias voltage (pulse voltage F1~F8) 8 times. At this time, the read current Icell corresponding to the pulse voltage F8 is latched to the saturated read state. Take current.
接著,在步驟S110,判斷飽和讀取電流的增加率是否低於一第二閾值。當飽和讀取電流的增加率未低於第二閾值時,代表介電層(TMO)中仍可進一步產生氧空缺及氧離子,所成型的阻絲結構仍未達到穩定的狀態,此時會繼續對電阻式記憶單元進行第二階段的阻絲成型,此時電阻式記憶體為起始低阻態。Next, in step S110, it is determined whether the increase rate of the saturated read current is lower than a second threshold. When the increase rate of the saturated read current is not lower than the second threshold, it means that further oxygen vacancies and oxygen ions can still be generated in the dielectric layer (TMO), and the formed resistance wire structure has not yet reached a stable state. At this time, Continue to perform the second stage of resistive wire molding on the resistive memory unit. At this time, the resistive memory unit is in an initial low-resistance state.
在一實施例中,當透過N位元移位暫存器來閂鎖飽和讀取電流時,例如可採用1/2 N作為第二閾值。類似地,當透過3位元移位暫存器來閂鎖飽和讀取電流時,例如可採用1/2 3=0.125作為第二閾值。 In one embodiment, when latching the saturation read current through the N-bit shift register, for example, 1/2 N may be used as the second threshold. Similarly, when latching the saturation read current through a 3-bit shift register, for example, 1/2 3 =0.125 can be used as the second threshold.
在步驟S110,當飽和讀取電流的增加率未少於第二臨界值時,執行步驟S112,提高閘極電壓Vg並且降低汲極電壓Vd以作為第二偏壓。之後,回到步驟S100,對電阻式記憶體單元施加閘極電壓Vg及汲極電壓Vd(第二偏壓),並重新進行步驟S100~S104的循環,直到讀取電流Icell重新達到飽和狀態(讀取電流Icell的增加率低於第一閾值)後,再次閂鎖飽和讀取電流Icell(步驟S106)。如圖5A的第二階段所示,本實施例中,當判斷出飽和讀取電流的增加率尚未低於第二閾值時,則將閘極電壓Vg提高為1.5V,將汲極電壓降低為3V以作為第二偏壓,並在對電阻式記憶體單元施加3次第二偏壓P1~P3後,電阻式記憶體單元的讀取電流Icell再次達到飽和狀態。此時對應脈衝電壓P3的讀取電流Icell被閂鎖為飽和讀取電流。同樣地,當再次判斷出飽和讀取電流的增加率尚未低於第二閾值時,先將閘極電壓Vg提高為2V,將汲極電壓降低為2.5V以作為第三偏壓,並在對電阻式記憶體單元施加2次第三偏壓2P1~2P2後,電阻式記憶體單元的讀取電流Icell再次達到飽和狀態。此時對應脈衝電壓2P2的讀取電流Icell被閂鎖為飽和讀取電流。In step S110, when the increase rate of the saturated read current is not less than the second critical value, step S112 is performed to increase the gate voltage Vg and decrease the drain voltage Vd as the second bias voltage. After that, return to step S100, apply gate voltage Vg and drain voltage Vd (second bias) to the resistive memory cell, and repeat the cycle of steps S100 to S104 until the read current Icell reaches the saturated state again ( After the increase rate of the read current Icell is lower than the first threshold), the saturated read current Icell is latched again (step S106). As shown in the second stage of Figure 5A, in this embodiment, when it is determined that the increase rate of the saturated read current has not been lower than the second threshold, the gate voltage Vg is increased to 1.5V and the drain voltage is reduced to 3V is used as the second bias voltage, and after applying the second bias voltage P1 to P3 to the resistive memory unit three times, the read current Icell of the resistive memory unit reaches a saturated state again. At this time, the read current Icell corresponding to the pulse voltage P3 is latched to the saturated read current. Similarly, when it is determined again that the increase rate of the saturated read current has not been lower than the second threshold, the gate voltage Vg is first increased to 2V, the drain voltage is reduced to 2.5V as the third bias voltage, and then the After the third bias voltage 2P1~2P2 is applied to the resistive memory unit twice, the read current Icell of the resistive memory unit reaches a saturated state again. At this time, the read current Icell corresponding to the pulse voltage 2P2 is latched to the saturated read current.
如圖4及圖5A所示,在判斷出飽和讀取電流的增加率低於第二閾值前,本實施例會持續調整對電阻式記憶單元施加的偏壓電壓直到飽和讀取電流的增加率低於第二閾值。在此,偏壓電壓中閘極電壓Vg的增加量與汲極電壓Vd的減少量並未特別限定。As shown in FIG. 4 and FIG. 5A , before it is determined that the increase rate of the saturated read current is lower than the second threshold, this embodiment will continue to adjust the bias voltage applied to the resistive memory cell until the increase rate of the saturated read current is low. at the second threshold. Here, the amount of increase in the gate voltage Vg and the amount of decrease in the drain voltage Vd in the bias voltage are not particularly limited.
回到步驟S110,當判斷出飽和讀取電流的增加率低於第二閾值時,代表阻絲結構已達到穩定的狀態,完成第二階段的阻絲成型。接著進行最終驗證階段,驗證電阻式記憶單元的飽和讀取電流是否已經達到目標電流值。具體而言,進行步驟S120,判斷飽和讀取電流是否已經達到目標電流值。當判斷出飽和讀取電流達到目標電流值時,結束本發明的阻絲成型方法。反之,當判斷出飽和讀取電流尚未達到目標電流值時,則執行步驟S122,將閘極電壓Vg與汲極電壓Vd均提高,並在步驟S124對電阻式記憶單元施加提高的閘極電壓Vg與汲極電壓Vd。接著,在步驟S126中重新感測讀取電流Icell並判斷讀取電流Icell是否達到目標電流值。若已達到目標電流值,則結束本實施例的阻絲成型方法。反之,則再次執行步驟S122、S124及S126的循環,直到讀取電流Icell達到目標電流值。Returning to step S110, when it is determined that the increase rate of the saturated reading current is lower than the second threshold, it means that the resistor wire structure has reached a stable state, and the second stage of resistor wire forming is completed. Then a final verification stage is carried out to verify whether the saturated read current of the resistive memory cell has reached the target current value. Specifically, step S120 is performed to determine whether the saturated read current has reached the target current value. When it is determined that the saturated reading current reaches the target current value, the resistor wire forming method of the present invention ends. On the contrary, when it is determined that the saturated read current has not reached the target current value, step S122 is executed to increase both the gate voltage Vg and the drain voltage Vd, and in step S124, the increased gate voltage Vg is applied to the resistive memory cell. and drain voltage Vd. Next, in step S126, the read current Icell is sensed again and it is determined whether the read current Icell reaches the target current value. If the target current value has been reached, the resistor wire forming method of this embodiment is ended. Otherwise, the loop of steps S122, S124 and S126 is executed again until the reading current Icell reaches the target current value.
圖6A繪示利用本實施例之阻絲成型方法後的初始重置前電流與初始重置後電流的分布圖。圖6B繪示利用習知圖5B之阻絲成型方法後的初始重置前電流與初始重置後電流的分布圖。如圖6A所示,在利用本實施例如圖4的流程進行阻絲成型後,電阻式記憶單元具有明顯的低電阻狀態(初始重置前的電流高),並且在進行初始重置後幾乎沒有電流尾出現在圖6A之虛線上方。因此,可以看出本發明成型的阻絲結構具有穩定的狀態,並可避免大電流尾的產生。FIG. 6A shows the distribution diagram of the current before initial reset and the current after initial reset using the resistor wire forming method of this embodiment. 6B shows the distribution diagram of the current before initial reset and the current after initial reset using the conventional resistance wire forming method of FIG. 5B. As shown in Figure 6A, after using the process of Figure 4 to perform resistance wire molding in this embodiment, the resistive memory unit has an obvious low resistance state (high current before initial reset), and has almost no resistance after the initial reset. The current tail appears above the dashed line in Figure 6A. Therefore, it can be seen that the resistor wire structure formed in the present invention has a stable state and can avoid the generation of large current tails.
反之,作為對比,通過如圖5B所示之習知阻絲成型方法之電壓施加方式,由圖6B可以看出其無法形成明顯的低電阻狀態(初始重置前的電流低),且在進行初始重置後虛線上方仍有很多的電流尾,所成型的阻絲結構並不穩定,可靠度不佳。On the contrary, as a comparison, through the voltage application method of the conventional resistance wire forming method as shown in Figure 5B, it can be seen from Figure 6B that it cannot form an obvious low resistance state (the current before the initial reset is low), and during the After the initial reset, there is still a lot of current tail above the dotted line. The formed resistance wire structure is not stable and has poor reliability.
如上所述,本實施例的阻絲成型方法會先通過兩階段的阻絲成型重複驗證成型的阻絲結構是否達到穩定的狀態,並在判斷出成型的阻絲結構已經穩定後,才會進一步驗證電阻式記憶單元的讀取電流是否已經達到目標電流值。相對於習知的方法在未判斷阻絲結構是否穩定時,即直接驗證讀取電流是否達到目標電流值。本實施例的阻絲成型方法,可有效地降低電流尾的產生,提高電阻式記憶單元的可靠度。As mentioned above, the resistance wire forming method of this embodiment will first repeatedly verify whether the formed resistance wire structure has reached a stable state through two stages of resistance wire forming, and only after it is determined that the formed resistance wire structure has been stabilized, further steps will be taken. Verify that the read current of the resistive memory cell has reached the target current value. Compared with the conventional method, when it is not judged whether the resistance wire structure is stable, it is directly verified whether the read current reaches the target current value. The resistance wire forming method of this embodiment can effectively reduce the generation of current tails and improve the reliability of the resistive memory unit.
12:介電層 (TMO) 14a:下電極 14b:電極 T:開關元件 R:電阻元件 Vg:閘極電壓 Vd:汲汲電壓 S100~S236:各步驟12: Dielectric layer (TMO) 14a: Lower electrode 14b:Electrode T: switching element R: Resistor element Vg: gate voltage Vd: drain voltage S100~S236: Each step
圖1繪示一般1T1R之電阻式記憶體的結構示意圖。 圖2繪示阻絲成型過程中作用在介電層之電壓與成型電流之關係以及與閘極電壓的相關性。 圖3繪示習知初始重置前電流與初始重置後電流的相關分布圖。 圖4繪示本實施例之電阻式記憶體之阻絲成型方法的流程示意圖。 圖5A繪示本實施例之電阻式記憶體之阻絲成型方法的一個偏壓施加例。 圖5B繪示習知之阻絲成型方法的偏壓施加方式。 圖6A繪示利用本實施例之成型程序後起始電流與重置後電流的分布圖。 圖6B繪示利用習知圖5B之成型程序後起始電流與重置後電流的分布圖。 Figure 1 shows a schematic structural diagram of a general 1T1R resistive memory. Figure 2 shows the relationship between the voltage acting on the dielectric layer and the forming current during the resistor wire forming process, as well as the correlation with the gate voltage. FIG. 3 illustrates the correlation distribution diagram of the conventional current before initial reset and the current after initial reset. FIG. 4 is a schematic flowchart of the resistance wire forming method of the resistive memory in this embodiment. FIG. 5A illustrates an example of bias voltage application in the resistance wire forming method of the resistive memory in this embodiment. FIG. 5B illustrates a bias voltage application method in a conventional resistor wire forming method. FIG. 6A shows the distribution diagram of the initial current and the current after reset using the molding process of this embodiment. FIG. 6B shows the distribution diagram of the initial current and the current after reset using the conventional molding process of FIG. 5B.
S100~S126:各步驟 S100~S126: Each step
Claims (14)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW111110468A TWI812094B (en) | 2022-03-22 | 2022-03-22 | Filament forming method for resistive memory unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW111110468A TWI812094B (en) | 2022-03-22 | 2022-03-22 | Filament forming method for resistive memory unit |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI812094B true TWI812094B (en) | 2023-08-11 |
TW202338832A TW202338832A (en) | 2023-10-01 |
Family
ID=88585555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111110468A TWI812094B (en) | 2022-03-22 | 2022-03-22 | Filament forming method for resistive memory unit |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI812094B (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI393216B (en) * | 2007-11-01 | 2013-04-11 | Ind Tech Res Inst | Resistance memory and method for manufacturing the same |
TWI643194B (en) * | 2017-10-11 | 2018-12-01 | 華邦電子股份有限公司 | Operating method of resistive memory storage apparatus |
TWI647704B (en) * | 2018-01-17 | 2019-01-11 | 華邦電子股份有限公司 | Power on reset method for resistive memory storage device |
TW202141480A (en) * | 2016-09-21 | 2021-11-01 | 中國大陸商合肥睿科微電子有限公司 | Techniques for initializing resistive memory devices |
-
2022
- 2022-03-22 TW TW111110468A patent/TWI812094B/en active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI393216B (en) * | 2007-11-01 | 2013-04-11 | Ind Tech Res Inst | Resistance memory and method for manufacturing the same |
TW202141480A (en) * | 2016-09-21 | 2021-11-01 | 中國大陸商合肥睿科微電子有限公司 | Techniques for initializing resistive memory devices |
TWI643194B (en) * | 2017-10-11 | 2018-12-01 | 華邦電子股份有限公司 | Operating method of resistive memory storage apparatus |
TWI647704B (en) * | 2018-01-17 | 2019-01-11 | 華邦電子股份有限公司 | Power on reset method for resistive memory storage device |
Also Published As
Publication number | Publication date |
---|---|
TW202338832A (en) | 2023-10-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9378817B2 (en) | Variable resistance nonvolatile memory element writing method and variable resistance nonvolatile memory device | |
US9171616B2 (en) | Memory with multiple levels of data retention | |
TWI732723B (en) | Resistive random-access memory cell and associated array structure | |
Chien et al. | Multi-level 40nm wo x resistive memory with excellent reliability | |
US9627060B2 (en) | Memory circuit and method of programming memory circuit | |
US9208876B1 (en) | Verify pulse delay to improve resistance window | |
Stoliar et al. | Nonvolatile multilevel resistive switching memory cell: A transition metal oxide-based circuit | |
US8995167B1 (en) | Reverse program and erase cycling algorithms | |
JP5707288B2 (en) | Semiconductor memory device and driving method thereof | |
TW201926345A (en) | Memory device and method of operating the same | |
US9336874B2 (en) | Mixed mode programming for phase change memory | |
CN110060722B (en) | Power-on reset method of resistive memory storage device | |
TW202044490A (en) | RANDOM ACCESS MEMORY CELL AND METHOD of OPERATING RESISTIVE RANDOM ACCESS MEMORY CELL | |
TW201715526A (en) | Operating method for resistive memory cell and resistive memory | |
US9734908B1 (en) | Writing method for resistive memory cell and resistive memory | |
TWI812094B (en) | Filament forming method for resistive memory unit | |
US11972799B2 (en) | Filament forming method for resistive memory unit | |
US11437101B2 (en) | Resistive memory storage apparatus and operating method thereof | |
CN116935924A (en) | Wire blocking forming method of resistive memory unit | |
TWI595486B (en) | Writing method for resistive? memory cell and resistive memory | |
TWI686803B (en) | Programming method of reram memory and voltage programming method of memory cell | |
Ueki et al. | Stabilizing schemes for the minority failure bits in Ta 2 O 5-based ReRAM macro | |
TWI633558B (en) | Operating method of resistive memory storage apparatus | |
TWI647704B (en) | Power on reset method for resistive memory storage device | |
Li et al. | Methods to Realize Low-BER and High-Reliability RRAM Chip With Fast Page-Forming Capability |