WO2014025434A2

WO2014025434A2 - Complementary resistive switching in single resistive memory devices

Info

Publication number: WO2014025434A2
Application number: PCT/US2013/041046
Authority: WO
Inventors: Wei Lu; Yuchao YANG
Original assignee: The Regents Of The University Of Michigan
Priority date: 2012-05-15
Filing date: 2013-05-15
Publication date: 2014-02-13
Also published as: WO2014025434A3

Abstract

A single resistive memory device comprises a first metal oxide layer and a second metal oxide layer. The second metal oxide layer is located underneath the first metal oxide layer, and has a different stoichiometry than the second metal oxide layer. In embodiment, the first and second metal oxide layers each comprise different oxides of the same base metal, and the base metal may comprise tantalum. An article of manufacture comprising a single resistive memory device that is operable in a complementary resistive switching mode is also provided.

Description

COMPLEMENTARY RESISTIVE SWITCHING

IN SINGLE RESISTIVE MEMORY DEVICES

STATEMENT OF FEDERALLY-SPONSORED RESEARCH

This invention was made with government support under ECCS0954621 awarded by the National Science Foundation and FA9550-12-1-0038 awarded by the Air Force Office of Scientific Research. The government has certain rights in the invention.

TECHNICAL FIELD

This invention relates generally to resistive memory devices and, more particularly, to resistive memory devices that are operated in a complementary resistive switching mode and that may be used in resistive random access memory (RRAM).

BACKGROUND

Resistive random access memory (RRAM) has shown great potential as a leading candidate for next-generation nonvolatile memory technology. RRAM devices integrated in passive crossbar arrays have promised low energy consumption and excellent scalability by producing the smallest cell size in theory, i.e. 4F²/n, where F is the minimum feature size and n is the layer number when 3-dimentional stacking is used. However, challenges arise when one tries to read a specific memory cell in the passive crossbar array due to the so-called sneak path problem, which is caused by the parasitic current flowing through undesignated devices at ON-state in the crossbar network. Various "selector" elements with rectifying behavior, e.g. diodes and metal-insulator transition switches, have been explored to address the sneak path problem with limited success. Recently the concept of complementary resistive switch (CRS) has attracted significant research interest as it bypasses the issues related to the use of external diodes or other volatile switches. A typical CRS is composed of two RRAM cells anti-serially stacked together by sharing a common electrode. By design one of the cells in CRS will always be in an OFF state at low voltage so the CRS can effectively suppress the sneak current. When sufficient voltage is applied (e.g., read voltage across the target device) both cells are turned ON to allow the target cell to be read. This concept provides an intriguing prospect for addressing the sneak path problem without introduction of any selector elements. However, potential issues related to CRS include the complexity involved in fabricating two cells back-to-back and possible degradation of the internal common electrode.

SUMMARY

According to one aspect of the invention, there is provided an article of manufacture comprising a single resistive memory device operable in a complementary resistive switching mode. In an embodiment, the single resistive memory device comprises a first metal oxide layer and a second metal oxide layer located underneath the first metal oxide layer.

According to another aspect of the invention, there is provided a resistive memory device comprising a first metal oxide layer and a second metal oxide layer located underneath the first metal oxide layer. In an embodiment, the first and second metal oxide layers each comprise different oxides of the same base metal, which, in an embodiment, comprises tantalum.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred exemplary embodiments will hereinafter be described in conjunction with the appended drawings, wherein like designations denote like elements, and further wherein:

Fig. 1(a) is a diagrammatic and schematic illustration of an embodiment of a resistive memory device;

Fig. 1(b) is a graph illustrating an I-V curve of an exemplary implementation of the resistive memory device illustrated in Fig. 1(a) showing bipolar resistive switching;

Fig. 1(c) is a graph illustrating the endurance of an exemplary implementation of the resistive memory device illustrated in Fig. 1(a); Fig. 1(d) is a graph illustrating the retention of an exemplary implementation of the resistive memory device illustrated in Fig. 1(a);

Fig. 2(a) is a graph illustrating an I-V curve of an exemplary implementation of the resistive memory device illustrated in Fig. 1(a) showing complementary resistive switching behavior;

Figs. 2(b)-2(e) is a diagrammatic and schematic illustration of complementary resistive switching processes in an exemplary implementation of the resistive memory device illustrated in Fig. 1(a), wherein Figs. 2(b)-2(e) each correspond to a respective one (1) of four (4) different states; Figs. 3(a) and 3(b) are graphs illustrating bipolar resistive switching and complementary resistive switching, respectively, of an exemplary implementation of the resistive memory device illustrated in Fig. 1(a) in pulse mode;

Fig. 4 is a graph illustrating endurance of complementary resistive switching in an exemplary implementation of the resistive memory device illustrated in Fig. 1(a);

Fig. 5(a) is a graph illustrating bipolar resistive switching characteristics of an exemplary implementation of the resistive memory device illustrated in Fig. 1(a) recovered with asymmetric bias;

Fig. 5(b) is a graph illustrating bipolar resistive switching characteristics of an exemplary implementation of the resistive memory device illustrated in Fig. 1(a) with reverse switching polarities;

Fig. 5(c) is a graph illustrating complementary resistive switching characteristics of an exemplary implementation of the resistive memory device illustrated in Fig. 1(a); and Fig. 5(d) is a graph illustrating I-V characteristics of an exemplary implementation of the resistive memory device illustrated in Fig. 1(a) showing bipolar switching at low temperature and complementary switching at high temperature in the same voltage range. DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Described and shown herein are embodiments of a single resistive memory device that may be operated using complementary resistive switching (CRS) modes and that may be fabricated in crossbar arrays to form RRAM devices that may be operated without encountering sneak paths currents that may otherwise impair proper memory cell readout.

The embodiment described below utilizes CRS behavior in a single tantalum oxide-based RRAM cell or device. Also, as discussed below, prototype testing has shown that complementary switching is in fact more natural than conventional bipolar switching when the cell or device does not have strong asymmetry. Tantalum oxide has become a leading material for RRAM research due to demonstrated superior memory performance metrics in many aspects including endurance up to 10¹², switching speed of <1 ns, and device size down to 30 nm. Realization of complementary switching in tantalum oxide-based RRAM is thus of significant importance in facilitating subsequent array-level implementations.

With reference to Fig. 1(a), there is shown an embodiment of a resistive memory device 10. The memory device 10 is based on a Pd/Ta₂0_5-x/TaO /Pd structure having a functional layer composed of two layers of tantalum oxides with different stoichiometries: a first, oxygen-rich Ta₂0_5-x layer 12 at the top and a second, oxygen-deficient TaO_y layer 14 at the bottom. Due to the different oxygen compositions of the Ta₂Os_-x and TaO_y layers 12, 14, oxygen vacancies (Vo) can be exchanged between the two layers upon application of external electric stimuli, leading to controllable resistive switching. In one embodiment, the TaO_y layer 14 has a thickness of approximately 60 nm, though the present disclosure is not limited to such a dimension, and may be deposited by direct current (DC) reactive sputtering of a tantalum metal target in Ar/0₂ gas mixture at 400 °C. The Ta₂Os_-x layer 12 may be thinner than the layer 14— in one embodiment having a thickness of approximately 5 nm, though the present disclosure is not limited to such a dimension— and may deposited by radio frequency sputtering of a tantalum oxide ceramic target with a nominal composition of Ta₂Os at room temperature. In an embodiment, the depositing of the layer 12 is performed subsequent to the depositing of the layer 14. In an embodiment, the oxygen partial pressure during reactive sputtering of TaO_y may be varied in the range of 3%-15% in order to change the Vo concentration in the TaOy layer 14 and modulate the switching behavior of the device 10. As illustrated in Fig. 1(a), in addition to layers 12, 14, the device 10 may further comprise upper and lower electrodes 16, 18 that, in an embodiment, are formed of palladium (Pd). In the illustrated embodiment, the layers 12, 14 are disposed between the electrodes 16, 18 and, in at least one embodiment, are in direct contact with each other. While Fig. 1(a) illustrates a single resistive memory device 10, in practice a plurality of such devices 10 may be arranged together to form a crossbar memory array. The crossbar memory array may include upper row electrodes and lower column electrodes connected to the array of memory devices 10 such that each of the single memory devices 10 may be individually addressed using a respective pair of upper and lower electrodes.

To validate the operation of the device 10, various implementations of the device 10 having sizes ranging from 0.5 x 0.5 to 2 x 2 μιη² were fabricated and studied. The devices 10 were fabricated in a crossbar structure with electrodes 16, 18 patterned through traditional photolithography, e-beam evaporation, and lift-off processes. Electrical measurements were performed using a low-noise Keithley 4200 semiconductor characterization system or a customized measurement system in combination with a temperature-variable probe station (Desert Cryogenics TTP4). The bias voltage was always applied to the top electrode 16 with the bottom electrode 18 grounded during measurements.

Figure 1(b) illustrates a typical current-voltage (I-V) curve of an exemplary implementation of the device 10. In this implementation, the device 10 is Pd/Ta₂05. _x/3%- TaOy/Pd device. As illustrated, the device 10 shows well-defined bipolar resistive switching with low threshold voltages. In an embodiment, it can be set from an OFF- (high-resistance) state to an ON- (low-resistance) state at— 0.9 V, and reset from the ON-state to the OFF-state at ~ 1.1 V. The inset in Fig. 1(b) displays the same I-V curve in logarithmic scale highlighting the different resistance states and the switching effects. During the study, an electroforming process that involves the application of negative voltage up to -4 - -5 V was typically required before resistive switching effects such as those shown in Fig. 1(b) were observed. The resistive switching can be understood based on the Vo exchange between the Ta₂05_-X and TaOy layers 12, 14. Because the two tantalum oxide layers 12, 14 are in series, the device resistance is mainly determined by the oxygen-rich Ta₂0_5-X layer 12. As a consequence, a negative voltage attracts Vo to the Ta₂0_5-X layer 12 and turns the device to the ON state, while a positive voltage repels the Vo from the Ta₂0_5-X layer 12 and switches the device back to the OFF state. In agreement with reported high performance of tantalum oxide-based RRAM devices, implementations of the device 10 fabricated and tested in this study showed good RRAM characteristics including low switching threshold voltages (~1 V), endurance of > 2000 cycles without any degradation (as displayed in Fig. 1(c), which corresponds to a "Write" pulse of -2 V, 5 ms; an "Erase" pulse of 2 V, 5 ms; and a "Read" pulse of -0.6 V, 300 μβ), and data retention time of >3600 s (as shown in Fig. 1(d), which corresponds to a "Read" pulse of -0.6 V, 10 ms).

Through testing and study, it was been determined that the device 10 can demonstrate CRS behavior when applied with a proper voltage range. As shown in Fig. 2(a), when a device 10, which comprises a Pd/Ta₂O_5-x/10%-TaOy /Pd device, was programmed in a larger voltage range of (-2, 2) V, the device 10 exhibited an I-V characteristic that is different from that in Fig. 1(b). Here the device resistance remains high at low bias voltages and can be switched to a low-resistance state with a negative voltage in the range of ~ -l - -1.8 V or a positive voltage in the range of ~ 1 - 1.8 V. When the voltage is increased further, however, the device is switched back to high-resistance again at either polarity. This behavior is analogous to that of anti- serially stacked CRSs. In a CRS, the device state "0" or "1" is not represented by the overall device resistance but instead by the different internal configurations of the device. Both "0" and "1" states show high resistance at low bias so the device provides the capability of suppressing sneak current in crossbar arrays. The difference in device states can be read out at a read voltage above a threshold (e.g. in regions marked with "Read" in Fig. 2(a)). Read is destructive in this case and the device state needs to be written back at even higher voltages (e.g. regions marked with "Write" and "Erase" in Fig. 2(a)). Specifically, in the case of the studied or tested implementations of the device 10, the processes can be explained by the redistribution of Vo inside the two tantalum oxide layers 12, 14 as schematically shown in Figs. 2(b)-2(e). The initial state (1) of the device is illustrated in Fig. 2(b) where the top Ta205_-X layer 12 is essentially depleted of Vo so the overall resistance of the device is high. At negative voltages below -I V (same threshold voltage for regular resistive switching in Fig. 1), Vo migration into and the formation of conducting paths in the Ta₂05_-X layer 12 cause the overall conductance to increase. The device 10 reaches an intermediate state (2), as illustrated in Fig. 2(c). However, at even higher negative voltages, the bottom TaOy layer 14 can be depleted of Vo and the device 10 reaches another state (3), as schematically illustrated in Fig. 2(d). Both states (3) and (1) show high resistances at low biases but represent different internal Vo distribution profiles, as shown in Figs. 2(b) and 2(d), respectively. Their differences can be observed at proper read voltages (e.g. read regions (2) in Fig. 2(a)). These two states (1) and (3) can then be used for data storage as "1" and "0" states of the device 10, respectively. Similar effects also occur at positive biases (See Figs. 2(a) and 2(e)).

As illustrated in Figs. 3(a) and 3(b) similar effects can also be obtained during pulse operations. Since the "1" and "0" states in CRS correspond to different internal configurations of the cell or device 10 instead of the overall high and low conductance states, both states can produce either a high or a low read current depending on the polarity of the read voltage as illustrated. This behavior is unique to CRS cells or devices and distinct from the normal resistive switching (RS) behavior where the ON state will always produce high read current and vice versa. The signatures of CRS can be clearly observed during pulse operations and are distinct from those of normal RS modes. Figures 3(a) and 3(b) show results obtained from the normal bipolar RS and CRS modes in pulse measurements, respectively, where the device 10 comprises a Pd/Ta₂0_5-x/12%-TaCv /Pd device. Using a "Write" pulse of -1.2 V, 10 ms, and an "Erase" pulse of 1.5 V, 10 ms, the device can be switched between the high- conductance ON state and low-conductance OFF state in the normal RS mode, as shown in Fig. 3(a), where both negative "Read-" and positive "Read+" pulses with the same amplitude of 0.5 V result in the same high or low current response, as expected. Similar with the case in DC sweeps, CRS behavior can be obtained by pulses with increased amplitudes, i.e., by applying "Write" pulse of 2.5 V, 10 ms, and "Erase" pulse of -2.5 V, 10 ms, as shown in Fig. 3(b). However, since the "1" and "0" states in CRS correspond to different internal configurations of the cell or device instead of the overall high and low conductance states, both states can produce either a high or a low read current depending on the polarity of the read voltage (e.g. both states can be brought into the conducting intermediate states during read, Fig. 2(b)-(e)). This behavior is unique to CRS cells or devices and is clearly different from the normal RS behavior. As shown in Fig. 3(b), state "0" of the CRS cell after "Erase" shows a large read current under a positive "Read+" pulse but a low read current under a negative "Read-" pulse, while state "1" after "Write" shows a large read current under a negative "Read-" pulse but a low read current under a positive "Read+" pulse. Both "Read+" and "Read-" pulses have the same amplitude of 1.3 V. This effect can then be used during pulse operations to verify the CRS nature of the device. As illustrated in Fig. 4, over 160 write/read/erase/read cycles have also been obtained from the aforementioned "non-optimized" devices (e.g., device 10 comprising a Pd/Ta₂O5-x/10%-TaO /Pd device and corresponding to: a "Write" pulse of 2 V, 5 ms; an "Erase" pulse of -2V, 5 ms; and a "Read" pulse of -1.2 V, 300 μ8), further verifying the feasibility of obtaining CRS in a single cell or device 10. The nature of the CRS behavior has also been verified by a number of control experiments. Significantly, complementary switching is found to be more natural in cells without strong asymmetry, and for the device 10 is directly tied to the observation of switching polarity reversal. Figure 5(a) shows the I-V characteristics of an exemplary implementation of the device 10 in a voltage range of (-1, 1.4) V, where similar bipolar RS as in Fig. 1(b) is observed. Here the device 10 only switches between states (1) and (2) and never reaches state (3) since the negative bias was not high enough to sufficiently deplete Vo in the TaO layer 14. This condition is similar to the switching conditions in Fig. 1(b). On the other hand, reversed switching polarity in the same device can be obtained by applying an asymmetric bias that is heavy on the negative side, e.g. (-1.4, 1) V in Fig. 5(b). Contrary to the switching polarity shown in Figs. 1(b) and 5(a), the set process in Fig. 5(b) was triggered by a positive voltage, while the reset process took place under a negative bias. While this behavior may seem counterintuitive, it is in fact fully expected in devices exhibiting CRS. Here the device switches between states (3) and (4) and never reaches state (1). It is noteworthy that CRS was immediately regained in the same device when the voltage range was enlarged to (-2, 2) V again, as demonstrated in Fig. 5(c), indicating that the depletion of Vo under high voltages is indeed the mechanism of the complementary switching behavior in Pd/Ta₂05-x/TaO /Pd devices. In general, to observe bipolar switching with a fixed polarity, some type of symmetry breaking is necessary. The symmetry breaking can be achieved by using an asymmetric electrode structure (e.g., using an active electrode as the anode and inert electrode as the cathode in filament-based memories), or an asymmetric switching layer stack. On the other hand, to observe CRS effects a symmetric device structure is needed so all four (4) different state configurations can be accessed.

As will be appreciated in view of the above, in studies on various implementations of device 10, the effect of oxygen partial pressure during the TaO_y layer 14 growth with various 0₂ partial pressures from 3% to 15% were explored. It was observed that devices fabricated with TaO layers 14 in a low 0₂ partial pressure (e.g., 3% such as the device in Fig. 1(b)) exhibit reliable, conventional bipolar switching due to the abundance of Vo in the TaO_y layer 14 and the resulting asymmetric Vo profile so state (3) is difficult to reach during normal device operations. On the other hand, CRS can be reliably observed for devices fabricated with TaOy layers 14 in a high 0₂ partial pressure (e.g., 10% such as the device corresponding to Figs. 2(a) and 5(a)-5(d)) due to the more symmetric Vo profile. In this case, regular bipolar RS can be obtained by breaking the symmetry through other means, such as using the asymmetric programming voltages in Figs. 5(a) and 5(b). It is also possible to obtain bipolar switching between states (l)-(2) or (3)-(4) at low voltage ranges by choosing the proper initial state (e.g. state (1) or (3)), but asymmetric biasing is necessary to ensure reliable bipolar switching in otherwise symmetric devices.

Temperature-dependent studies were also conducted to further test and verify the proposed physical picture of the complementary switching effect. Given that the migration of oxygen vacancies is a thermodynamic process, it is expected that the CRS should be influenced by temperature. Mainly, the voltage that is required to reach all four (4) resistance states will be reduced at higher temperatures so CRS effects will be more readily observable. To verify this hypothesis, the behavior of the device 10 at different temperatures was monitored. Initially, the device 10 showed typical bipolar RS in the voltage range of (-1.1, 1.3) V at low temperatures (up to 340 K) since region (3) cannot be accessed, as shown in Fig. 5(d). However, when the temperature was further increased to 380 K, CRS behavior similar those in Figs. 2(a)- 2(e) was observed even in the same voltage range, showing the impact of thermal effects since now the device 10 can access all four (4) states in the reduced voltage range. It will be appreciated that while certain implementations of the resistive memory device 10 have been discussed in detail in connection with the testing and study of device 10, the present disclosure is not meant to be limited to such implementations. Rather, it will be appreciated by those having ordinary skill in the art that device 10 may take the form of any number of implementations including, but not limited to, those described, and that the present disclosure is not limited to any particular implementation(s).

Thus, as described above, CRS can be achieved in single-stack tantalum oxide-based resistive memory devices or cells; though it will be appreciated that suitable metal oxides other than tantalum may be used, as can be determined by those skilled in the art through simple experimentation, and therefore, the present disclosure is not meant to be limited to any particular metal oxide(s). In any event, the observed complementary switching effects can be interpreted by the depletion of oxygen vacancies in one of the tantalum oxide layers 12, 14. Conventional bipolar switching requires symmetry breaking while CRS requires roughly symmetric device structure to access all four (4) possible device configurations. In view of the foregoing, tantalum oxide-based resistive memory devices with CRS provides a candidate for high-performance large-scale crossbar resistive memory.

It is to be understood that the foregoing description is of one or more preferred exemplary embodiments of the invention. The invention is not limited to the particular embodiment(s) disclosed herein, but rather is defined solely by the claims below. Furthermore, the statements contained in the foregoing description relate to particular embodiments and are not to be construed as limitations on the scope of the invention or on the definition of terms used in the claims, except where a term or phrase is expressly defined above. Various other embodiments and various changes and modifications to the disclosed embodiment(s) will become apparent to those skilled in the art. All such other embodiments, changes, and modifications are intended to come within the scope of the appended claims.

As used in this specification and claims, the terms "e.g.," "for example," "for instance," and "such as," and the verbs "comprising," "having," "including," and their other verb forms, when used in conjunction with a listing of one or more components or other items, are each to be construed as open-ended, meaning that the listing is not to be considered as excluding other, additional components or items. Other terms are to be construed using their broadest reasonable meaning unless they are used in a context that requires a different interpretation.

Claims

1. An article of manufacture comprising a single resistive memory device operable in a complementary resistive switching mode.

2. An article of manufacture as defined in claim 1 , wherein the single resistive memory device comprises:

a first metal oxide layer; and

a second metal oxide layer located underneath the first metal oxide layer;

wherein the first metal oxide layer has a different stoichiometry than the second metal oxide layer.

3. An article of manufacture as defined in claim 2, wherein the first metal oxide layer has an oxygen-rich stoichiometry relative to the stoichiometry of the second metal oxide layer.

4. An article of manufacture as defined in claim 2, wherein the first metal oxide layer comprises Ta₂0s_-X and the second metal oxide layer comprises TaOy.

5. An article of manufacture as defined in claim 2, wherein the first and second metal oxide layers are in direct contact with each other.

6. An article of manufacture as defined in claim 2, wherein the single resistive memory device further comprises upper and lower electrodes, with said first and second metal oxide layers being located between said electrodes.

7. A resistive memory device, comprising:

a first metal oxide layer; and

a second metal oxide layer located underneath the first metal oxide layer;

8. A resistive memory device as defined in claim 7, wherein the first metal oxide layer has an oxygen-rich stoiciometry relative to the stoichiometry of the second metal oxide layer.

9. A resistive memory device as defined in claim 7, wherein the first and second metal oxide layers each comprise different oxides of the same base metal.

10. A resistive memory device as defined in claim 9, wherein the base metal comprises tantalum.

11. A resistive memory device as defined in claim 10, wherein the first metal oxide layer comprises Ta₂0_5-X and the second metal oxide layer comprises TaCy

12. A resistive memory device as defined in claim 7, wherein the metal oxide layers are in direct contact with each other.

13. A resistive memory device as defined in claim 7, further comprising upper and lower electrodes, with said first and second metal oxide layers being located between said electrodes.

14. A resistive memory device as defined in claim 13, wherein said electrodes comprise palladium.

15. A crossbar memory array comprising an array of single memory devices each constructed as defined in claim 7, and including upper row electrodes and lower column electrodes connected to the array of single memory devices such that each of the single memory devices may be individually addressed using a pair of upper and lower electrodes.