TW201721865A - Nitride transistor structure enhances the electron mobility and the carrier concentration of a two-dimensional electron gas channel to achieve efficacy of increasing performance - Google Patents

Nitride transistor structure enhances the electron mobility and the carrier concentration of a two-dimensional electron gas channel to achieve efficacy of increasing performance Download PDF

Info

Publication number
TW201721865A
TW201721865A TW104141021A TW104141021A TW201721865A TW 201721865 A TW201721865 A TW 201721865A TW 104141021 A TW104141021 A TW 104141021A TW 104141021 A TW104141021 A TW 104141021A TW 201721865 A TW201721865 A TW 201721865A
Authority
TW
Taiwan
Prior art keywords
nitride
layer
gallium
crystal structure
aluminum
Prior art date
Application number
TW104141021A
Other languages
Chinese (zh)
Other versions
TWI572036B (en
Inventor
jia-qing Lin
guo-ren Zhang
zheng-chun Yang
Yu-Ting Xu
Wen-Hou Lan
Original Assignee
Nat Chung-Shan Inst Of Science And Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nat Chung-Shan Inst Of Science And Tech filed Critical Nat Chung-Shan Inst Of Science And Tech
Priority to TW104141021A priority Critical patent/TWI572036B/en
Application granted granted Critical
Publication of TWI572036B publication Critical patent/TWI572036B/en
Publication of TW201721865A publication Critical patent/TW201721865A/en

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

The invention is a nitride transistor structure and its method. The electron mobility and the carrier concentration of a two-dimensional electron gas channel can be further improved by inserting one layer or more layers of nitride intermediate layers growing at lower five-to-three ratio in the nitride transistor structure to achieve the effect of enhancing the performance of nitride transistors.

Description

氮化物電晶體結構 Nitride crystal structure

本發明係關於一種電晶體結構,特別是關於一種氮化物電晶體結構。 This invention relates to a crystal structure, and more particularly to a nitride crystal structure.

隨著科技的進步,對於高能電子元件的需求與日俱增,傳統矽基(Si-based)與砷化鎵(GaAs)元件由於其能隙較小已不符合高功率元件應用需求,必須使用寬能隙半導體材料,例如碳化矽(SiC)或氮化鎵(GaN)等;相較於碳化矽,氮化鎵系列材料可藉由材料能隙調變與組合來達到較高之通道電子遷移率與載子濃度,因此更適合作為高能電子元件需求應用,一般熟知之氮化物電晶體結構,尤其是高電子遷移率電晶體(High Electron Mobility Transistor,HEMT),其磊晶層結構由上至下為第一層氮化鋁鎵(AlGaN)層、第二層氮化鎵(GaN)層、第三層成核(Nucleation)層與第四層基板(Substrate),其中第一層氮化鋁鎵層亦可稱為阻障層,第二層氮化鎵層亦可稱為通道層,又其中第二層氮化鎵層可為無摻雜氮化鎵層與半絕緣氮化鎵層之組合;並且由於氮化物材料獨特的極化效應(Polarization Effect),包括自發極化(Spontaneous Polarization)與壓電極化(Piezoelectric Polarization),在沒有摻雜任何雜質 的情況下,極化效應可以使氮化鋁鎵/氮化鎵異質結構在在氮化鎵層靠近界面處自動感應形成二維電子氣(Two Dimensional Electron Gas,2DEG),在2DEG中的電子有較高之移動速度且其電子濃度大小與極化強弱有關。若要此磊晶結構具有元件操作功能,則必須在其上製作源極(Source)、汲極(Drain)與閘極(Gate)金屬電極,其中閘極電極介於源極與汲極電極之間,並且源極與汲極電極與半導體之間為歐姆接觸(Ohmic Contact),閘極電極與半導體之間為蕭特基接觸(Schottky Contact);元件操作方式為由源極提供一電流,該電流經由2DEG形成之通道由汲極電極輸出,並由閘極電極提供一電壓,藉由調節該電壓大小來控制通道電流開關特性與電流大小。 With the advancement of technology, the demand for high-energy electronic components is increasing day by day. Traditional Si-based and gallium arsenide (GaAs) components are not suitable for high-power component applications due to their small energy gap, and wide energy gaps must be used. Semiconductor materials, such as tantalum carbide (SiC) or gallium nitride (GaN); compared to tantalum carbide, gallium nitride series materials can achieve higher channel electron mobility and loading by material energy gap modulation and combination Sub-concentration, therefore more suitable as a high-energy electronic component demand application, generally known nitride crystal structure, especially High Electron Mobility Transistor (HEMT), the epitaxial layer structure from top to bottom is the first a layer of aluminum gallium nitride (AlGaN) layer, a second layer of gallium nitride (GaN) layer, a third layer of nucleation layer and a fourth layer of substrate, wherein the first layer of aluminum gallium nitride layer is also The second layer of gallium nitride layer may also be referred to as a channel layer, and the second layer of gallium nitride layer may be a combination of an undoped gallium nitride layer and a semi-insulating gallium nitride layer; Due to the unique polarization effect of the nitride material, the package Spontaneous polarization (Spontaneous Polarization) and piezoelectric polarization (Piezoelectric Polarization), without doping any impurities In the case of the polarization effect, the aluminum gallium nitride/gallium nitride heterostructure can be automatically induced to form two-dimensional electron gas (2DEG) at the interface near the gallium nitride layer, and the electrons in the 2DEG have The higher the moving speed and the magnitude of its electron concentration are related to the polarization. If the epitaxial structure has a component operation function, a source, a drain, and a gate metal electrode must be fabricated thereon, wherein the gate electrode is interposed between the source and the drain electrode. And the ohmic contact between the source and the drain electrode and the semiconductor, the Schottky contact between the gate electrode and the semiconductor; the operation of the device is to provide a current from the source, The current is output from the drain electrode via the 2DEG channel, and a voltage is supplied from the gate electrode. By adjusting the voltage, the channel current switching characteristics and current are controlled.

以上述之氮化物電晶體結構製作之元件一般為空乏型(Depletion Mode)元件,或稱為常通型(Normally On)元件,亦即在閘極電極施加電壓為0V時,2DEG通道間仍有電流產生,使源極與汲極之間為導通狀態;然而在高能電子應用上,尤其是高功率開關切換應用,增強型(Enchancement Mode)元件,或稱為常閉型(Normally Off)元件可提高元件與電路的安全性,增強型元件亦即在閘極電極施加電壓為0V時,2DEG通道間並無電流產生,必須在閘極電極施加正向偏壓才可使源極與汲極之間導通;理想狀態為在閘極電極正下方之通道區域並無2DEG形成,但閘極與源極之間,以及閘極與汲 極之間之通道區域仍有2DEG形成,為使元件導通須在閘極電極施加正向偏壓引發2DEG形成來導通元件,有諸多方式可達成此一增強型氮化物電晶體元件,例如可參照美國專利第US 7,728,356 B2號與US 7,851,825 B2號,藉由改變氮化物電晶體磊晶層結構與元件製程來達成。 The component fabricated by the above nitride crystal structure is generally a depletion mode component, or a normally-on component, that is, when the gate electrode is applied with a voltage of 0 V, there is still a gap between the 2DEG channels. Current is generated to bring the source and drain together; however, in high-energy applications, especially for high-power switching applications, the Enchancement Mode component, or Normally Off component, can be used. Improve the safety of components and circuits. When the applied voltage is 0V at the gate electrode, there is no current between the 2DEG channels. The forward bias must be applied to the gate electrode to make the source and drain. Inductive; ideally, there is no 2DEG formation in the channel region directly below the gate electrode, but between the gate and the source, and the gate and the gate There is still 2DEG formed in the channel region between the poles. In order to make the components turn on, a forward bias is applied to the gate electrodes to induce 2DEG formation to conduct the components. There are many ways to achieve this enhanced nitride transistor component, for example, refer to U.S. Patent Nos. 7,728,356 B2 and US 7,851,825 B2 are achieved by varying the structure and component process of the nitride transistor epitaxial layer.

上述之氮化物電晶體磊晶結構其晶體面向由基板朝上一般為鎵極性(Gallium Polar,Ga-polar),或稱為鎵面向(Gallium Face,Ga-face),相對於鎵面向的另一晶體面向為氮極性(Nitrogen Polar,N-polar),或稱為氮面向(Nitrogen Face,N-face),以晶體面向為氮面向製作之氮化物電晶體結構,其磊晶層結構由上至下為第一層氮化鎵(GaN)層、第二層氮化鋁鎵(AlGaN)層、第三層氮化鎵(GaN)層、第四層成核(Nucleation)層與第五層基板(Substrate),其中第一層氮化鎵層亦可稱為通道層,第二層氮化鋁鎵層亦可稱為阻障層;該氮面向氮化物電晶體結構同樣擁有極化效應,可在氮化鋁鎵/氮化鎵異質結構在在氮化鎵層靠近界面處自動感應形成二維電子氣(2DEG);有諸多方式可達成此一氮面向氮化物電晶體結構,例如可參照美國專利第US 8,878,249 B2號,藉由使用偏角度基板來達成。 The nitride crystal epitaxial structure described above has a crystal orientation such as Gallium Polar (Ga-polar), or Gallium Face (Ga-face), which is oriented upward from the substrate, and is opposite to the gallium surface. The crystal orientation is a Nitrogen Polar (N-polar), or Nitrogen Face (N-face), and the crystal orientation is a nitrogen-oriented nitride crystal structure, and the epitaxial layer structure is up to The first layer is a first layer of gallium nitride (GaN) layer, a second layer of aluminum gallium nitride (AlGaN) layer, a third layer of gallium nitride (GaN) layer, a fourth layer of nucleation layer and a fifth layer substrate (Substrate), wherein the first layer of gallium nitride layer may also be referred to as a channel layer, and the second layer of aluminum gallium nitride layer may also be referred to as a barrier layer; the nitrogen layer also has a polarization effect on the nitride crystal structure. The aluminum gallium nitride/gallium nitride heterostructure is automatically induced to form a two-dimensional electron gas (2DEG) near the interface of the gallium nitride layer; there are many ways to achieve this nitrogen-oriented nitride crystal structure, for example, refer to the US Patent No. US 8,878,249 B2 is achieved by using an off-angle substrate.

上述之氮化物電晶體結構,尤其是高電子遷移率電晶體,其電晶體元件特性優劣很大一部份取決於2DEG通道中的電子移動速度與電子濃度,因此若能改善2DEG通道特 性,例如提高2DEG電子遷移率或是電子濃度,均有助於改善電晶體元件效能。例如參照美國專利第US 6,849,882 B2號,其揭示一種在氮化鋁鎵阻障層與氮化鎵通道層之間插入一層氮化鋁(AlN)層,藉此來提高2DEG通道之電子遷移率;又例如參照美國專利第US 7,795,642 B2號,其揭示一種利用氮化鋁鎵/氮化鎵/氮化鋁鎵組合層來取代氮化鋁鎵阻障層,並調整氮化鋁鎵之鋁含量來提高2DEG通道之電子濃度;再例如參照美國專利第US 2006/0163594 A1號,其揭示一種利用氮化銦鎵層取代氮化鋁鎵阻障層,藉此來提高2DEG通道之電子濃度。 The nitride crystal structure described above, especially the high electron mobility transistor, has a large portion of the characteristics of the transistor component depending on the electron moving speed and electron concentration in the 2DEG channel, so if the 2DEG channel can be improved Properties, such as increased 2DEG electron mobility or electron concentration, all contribute to improved transistor component performance. For example, reference is made to US Pat. No. 6,849,882 B2, which discloses the disclosure of a layer of aluminum nitride (AlN) between an aluminum gallium nitride barrier layer and a gallium nitride channel layer, thereby increasing the electron mobility of the 2DEG channel; For example, reference is made to US Pat. No. 7,795,642 B2, which discloses the use of a gallium aluminum nitride/gallium nitride/aluminum gallium nitride combination layer in place of an aluminum gallium nitride barrier layer and adjusting the aluminum content of aluminum gallium nitride. Increasing the electron concentration of the 2DEG channel is disclosed in US Patent No. US 2006/0163594 A1, which discloses the use of an indium gallium nitride layer in place of an aluminum gallium nitride barrier layer, thereby increasing the electron concentration of the 2DEG channel.

職是之故,申請人乃進行試驗與研究,提出一種可提高2DEG通道電子遷移率與電子濃度之氮化物電晶體結構與製作方法,利用一層或多層較低五三比之氮化物中間層置於2DEG通道下方,其位置介於2DEG通道與基板之間,可提高2DEG通道電子遷移率與電子濃度,進而達到提升氮化物電晶體元件性能之功效。 For the sake of his position, the applicant conducted experiments and research, and proposed a nitride crystal structure and fabrication method that can improve the electron mobility and electron concentration of the 2DEG channel, using one or more layers of lower five or three ratio nitride intermediate layers. Below the 2DEG channel, the position is between the 2DEG channel and the substrate, which can improve the electron mobility and electron concentration of the 2DEG channel, thereby improving the performance of the nitride transistor component.

鑒於上述習知技術之缺點,本發明之主要目的在於提供一種氮化物電晶體結構,整合一成核層、一通道層、一中間層、一阻障層、及一緩衝層等半導體結構,以製備出提高二維電子氣通道之電子遷移率與載子濃度,而達到提升 氮化物電晶體性能之功效。 In view of the above disadvantages of the prior art, the main object of the present invention is to provide a nitride transistor structure, which integrates a semiconductor structure such as a nucleation layer, a channel layer, an intermediate layer, a barrier layer, and a buffer layer. Equivalent to increase the electron mobility and carrier concentration of the two-dimensional electron gas channel The efficacy of nitride transistor performance.

本發明提出利用一層或多層以較低五三比磊晶成長之氮化物中間層置於2DEG通道下方,其位置介於2DEG通道與基板之間,可提高2DEG通道電子遷移率與電子濃度,進而達到提升氮化物電晶體元件性能之功效。其中五三比為氮化物材料在進行磊晶成長過程中之一主要調整參數,其比例為磊晶成長時所通入之五族元素莫爾流量與三族元素莫爾流量之比例,本發明提出之較低五三比氮化物中間層置於2DEG通道下方,其位置介於2DEG通道與基板之間,亦即此低五三比氮化物中間層處於通道層之中,因此,此一氮化物中間層成長時之五三比必須小於通道層成長時之五三比,才可達到本發明所提出之提高2DEG通道電子遷移率與電子濃度之功效。 The invention proposes to use one or more layers of nitride intermediate layer which is epitaxially grown at a lower five-three ratio to be placed under the 2DEG channel, and the position is between the 2DEG channel and the substrate, which can improve the electron mobility and electron concentration of the 2DEG channel, and further Achieve the performance of improving the performance of nitride transistor components. The fifth to third ratio is one of the main adjustment parameters of the nitride material during the epitaxial growth process, and the ratio thereof is the ratio of the five-element element Moire flow rate and the three-element element Mohr flow rate which are introduced during the epitaxial growth, and the present invention The lower five-three-nitride intermediate layer is placed under the 2DEG channel, and the position is between the 2DEG channel and the substrate, that is, the lower five-three-nitride intermediate layer is in the channel layer, and therefore, the nitrogen The effect of increasing the electron mobility and electron concentration of the 2DEG channel proposed by the present invention can be achieved by the fact that the intermediate layer of the intermediate layer must be less than the ratio of the five to three ratios when the channel layer is grown.

為了達到上述目的,根據本發明所提出之一方案,提供一種鎵面向氮化物電晶體結構,包括:一基板;一成核層,該成核層形成於該基板之上;一通道層,係設置於該成核層之上,該通道層中具有至少一中間層;一阻障層,該阻障層係位該通道層之上;一源極、一汲極與一閘極三個金屬電極,係設置於該阻障層之上,該閘極位置處於該源極與該汲極之間,該源極與該汲極之金屬電極為歐姆接觸,與該閘極金屬電極為蕭特基接觸;其中形成該中間層之成長五三比較形成該通道層之成長五三比低。 In order to achieve the above object, according to one aspect of the present invention, a gallium-facing nitride transistor structure is provided, including: a substrate; a nucleation layer formed on the substrate; a channel layer, Provided on the nucleation layer, the channel layer has at least one intermediate layer; a barrier layer, the barrier layer is above the channel layer; a source, a drain and a gate three metals An electrode is disposed on the barrier layer, the gate is located between the source and the drain, the source is in ohmic contact with the metal electrode of the drain, and the gate metal electrode is Schott The base contact; wherein the growth of the intermediate layer is compared with the growth of the channel layer to form a growth ratio of five to three.

如上述中之鎵面向氮化物電晶體結構,其中該基板係為選自於藍寶石、碳化矽、矽、氮化鎵、氮化鋁或其他適合做為氮化物磊晶成長之基板材料;如上述中之鎵面向氮化物電晶體結構,其中該成核層可為氮化鎵、氮化鋁、氮化鋁鎵或其他可有效降低基板引發通道層應力與缺陷之氮化物材料;如上述中之鎵面向氮化物電晶體結構,其中該通道層可為氮化鎵或其他能隙小於阻障層材料能隙之氮化物材料;如上述中之鎵面向氮化物電晶體結構,其中該阻障層可為氮化鋁鎵、氮化銦鋁或其他能隙大於通道層材料能隙之氮化物材料;如上述中之鎵面向氮化物電晶體結構,其中該阻障層與通道層之界面必須形成二維電子氣;如上述中之鎵面向氮化物電晶體結構,其中該氮化物中間層可為氮化鎵、氮化鋁鎵或其他氮化物材料;如上述中之鎵面向氮化物電晶體結構,其中該氮化物中間層其成長之五三比必須小於通道層成長五三比;如上述中之鎵面向氮化物電晶體結構,其中該電晶體結構可為增強型或空乏型元件。 The gallium according to the above is oriented to a nitride crystal structure, wherein the substrate is selected from the group consisting of sapphire, tantalum carbide, niobium, gallium nitride, aluminum nitride or other substrate material suitable for epitaxial growth of nitride; The gallium is oriented to a nitride crystal structure, wherein the nucleation layer may be gallium nitride, aluminum nitride, aluminum gallium nitride or other nitride material which can effectively reduce the stress and defects of the channel induced channel layer; The gallium is oriented to the nitride transistor structure, wherein the channel layer may be a gallium nitride or other nitride material having a band gap smaller than that of the barrier layer material; and the gallium facing the nitride transistor structure as described above, wherein the barrier layer It may be aluminum gallium nitride, indium aluminum nitride or other nitride material having a larger energy gap than the material of the channel layer; as described above, the gallium faces the nitride crystal structure, wherein the interface between the barrier layer and the channel layer must be formed. a two-dimensional electron gas; wherein the gallium is oriented to a nitride transistor structure, wherein the nitride intermediate layer may be gallium nitride, aluminum gallium nitride or other nitride material; and the gallium facing nitride crystal structure as described above Wherein the nitride intermediate layer fifty-three its growth must be less than the ratio of the channel layer is grown fifty-three ratio; as described in the gallium nitride for transistor structure, wherein the transistor structure may be a depletion mode or enhancement mode device.

如上述中之鎵面向氮化物電晶體結構,其中該磊晶成長的方式為為選自於化學氣相磊晶法(Chemical Vapor Deposition,CVD)、有機金屬化學氣相磊晶法(Metal Organic Chemical Vapor Deposition,MOCVD)、分子束磊晶(Molecular Beam Epitaxy,MBE)、氫化物氣相磊晶(Hydride Vapor Phase Epitaxy,HVPE)、離子增強化學氣相磊晶法(Plasma Enhanced Chemical Vapor Deposition,PECVD)或其他適合成長氮化物材料之磊晶方法。 The gallium as described above faces the nitride crystal structure, wherein the epitaxial growth is selected from the group consisting of chemical vapor deposition (CVD) and organometallic chemical vapor deposition (Metal Organic Chemical). Vapor Deposition, MOCVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), Plasma Enhanced Chemical Vapor Deposition (Plasma Enhanced) Chemical Vapor Deposition (PECVD) or other epitaxial method suitable for growing nitride materials.

為了達到上述目的,根據本發明所提出之另一方案,提供一種氮面向氮化物電晶體結構,包括:一基板;一成核層,該成核層形成於該基板之上;一緩衝層,係位於該成核層之上,該緩衝層中具有至少一中間層;一阻障層,該阻障層係位於該緩衝層之上;一通道層,該通道層係位該阻障層之上;一源極、一汲極與一閘極三個金屬電極,係設置於該通道層之上,其中該閘極位置處於該源極與該汲極之間,該源極與該汲極之金屬電極為歐姆接觸,與該閘極金屬電極為蕭特基接觸;其中形成該中間層之成長五三比較形成該緩衝層之成長五三比低。 In order to achieve the above object, according to another aspect of the present invention, a nitrogen-facing nitride transistor structure is provided, comprising: a substrate; a nucleation layer formed on the substrate; a buffer layer, Is located on the nucleation layer, the buffer layer has at least one intermediate layer; a barrier layer, the barrier layer is located above the buffer layer; a channel layer, the channel layer is tied to the barrier layer a source electrode, a drain electrode and a gate three metal electrodes are disposed on the channel layer, wherein the gate position is between the source and the drain, the source and the drain The metal electrode is an ohmic contact, and the gate metal electrode is in Schottky contact; wherein the growth of the intermediate layer is compared to form a growth ratio of the buffer layer which is lower than the growth ratio of the buffer layer.

如上述中之氮面向氮化物電晶體結構,其中該基板係為選自於藍寶石、碳化矽、矽、氮化鎵、氮化鋁或其他適合做為氮化物磊晶成長之基板材料;如上述中之氮面向氮化物電晶體結構,其中該成核層可為氮化鎵、氮化鋁、氮化鋁鎵或其他可有效降低基板引發緩衝層應力與缺陷之氮化物材料;如上述中之氮面向氮化物電晶體結構,其中該緩衝層可為氮化鎵或其他氮化物材料;如上述中之氮面向氮化物電晶體結構,其中該阻障層可為氮化鋁鎵、氮化銦鋁或其他能隙大於通道層材料能隙之氮化物材料;如上述中之氮面向氮化物電晶體結構,其中該通道層可為氮化鎵或其他能隙小於 阻障層材料能隙之氮化物材料;如上述中之氮面向氮化物電晶體結構,其中該阻障層與通道層之界面必須形成二維電子氣;如上述中之氮面向氮化物電晶體結構,其中該氮化物中間層可為氮化鎵、氮化鋁鎵或其他氮化物材料;如上述中之氮面向氮化物電晶體結構,其中該氮化物中間層其成長之五三比必須小於緩衝層成長五三比;如上述中之氮面向氮化物電晶體結構,其中該電晶體結構可為增強型或空乏型元件。 The nitrogen as described above faces the nitride crystal structure, wherein the substrate is selected from the group consisting of sapphire, tantalum carbide, niobium, gallium nitride, aluminum nitride or other substrate material suitable for epitaxial growth of nitride; The nitrogen is oriented to a nitride crystal structure, wherein the nucleation layer may be gallium nitride, aluminum nitride, aluminum gallium nitride or other nitride material which can effectively reduce stress and defects of the buffer layer induced by the substrate; The nitrogen is oriented to a nitride crystal structure, wherein the buffer layer may be a gallium nitride or other nitride material; and the nitrogen as described above faces the nitride crystal structure, wherein the barrier layer may be aluminum gallium nitride or indium nitride Aluminum or other nitride material having a larger energy gap than the material of the channel layer; as described above, the nitrogen faces the nitride transistor structure, wherein the channel layer may be gallium nitride or other energy gap is less than a nitride material having a gap of a material of the barrier layer; as described above, the nitrogen faces the nitride crystal structure, wherein an interface between the barrier layer and the channel layer must form a two-dimensional electron gas; as described above, the nitrogen faces the nitride transistor a structure, wherein the nitride intermediate layer may be gallium nitride, aluminum gallium nitride or other nitride material; as described above, the nitrogen faces the nitride crystal structure, wherein the nitride intermediate layer has a growth ratio of less than five The buffer layer grows five to three ratios; as described above, the nitrogen faces the nitride transistor structure, wherein the transistor structure can be an enhancement or depletion element.

如上述中之氮面向氮化物電晶體結構,其中該磊晶成長的方式為為選自於化學氣相磊晶法(Chemical Vapor Deposition,CVD)、有機金屬化學氣相磊晶法(Metal Organic Chemical Vapor Deposition,MOCVD)、分子束磊晶(Molecular Beam Epitaxy,MBE)、氫化物氣相磊晶(Hydride Vapor Phase Epitaxy,HVPE)、離子增強化學氣相磊晶法(Plasma Enhanced Chemical Vapor Deposition,PECVD)或其他適合成長氮化物材料之磊晶方法。 The nitrogen as described above faces the nitride crystal structure, wherein the epitaxial growth is selected from the group consisting of chemical vapor deposition (CVD), and organometallic chemical vapor deposition (Metal Organic Chemical). Vapor Deposition (MOCVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), Plasma Enhanced Chemical Vapor Deposition (PECVD) Or other epitaxial methods suitable for growing nitride materials.

以上之概述與接下來的詳細說明及附圖,皆是為了能進一步說明本創作達到預定目的所採取的方式、手段及功效。而有關本創作的其他目的及優點,將在後續的說明及圖式中加以闡述。 The above summary and the following detailed description and drawings are intended to further illustrate the manner, means and effects of the present invention in achieving its intended purpose. Other purposes and advantages of this creation will be explained in the following description and drawings.

100、200‧‧‧基板 100, 200‧‧‧ substrate

101、201‧‧‧成核層 101, 201‧‧‧ nucleation layer

102、205‧‧‧通道層 102, 205‧‧‧ channel layer

103、203‧‧‧中間層 103, 203‧‧‧ middle layer

104、204‧‧‧阻障層 104, 204‧‧‧ barrier layer

105、206‧‧‧源極 105, 206‧‧‧ source

106、207‧‧‧汲極 106, 207‧‧ ‧ bungee

107、208‧‧‧閘極 107, 208‧‧‧ gate

112、215‧‧‧二維電子氣 112, 215‧‧‧Two-dimensional electronic gas

第一圖係為本發明一種鎵面向氮化物電晶體結構示意圖; 第二圖係為本發明一種氮面向氮化物電晶體結構示意圖;第三圖係為本發明一種具有低五三比中間層之氮化物電晶體電性量測結果;第四圖係為本發明一種具有低五三比中間層之氮化物電晶體電性量測結果。 The first figure is a schematic diagram of a gallium-facing nitride transistor structure of the present invention; The second figure is a schematic diagram of a nitrogen-oriented nitride crystal structure of the present invention; the third figure is a result of measuring the electrical conductivity of a nitride transistor having a low five-three ratio intermediate layer; the fourth figure is the invention A result of electrical measurement of a nitride transistor having a low five-three ratio intermediate layer.

以下係藉由特定的具體實例說明本創作之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地了解本創作之優點及功效。 The embodiments of the present invention are described by way of specific examples, and those skilled in the art can readily understand the advantages and effects of the present invention from the disclosure of the present disclosure.

請參閱第一圖所示,為本發明一種鎵面向氮化物電晶體結構示意圖。如圖一所示,本發明所提供一種鎵面向氮化物電晶體結構,包括有下列組成:一基板100,本實施例使用藍寶石作為磊晶基板,但亦可使用碳化矽、矽、氮化鎵、氮化鋁或其他適合做為氮化物磊晶成長之基板材料;其後於該基板100之上利用有機金屬化學氣相磊晶法磊晶成長成核層101,本實施例使用氮化鎵作為成核層101,但依磊晶方法的不同與選用不同基板,可選擇使用氮化鋁、氮化鋁鎵或其他可有效降低基板引發通道層102應力與缺陷之氮化物材料;其後於該成核層101之上成長通道層102,本實施例使用氮化鎵作為通道層102,但亦可使用其他能隙小於阻障層104 能隙之氮化物材料;依本發明特徵需說明通道層102成長五三比,於本實施例中,通道層102成長五三比為848,該五三比之值可依磊晶設備與程序不同而改變,不應限制本發明通道層102成長五三比於該五三比值;而在成長該通道層102過程中,本發明係將五三比降低至71~346之間係以成長一低五三比中間層103,本實施例使用氮化鎵與氮化鋁鎵作為低五三比中間層103,但亦可使用其他氮化物材料,該五三比之值可依磊晶設備與程序不同而改變,不應限制本發明低五三比中間層103成長五三比於該五三比範圍;並且在上述該低五三比中間層103製程後,接續提昇五三比值至848成長通道層102;其後於該通道層102之上成長阻障層104,本實施例使用氮化鋁鎵作為阻障層104,但亦可使用氮化銦鋁或其他能隙大於通道層102能隙之氮化物材料,並且該阻障層104與該通道層102之界面必須形成二維電子氣112。其後於阻障層104之上製作三個金屬電極,源極105、汲極106與閘極107完成電晶體元件製作,其中閘極107位置處於源極105與汲極106之間,源極與汲極之金屬電極為歐姆接觸,閘極金屬電極為蕭特基接觸;並可由閘極電極提供一電壓,藉由調節該電壓大小來控制通道電流開關特性與電流大小;其中該電晶體結構可為增強型或空乏型元件。 Please refer to the first figure for a schematic diagram of a gallium-facing nitride transistor structure of the present invention. As shown in FIG. 1 , the present invention provides a gallium-oriented nitride transistor structure, comprising the following composition: a substrate 100. In this embodiment, sapphire is used as an epitaxial substrate, but gallium carbide, germanium, gallium nitride can also be used. Aluminum nitride or other substrate material suitable for nitride epitaxial growth; thereafter epitaxial growth of the nucleation layer 101 on the substrate 100 by organometallic chemical vapor phase epitaxy, and gallium nitride is used in this embodiment. As the nucleation layer 101, depending on the epitaxial method and different substrates, aluminum nitride, aluminum gallium nitride or other nitride materials which can effectively reduce the stress and defects of the substrate-initiating channel layer 102 can be selected; The channel layer 102 is grown on the nucleation layer 101. In this embodiment, gallium nitride is used as the channel layer 102, but other energy gaps may be used instead of the barrier layer 104. According to the characteristics of the present invention, the channel layer 102 is grown at a ratio of five to three. In this embodiment, the channel layer 102 is grown at a ratio of 848 to 848. The value of the five-three ratio can be determined by the epitaxial device and the program. Differently, the channel layer 102 of the present invention should not be limited to a ratio of five to three ratios. In the process of growing the channel layer 102, the invention reduces the ratio of five to three to between 71 and 346 to grow one. The lower five or three ratio intermediate layer 103, this embodiment uses gallium nitride and aluminum gallium nitride as the lower five-three ratio intermediate layer 103, but other nitride materials may also be used, and the value of the five-three ratio may depend on the epitaxial device and The program is changed differently, and should not limit the low-fifth ratio intermediate layer 103 of the present invention to a ratio of five to three ratios; and after the low-three-three ratio intermediate layer 103 process described above, the fifth-to-three ratio is increased to 848. The channel layer 102; thereafter, the barrier layer 104 is grown on the channel layer 102. In this embodiment, aluminum gallium nitride is used as the barrier layer 104, but indium aluminum nitride or other energy gaps may be used to be larger than the channel layer 102. a nitride material of the gap, and the boundary between the barrier layer 104 and the channel layer 102 Dimensional electron gas 112 to be formed. Thereafter, three metal electrodes are formed on the barrier layer 104. The source 105, the drain 106 and the gate 107 complete the fabrication of the transistor device, wherein the gate 107 is located between the source 105 and the drain 106, the source. The metal electrode of the drain is in ohmic contact, the gate metal electrode is a Schottky contact; and a voltage is provided by the gate electrode, and the current switching characteristic and current magnitude are controlled by adjusting the voltage; wherein the transistor structure It can be an enhanced or depleted component.

請參閱第二圖所示,為本發明一種氮面向氮化物電晶體結構示意圖。如圖二所示,本發明所提供一種氮面向 氮化物電晶體結構,包括有下列組成:一基板200,本實施例使用藍寶石作為磊晶基板,但亦可使用碳化矽、矽、氮化鎵、氮化鋁或其他適合做為氮化物磊晶成長之基板材料;其後於該基板200之上利用有機金屬化學氣相磊晶法磊晶成長成核層201,本實施例使用氮化鎵作為成核層201,但依磊晶方法的不同與選用不同基板,可選擇使用氮化鋁、氮化鋁鎵或其他可有效降低基板引發緩衝層202應力與缺陷之氮化物材料;其後於該成核層201之上成長緩衝層202,本實施例使用氮化鎵作為緩衝層202,但亦可使用其他氮化物材料;依本發明特徵需說明緩衝層202成長五三比,於本實施例中,緩衝層202成長五三比為848,該五三比之值可依磊晶設備與程序不同而改變,不應限制本發明緩衝層202成長五三比於該五三比值;而在成長該緩衝層202過程中,本發明係將五三比降低至71~346之間係以成長一低五三比中間層203,本實施例使用氮化鎵與氮化鋁鎵作為低五三比中間層203,但亦可使用其他氮化物材料,該五三比之值可依磊晶設備與程序不同而改變,不應限制本發明低五三比中間層203成長五三比於該五三比範圍;並且在上述該低五三比中間層203製程後,接續提昇五三比值至848成長緩衝層202;其後於該緩衝層202之上成長阻障層204,本實施例使用氮化鋁鎵作為阻障層204,但亦可使用氮化銦鋁或其他能隙大於通道層205能隙之氮化物材料;其後於該阻障層204之上成長通道層205,本實 施例使用氮化鎵作為通道層205,但亦可使用其他能隙小於阻障層204能隙之氮化物材料;並且該通道層205與該阻障層204之界面必須形成二維電子氣215。其後於通道層205之上製作三個金屬電極,源極206、汲極207閘極208完成電晶體元件製作,其中閘極208位置處於源極206與汲極207之間,源極與汲極之金屬電極為歐姆接觸,閘極金屬電極為蕭特基接觸;並可由閘極電極提供一電壓,藉由調節該電壓大小來控制通道電流開關特性與電流大小;其中該電晶體結構可為增強型或空乏型元件。 Please refer to the second figure, which is a schematic diagram of a nitrogen-facing nitride transistor structure of the present invention. As shown in Figure 2, the present invention provides a nitrogen-oriented The nitride crystal structure includes the following composition: a substrate 200. This embodiment uses sapphire as the epitaxial substrate, but may also use tantalum carbide, tantalum, gallium nitride, aluminum nitride or the like as a nitride epitaxial. a grown substrate material; thereafter, epitaxial growth of the nucleation layer 201 is performed on the substrate 200 by an organometallic chemical vapor phase epitaxy method. In this embodiment, gallium nitride is used as the nucleation layer 201, but the epitaxial method is different. Alternatively, a different substrate may be used, and aluminum nitride, aluminum gallium nitride or other nitride material which can effectively reduce the stress and defects of the substrate-initiated buffer layer 202 may be selected; thereafter, the buffer layer 202 is grown on the nucleation layer 201, The embodiment uses gallium nitride as the buffer layer 202, but other nitride materials may be used. According to the features of the present invention, the buffer layer 202 is grown by a ratio of five to three. In this embodiment, the buffer layer 202 is grown at a ratio of 848 to 848. The value of the five-three ratio may vary according to the epitaxial device and the program, and the buffer layer 202 of the present invention should not be limited to a ratio of five to three. In the process of growing the buffer layer 202, the present invention will be five. The ratio is reduced to 7 Between 1 and 346, the intermediate layer 203 is grown by a lower five to three ratio. In this embodiment, gallium nitride and aluminum gallium nitride are used as the lower five to three intermediate layer 203, but other nitride materials may also be used. The value can be changed according to the epitaxial device and the program, and should not limit the low five to three intermediate layer 203 of the present invention to grow five to three ratios; and after the low five or three intermediate layer 203 process described above Then, the fifth to third ratio is raised to the 848 growth buffer layer 202; thereafter, the barrier layer 204 is grown on the buffer layer 202. In this embodiment, aluminum gallium nitride is used as the barrier layer 204, but indium aluminum nitride can also be used. Or other nitride material having a larger energy gap than the channel layer 205; and subsequently growing the channel layer 205 over the barrier layer 204. The embodiment uses gallium nitride as the channel layer 205, but other nitride materials having a smaller energy gap than the barrier layer 204 can be used; and the interface between the channel layer 205 and the barrier layer 204 must form a two-dimensional electron gas 215. . Thereafter, three metal electrodes are fabricated on the channel layer 205, and the source 206 and the drain 207 gate 208 complete the fabrication of the transistor device. The gate 208 is located between the source 206 and the drain 207, and the source and the gate are The metal electrode of the pole is an ohmic contact, and the gate metal electrode is a Schottky contact; and a voltage is provided by the gate electrode, and the current switching characteristic and current magnitude of the channel are controlled by adjusting the voltage; wherein the transistor structure can be Enhanced or depleted components.

請參閱第三圖所示,為本發明一種具有低五三比中間層之氮化物電晶體電性量測結果。如圖三所示,包含室溫(Room Temperature,RT)與低溫80K之2DEG電子遷移率(Mobility)與片載子濃度(Sheet Concentration)圖,該圖中比較一般氮化物電晶體結構與具有低五三比氮化物中間層之氮化物電晶體結構電性量測結果,其中低五三比氮化物中間層之五三比分別為177、141與71;由圖中可發現,隨著低五三比氮化物中間層五三比的降低,室溫與低溫電子遷移率有顯著的提高,室溫電子遷移率可由1481cm2/Vs提高至1815cm2/Vs;低溫80K電子遷移率更是由6349cm2/Vs大幅提高至13420cm2/Vs,由於低溫量測可使試片不受外在環境熱擾動影響,更能顯示出結構改善後之成果;然而與電子遷移率相比,片載子濃度則由1.4x1013cm-2降低至1.2x1013cm-2,但仍保持在1013 cm-2以上,仍足以滿足氮化鎵電晶體元件需求。 Please refer to the third figure, which is a result of measuring the electrical conductivity of a nitride transistor having a low five-three ratio intermediate layer. As shown in Figure 3, 2DEG electron mobility (Mobility) and sheet concentration (Sheet Concentration) graphs including room temperature (RT) and low temperature 80K, which compares the general nitride crystal structure with low The electrical measurement results of the nitride crystal structure of the five-three-nitride intermediate layer, wherein the ratio of the five to three ratios of the lower five to three nitride intermediate layers are 177, 141 and 71 respectively; as can be seen from the figure, with the lower five three intermediate reduction ratio of the nitride layer fifty-three ratio, and low electron mobility at room temperature have a significant increase, the electron mobility at room temperature may be 1481cm 2 / Vs was increased to 1815cm 2 / Vs; cryogenic 80K electron mobility is more 6349cm 2 /Vs is greatly increased to 13420cm 2 /Vs. Because the low temperature measurement can make the test piece not affected by the external environmental thermal disturbance, it can show the result of structural improvement; however, compared with the electron mobility, the carrier concentration From 1.4x10 13 cm -2 to 1.2x10 13 cm -2 , but still above 10 13 cm -2 , still enough to meet the needs of gallium nitride transistor components.

請參閱第四圖所示,為本發明一種具有低五三比中間層之氮化物電晶體電性量測結果。如圖四所示,現請再參考第4圖,其顯示為本發明提出之具有低五三比氮化物中間層之氮化物電晶體結構電性量測結果,包含室溫(Room Temperature,RT)與低溫80K之2DEG電子遷移率(Mobility)與片載子濃度(Sheet Concentration)圖,該圖中比較一般氮化物電晶體結構與具有低五三比氮化物中間層之氮化物電晶體結構電性量測結果,其中低五三比氮化物中間層分別為氮化鎵與氮化鋁鎵,其五三比分別為71與346;由圖中可發現,當使用氮化鋁鎵作為低五三比氮化物中間層時,室溫電子遷移率可由1481cm2/Vs提高至1800cm2/Vs;低溫80K電子遷移率更是由6349cm2/Vs大幅提高至14800cm2/Vs,同樣顯示出結構改善後之成果;並且在片載子濃度量測結果,使用氮化鋁鎵作為低五三比氮化物中間層可使片載子濃度由1.4x1013cm-2提高至2.1x1013cm-2,顯示出使用氮化鋁鎵作為低五三比氮化物中間層可同時提升片載子濃度。 Please refer to the fourth figure, which is a result of measuring the electrical conductivity of a nitride transistor having a low five-three ratio intermediate layer. As shown in FIG. 4, please refer to FIG. 4 again, which shows the electrical measurement results of the nitride crystal structure with the low five-three ratio nitride intermediate layer proposed by the present invention, including room temperature (Room Temperature, RT). And 2eG electron mobility (Mobility) and sheet concentration (Sheet Concentration) map of low temperature 80K, which compares the general nitride crystal structure with the nitride crystal structure with a low five-three ratio nitride intermediate layer The measurement results, wherein the lower five to three nitride intermediate layers are respectively gallium nitride and aluminum gallium nitride, and the five to three ratios are 71 and 346 respectively; as can be seen from the figure, when using aluminum gallium nitride as the lower five when more than three nitride intermediate layer, the electron mobility at room temperature may be 1481cm 2 / Vs was increased to 1800cm 2 / Vs; cryogenic 80K electron mobility is increased from 6349cm 2 / Vs sharply to 14800cm 2 / Vs, also shows improved structure The result of the latter; and in the measurement of the concentration of the carrier, the use of aluminum gallium nitride as the lower five-three-nitride intermediate layer can increase the carrier concentration from 1.4x10 13 cm -2 to 2.1x10 13 cm -2 , Shows the use of aluminum gallium nitride as the middle of the lower five to three ratio nitride The layer can simultaneously increase the carrier concentration.

上述之實施例僅為例示性說明本創作之特點及功效,非用以限制本創作之實質技術內容的範圍。任何熟悉此技藝之人士均可在不違背創作之精神及範疇下,對上述實施例進行修飾與變化。因此,本創作之權利保護範圍,應如後述之申請專利範圍所列。 The above-described embodiments are merely illustrative of the features and functions of the present invention and are not intended to limit the scope of the technical content of the present invention. Any person skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the creation. Therefore, the scope of protection of this creation should be as listed in the scope of the patent application described later.

100‧‧‧基板 100‧‧‧Substrate

101‧‧‧成核層 101‧‧‧ nucleation layer

102‧‧‧通道層 102‧‧‧Channel layer

103‧‧‧中間層 103‧‧‧Intermediate

104‧‧‧阻障層 104‧‧‧Barrier layer

105‧‧‧源極 105‧‧‧ source

106‧‧‧汲極 106‧‧‧汲polar

107‧‧‧閘極 107‧‧‧ gate

112‧‧‧二維電子氣 112‧‧‧Two-dimensional electronic gas

Claims (17)

一種鎵面向氮化物電晶體結構,包括:一基板;一成核層,該成核層形成於該基板之上;一通道層,係設置於該成核層之上,該通道層中具有至少一中間層;一阻障層,該阻障層係位該通道層之上;一源極、一汲極與一閘極三個金屬電極,係置於該阻障層之上,該閘極位置處於該源極與該汲極之間,該源極與該汲極之金屬電極為歐姆接觸,與該閘極金屬電極為蕭特基接觸;其中形成該中間層之成長五三比較形成該通道層之成長五三比低。 A gallium-facing nitride transistor structure includes: a substrate; a nucleation layer formed on the substrate; a channel layer disposed on the nucleation layer, the channel layer having at least An intermediate layer; a barrier layer, the barrier layer is above the channel layer; a source, a drain and a gate three metal electrodes are placed on the barrier layer, the gate The position is between the source and the drain, the source is in ohmic contact with the metal electrode of the drain, and the gate metal electrode is in Schottky contact; wherein the growth of the intermediate layer is formed to form the The growth of the channel layer is lower than the ratio of five to three. 如申請專利範圍第1項所述之鎵面向氮化物電晶體結構,其中,該基板係選自藍寶石、碳化矽、矽、氮化鎵、氮化鋁其中之一。 The gallium according to claim 1 is a nitride-oriented crystal structure, wherein the substrate is selected from one of sapphire, tantalum carbide, niobium, gallium nitride, and aluminum nitride. 如申請專利範圍第1項所述之鎵面向氮化物電晶體結構,其中,該成核層、該通道層、該中間層、該阻障層係包含氮化物。 The gallium-facing nitride transistor structure according to claim 1, wherein the nucleation layer, the channel layer, the intermediate layer, and the barrier layer comprise a nitride. 如申請專利範圍第3項所述之鎵面向氮化物電晶體結構,其中,該成核層係為氮化鎵、氮化鋁、氮化鋁鎵其中之一。 The gallium according to claim 3 is a nitride-oriented crystal structure, wherein the nucleation layer is one of gallium nitride, aluminum nitride, and aluminum gallium nitride. 如申請專利範圍第3項所述之鎵面向氮化物電晶體結構,其中,該通道層係為氮化鎵。 A gallium-oriented nitride transistor structure as described in claim 3, wherein the channel layer is gallium nitride. 如申請專利範圍第3項所述之鎵面向氮化物電晶體結構,其中,該阻障層係為氮化鋁鎵、氮化銦鋁其中之一。 The gallium according to claim 3 is a nitride-oriented crystal structure, wherein the barrier layer is one of aluminum gallium nitride and indium aluminum nitride. 如申請專利範圍第3項所述之鎵面向氮化物電晶體結構,其中,該中間層係為氮化鎵、氮化鋁鎵其中之一。 The gallium according to claim 3 is a nitride-oriented crystal structure, wherein the intermediate layer is one of gallium nitride and aluminum gallium nitride. 如申請專利範圍第1項所述之鎵面向氮化物電晶體結構,其中,該阻障層與該通道層之界面係形成二維電子氣。 The gallium-oriented nitride transistor structure according to claim 1, wherein the interface between the barrier layer and the channel layer forms a two-dimensional electron gas. 一種氮面向氮化物電晶體結構,係包括:一基板;一成核層,該成核層形成於該基板之上;一緩衝層,係位於該成核層之上,該緩衝層中具有至少一中間層;一阻障層,該阻障層係位於該緩衝層之上;一通道層,該通道層係位該阻障層之上;一源極、一汲極與一閘極三個金屬電極,係設置於該通道層之上,其中該閘極位置處於該源極與該汲極之間,該源極與該汲極之金屬電極為歐姆接觸,與該閘極金屬電極為蕭特基接觸;其中形成該中間層之成長五三比較形成該緩衝層之成長五三比低。 A nitrogen-facing nitride transistor structure includes: a substrate; a nucleation layer formed on the substrate; a buffer layer disposed on the nucleation layer, the buffer layer having at least An intermediate layer; a barrier layer, the barrier layer is located above the buffer layer; a channel layer, the channel layer is above the barrier layer; a source, a drain and a gate a metal electrode is disposed on the channel layer, wherein the gate position is between the source and the drain, the source is in ohmic contact with the metal electrode of the drain, and the gate metal electrode is Xiao The base contact; wherein the growth of the intermediate layer is compared with the growth of the buffer layer to form a growth ratio of five to three. 如申請專利範圍第9項所述之氮面向氮化物電晶體結構,其中,該基板係選自藍寶石、碳化矽、矽、氮化鎵、氮化鋁其中之一。 The nitrogen according to claim 9 is a nitride-oriented crystal structure, wherein the substrate is selected from one of sapphire, tantalum carbide, niobium, gallium nitride, and aluminum nitride. 如申請專利範圍第9項所述之氮面向氮化物電晶體結構,其中,該成核層、該緩衝層、該通道層、該中間層、該阻障層係包含氮化物。 The nitrogen according to claim 9 is for a nitride crystal structure, wherein the nucleation layer, the buffer layer, the channel layer, the intermediate layer, and the barrier layer comprise a nitride. 如申請專利範圍11項所述之氮面向氮化物電晶體結構,其中,該成核層係為氮化鎵、氮化鋁、氮化鋁鎵其中之一。 The nitrogen according to claim 11 is a nitride-oriented crystal structure, wherein the nucleation layer is one of gallium nitride, aluminum nitride, and aluminum gallium nitride. 如申請專利範圍11項所述之氮面向氮化物電晶體結構,其中,該緩衝層係為氮化鎵。 The nitrogen according to claim 11 is a nitride-oriented crystal structure, wherein the buffer layer is gallium nitride. 如申請專利範圍第11項所述之氮面向氮化物電晶體結構,其中,該阻障層係為氮化鋁鎵、氮化銦鋁其中之一。 The nitrogen according to claim 11 is a nitride-oriented crystal structure, wherein the barrier layer is one of aluminum gallium nitride and indium aluminum nitride. 如申請專利範圍第11項所述之氮面向氮化物電晶體結構,其中,該通道層係為氮化鎵。 The nitrogen according to claim 11 is a nitride-oriented crystal structure, wherein the channel layer is gallium nitride. 如申請專利範圍第11項所述之氮面向氮化物電晶體結構,其中,該中間層係為氮化鎵、氮化鋁鎵其中之一。 The nitrogen according to claim 11 is a nitride-oriented crystal structure, wherein the intermediate layer is one of gallium nitride and aluminum gallium nitride. 如申請專利範圍第11項所述之氮面向氮化物電晶體結構,其中,該阻障層與該通道層之界面必須形成二維電子氣。 The nitrogen according to claim 11 is a nitride-oriented crystal structure, wherein an interface between the barrier layer and the channel layer must form a two-dimensional electron gas.
TW104141021A 2015-12-08 2015-12-08 Nitride crystal structure TWI572036B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW104141021A TWI572036B (en) 2015-12-08 2015-12-08 Nitride crystal structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW104141021A TWI572036B (en) 2015-12-08 2015-12-08 Nitride crystal structure

Publications (2)

Publication Number Publication Date
TWI572036B TWI572036B (en) 2017-02-21
TW201721865A true TW201721865A (en) 2017-06-16

Family

ID=58608349

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104141021A TWI572036B (en) 2015-12-08 2015-12-08 Nitride crystal structure

Country Status (1)

Country Link
TW (1) TWI572036B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109309090A (en) * 2017-07-28 2019-02-05 新唐科技股份有限公司 Semiconductor device and method for manufacturing the same
US12034053B2 (en) 2020-05-08 2024-07-09 National Research Council Of Canada Ohmic contacts with direct access pathways to two-dimensional electron sheets

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI716230B (en) * 2019-12-20 2021-01-11 國家中山科學研究院 Aluminum nitride transistor structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5891650B2 (en) * 2011-08-18 2016-03-23 富士通株式会社 Compound semiconductor device and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109309090A (en) * 2017-07-28 2019-02-05 新唐科技股份有限公司 Semiconductor device and method for manufacturing the same
TWI660465B (en) * 2017-07-28 2019-05-21 新唐科技股份有限公司 Semiconductor device and manufacturing method thereof
US10411098B2 (en) 2017-07-28 2019-09-10 Nuvoton Technology Corporation Semiconductor device and manufacturing method thereof
US12034053B2 (en) 2020-05-08 2024-07-09 National Research Council Of Canada Ohmic contacts with direct access pathways to two-dimensional electron sheets

Also Published As

Publication number Publication date
TWI572036B (en) 2017-02-21

Similar Documents

Publication Publication Date Title
US8710511B2 (en) AIN buffer N-polar GaN HEMT profile
JP5580602B2 (en) Cascode circuit using depletion mode GaN-based FET
US8541816B2 (en) III nitride electronic device and III nitride semiconductor epitaxial substrate
JP2011166067A (en) Nitride semiconductor device
CN111406306B (en) Method for manufacturing semiconductor device and semiconductor device
US20130256681A1 (en) Group iii nitride-based high electron mobility transistor
US20150115327A1 (en) Group III-V Device Including a Buffer Termination Body
US11424321B2 (en) Semiconductor structure and preparation method thereof
US11545566B2 (en) Gallium nitride high electron mobility transistors (HEMTs) having reduced current collapse and power added efficiency enhancement
US9620362B2 (en) Seed layer structure for growth of III-V materials on silicon
JP2016207748A (en) Method of manufacturing semiconductor device, and semiconductor device
JP2008277655A (en) Semiconductor epitaxial wafer, and field-effect transistor
JP2015527749A (en) GANGEMT characteristics of N pole of INGAN channel
JP6305137B2 (en) Nitride semiconductor laminate and semiconductor device
US10332975B2 (en) Epitaxial substrate for semiconductor device and method for manufacturing same
JP2013069772A (en) Semiconductor device and semiconductor device manufacturing method
JP2017168627A (en) High electron mobility transistor and manufacturing method of the same
Wang et al. Influence of AlGaN back barrier layer thickness on the dynamic ron characteristics of AlGaN/GaN HEMTs
TWI572036B (en) Nitride crystal structure
WO2018098952A1 (en) Gan-based epitaxial structure, semiconductor device and formation method therefor
JP2007123824A (en) Electronic device using group-iii nitride based compound semiconductor
JP6815278B2 (en) Nitride semiconductor laminate, semiconductor device, nitride semiconductor laminate manufacturing method and semiconductor device manufacturing method
US20180366572A1 (en) Nitride semiconductor epitaxial substrate and semiconductor device
TW201707052A (en) Semiconductor device and manufacturing method thereof
JP2010045416A (en) Group iii nitride electronic device