TW201714299A - 鰭狀場效電晶體及其製造方法 - Google Patents

鰭狀場效電晶體及其製造方法 Download PDF

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TW201714299A
TW201714299A TW104132649A TW104132649A TW201714299A TW 201714299 A TW201714299 A TW 201714299A TW 104132649 A TW104132649 A TW 104132649A TW 104132649 A TW104132649 A TW 104132649A TW 201714299 A TW201714299 A TW 201714299A
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layer
field effect
effect transistor
fin
breakdown
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TWI677098B (zh
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江懷慈
林勝豪
李皞明
楊玉如
黃世賢
陳建宏
吳俊元
蔡成宗
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聯華電子股份有限公司
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Priority to US14/936,370 priority patent/US10068963B2/en
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Abstract

提供一種鰭狀場效電晶體，其包括基底、至少一鰭片以及至少一閘極。部分所述至少一鰭片嵌入於基底中，且鰭片包括由下而上的晶種層、應力舒緩層以及通道層。至少一閘極橫跨所述至少一鰭片。另提供一種鰭狀場效電晶體的製造方法。

Description

鰭狀場效電晶體及其製造方法
本發明是有關於一種半導體結構及其製造方法，且特別是有關於一種鰭狀場效電晶體及其製造方法。
由於積體電路的尺寸減小，對於具有高驅動電流及小尺寸的電晶體的需求增加，因而研發出鰭狀場效電晶體（fin-type field effect transistor；FinFET）。鰭狀場效電晶體的通道形成於鰭片的側壁和頂表面上，使得鰭狀場效電晶體具有較大的通道寬度，進而可以增加電晶體的驅動電流。然而，習知的矽鍺鰭片成長在矽基底上常有晶格失配（mismatch）或錯位（dislocation）的問題，使得鰭狀場效電晶體的效能降低。
有鑒於此，本發明提供一種鰭狀場效電晶體及其製造方法，可解決習知鰭片之晶格失配或錯位的問題。
本發明提供一種鰭狀場效電晶體，其包括基底、至少一鰭片以及至少一閘極。部分所述至少一鰭片嵌入於基底中，且鰭片包括由下而上的晶種層、應力舒緩層以及通道層。至少一閘極橫跨所述至少一鰭片。
在本發明的一實施例中，上述鰭狀場效電晶體更包括抗擊穿層，其配置於應力舒緩層與通道層之間。
在本發明的一實施例中，上述通道層的鍺濃度等於抗擊穿層的鍺濃度，抗擊穿層的鍺濃度大於應力舒緩層的鍺濃度，且應力舒緩層的鍺濃度大於晶種層的鍺濃度。
在本發明的一實施例中，上述應力舒緩層具有漸變的應力分布，且應力舒緩層的鍺濃度自晶種層往抗擊穿層逐漸升高。
在本發明的一實施例中，上述抗擊穿層的摻質濃度大於應力舒緩層或通道層的摻質濃度。
在本發明的一實施例中，上述鰭狀場效電晶體更包括環繞所述至少一鰭片的下部的絕緣層，且絕緣層的表面高於抗擊穿層與通道層的界面。
在本發明的一實施例中，上述通道層的鍺濃度的範圍為約20%至100%。
在本發明的一實施例中，上述晶種層以及部分應力舒緩層配置於基底中。
在本發明的一實施例中，上述基底與晶種層具有實質上相同的晶格常數，且擊穿層與通道層具有實質上相同的晶格常數。
本發明另提供一種鰭狀場效電晶體的製造方法。提供基底，所述基底上已形成有絕緣層，所述絕緣層中已形成有至少一溝渠，且至少一溝渠延伸至部分基底中。於至少一溝渠中依序形成晶種層、應力舒緩層以及通道層。移除部分絕緣層，以裸露出部分通道層。形成至少一閘極，所述至少一閘極橫跨通道層。
在本發明的一實施例中，上述方法更包括於應力舒緩層與通道層之間形成抗擊穿層。
在本發明的一實施例中，上述通道層的鍺濃度等於抗擊穿層的鍺濃度，抗擊穿層的鍺濃度大於應力舒緩層的鍺濃度，且應力舒緩層的鍺濃度大於晶種層的鍺濃度。
在本發明的一實施例中，上述應力舒緩層具有漸變的應力分布，且應力舒緩層的鍺濃度自晶種層往抗擊穿層逐漸升高。
在本發明的一實施例中，形成上述晶種層、應力舒緩層、抗擊穿層以及通道層的方法各自包括進行磊晶成長製程。
在本發明的一實施例中，上述抗擊穿層的摻質濃度大於應力舒緩層或通道層的摻質濃度。
在本發明的一實施例中，上述抗擊穿層的摻質包括砷、磷或硼。
在本發明的一實施例中，移除部分上述絕緣層的步驟之後，剩餘的絕緣層的表面高於抗擊穿層與通道層的界面。
在本發明的一實施例中，形成上述至少一溝渠的方法包括：提供具有至少一虛設鰭片（dummy fin）的基底，絕緣層環繞所述至少一虛設鰭片；以及進行蝕刻製程，以移除所述至少一虛設鰭片以及部分基底。
在本發明的一實施例中，上述通道層的鍺濃度的範圍為約20%至100%。
在本發明的一實施例中，上述基底與晶種層具有實質上相同的晶格常數，且擊穿層與通道層具有實質上相同的晶格常數。
基於上述，在本發明之鰭狀場效電晶體中，藉由配置具有（由下而上）晶種層、應力舒緩層、抗擊穿層以及通道層的鰭片，不但可解決習知鰭片之晶格失配問題，且可避免擊穿現象，故可有效提升元件的效能，增加競爭力。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1E為依照本發明一實施例所繪示的一種鰭狀場效電晶體的製造方法的立體示意圖。圖2為圖1E之沿I-I線的剖面示意圖。
請參照圖1A，提供具有至少一虛設鰭片（dummy fin）101的基底100。基底100可為半導體基底，且虛設鰭片101可為半導體鰭片或介電鰭片。在一實施例中，基底100與虛設鰭片101的材料相同。舉例來說，虛設鰭片101與基底100的材料均為矽，但本發明並不以此為限。在另一實施例中，虛設鰭片101與基底100的材料不同。舉例來說，基底100的材料為矽，而虛設鰭片101的材料為介電材料。在一實施例中，形成具有上述虛設鰭片101的基底100的方法包括進行側壁圖像轉移（sidewall image transfer；SIT）技術。
此外，基底100上已形成有環繞至少一虛設鰭片101的絕緣層103。形成絕緣層103的方法包括先於基底100上形成絕緣材料層（未繪示），且絕緣材料層覆蓋虛設鰭片101。之後，以虛設鰭片101為研磨中止層，進行化學氣相研磨（chemical mechanical polishing；CMP）製程。在一實施例中，研磨製程之後，虛設鰭片101的頂部與絕緣層103的頂表面實質上齊平。
請參照圖1B，移除至少一虛設鰭片101以及部分基底100，以於絕緣層103中形成至少一溝渠105，且溝渠105延伸至部分基底100中。在一實施例中，虛設鰭片101以及絕緣層103具有不同的蝕刻速率，且上述移除步驟包括進行蝕刻製程。在一實施例中，先進行乾式蝕刻使溝渠的深度接近絕緣層103與基底100的界面，再進行濕式蝕刻使溝渠的底部延伸至基底100中。在一實施例中，利用晶面{111}與晶面{100}的蝕刻速率不同的特性，可使溝渠105具有V形底部，如圖1B所示。在另一實施例中，可以僅進行乾式蝕刻，例如多步驟乾式蝕刻，使溝渠105具有大致上平坦的底部。之後，可進行清洗製程，以移除溝渠105表面的蝕刻殘留物。
請參照圖1C，於至少一溝渠105中形成至少一鰭片（或稱主動鰭片）110。鰭片110包括（由下而上）依序形成的晶種層102、應力舒緩層104、抗擊穿層106以及通道層108。在一實施例中，鰭片110沿第一方向延伸。
晶種層102可修復被蝕刻製程破壞的基底表面，減少晶格錯位的現象。在一實施例中，晶種層102與基底100具有實質上相同的晶格常數。舉例來說，晶種層102與基底100的材料均為矽。在一實施例中，晶種層102的摻質濃度可為零或接近零。
應力舒緩層104可舒緩鰭片110的應力分布。在一實施例中，應力舒緩層104具有漸變的應力分布。應力舒緩層104也可稱為應力漸變緩衝層（graded stress buffer layer）。在一實施例中，應力舒緩層104的應力原子濃度（例如鍺濃度）自晶種層102往抗擊穿層106逐漸升高。更具體地說，晶種層102的鍺濃度可為零或接近零，而應力舒緩層104的鍺濃度（由下而上）由零或接近零逐漸提高至大致上等於抗擊穿層106的鍺濃度。換言之，應力舒緩層104的平均鍺濃度介於晶種層102的鍺濃度與抗擊穿層106的鍺濃度之間。在一實施例中，應力舒緩層104的摻質濃度可為零或接近零。在另一實施例中，應力舒緩層104具有低摻質濃度，例如小於約1×1016 cm-3 。
通道層108的鍺濃度的範圍為20%至100%。在一實施例中，通道層108的材料為矽鍺。在另一實施例中，通道層108的材料為鍺。在一實施例中，通道層108的摻質濃度可為零或接近零。在另一實施例中，通道層108具有低摻質濃度，例如小於約1×1016 cm-3 。
抗擊穿層106可避免源極/汲極118之間發生擊穿效應。抗擊穿層106的導電類型與源極/汲極118的導電類型相反，但與通道層108的導電類型相同。抗擊穿層106的摻質包括N型摻質或P型摻質。在一實施例中，抗擊穿層106的摻質包括砷、磷或硼。此外，抗擊穿層106的摻質濃度大於應力舒緩層104或通道層108的摻質濃度。在一實施例中，抗擊穿層106的摻質濃度的範圍為約1×1018 cm-3 至1×1019 cm-3 之間，而應力舒緩層104或通道層108的摻質濃度小於約1×1016 cm-3 。在一實施例中，抗擊穿層106與通道層108具有實質上相同的晶格常數。舉例來說，抗擊穿層106與通道層108的材料均為矽鍺或鍺。
此外，形成晶種層102、應力舒緩層104、抗擊穿層106以及通道層108的方法包括各自進行磊晶成長製程，例如化學氣相磊晶、分子束磊晶（molecular beam epitaxy；MBE）、液相磊晶（liquid phase epitaxy；LPE）、固相磊晶（solid phase epitaxy；SPE）或適合的磊晶技術。在一實施例中，視情況，可於磊晶成長製程的期間進行原位（in-situ）摻雜。在一實施例中，由於通道層108為最上層，可能會成長為於超出溝渠105，故可選擇性地進行化學機械研磨製程，以移除掉溝渠105外的膜層。
請參照圖1D，移除部分絕緣層103，以裸露出部分通道層108。在一實施例中，移除部分絕緣層103的步驟之後，剩餘的絕緣層103的表面高於抗擊穿層106與通道層108的界面107。在另一實施例中，剩餘的絕緣層103的表面也可實質上等於抗擊穿層106與通道層108的界面107。此外，移除部分絕緣層103的方法包括進行回蝕刻製程。
請參照圖1E以及圖2，形成至少一閘極114以及源極/汲極區118。至少一閘極114橫跨通道層108。閘極114的材料包括含矽材料或金屬。含矽材料包括多晶矽、非晶矽或其組合。金屬包括功函數金屬（例如TiAl、TiN等等）以及低阻值金屬（例如Cu、Al、W等等）。在一實施例中，閘極114沿不同於第一方向的第二方向延伸。例如，第二方向與第一方向垂直。在一實施例中，閘介電層112配置於閘極114與通道層108之間。閘介電層112包括高介電常數（高k）層。高介電常數層包括介電常數大於7或甚至大於10的介電材料，例如金屬氧化物。源極/汲極區118配置於鰭片110的兩側。在一實施例中，源極/汲極118的底部向下延伸至部分抗擊穿層106中，但未超出抗擊穿層106的底部。源極/汲極區118的材料包括磊晶層（例如SiGe、SiP或SiC）及摻雜區（例如N型摻質或P型摻質）。
在一實施例中，先形成包括高k材料的閘介電層112以及包括含矽材料的閘極114。之後，形成源極/汲極區118。
在另一實施例中，先形成包括高k材料的閘介電層112以及包括含矽材料的虛設閘極。之後，形成源極/汲極區118。然後，再將虛設閘極置換為包括金屬的閘極114。至此，完成本發明之鰭狀場效電晶的製作。
接下來，將參照圖1E與圖2說明本發明之鰭狀場效電晶體的結構。本發明之鰭狀場效電晶體包括基底100、絕緣層103、少一鰭片110以及至少一閘極114。鰭片110包括由下而上的晶種層102、應力舒緩層104、抗擊穿層106以及通道層108。部分所述至少一鰭片101嵌入於基底100中。在一實施例中，晶種層102以及部分應力舒緩層104配置於基底100中。絕緣層103環繞所述鰭片110的下部。在一實施例中，絕緣層103高於抗擊穿層106與通道層108的界面107。至少一閘極114橫跨至少一鰭片110。在一實施例中，閘極114橫跨鰭片110的通道層108。
特別要說明的是，本發明的鰭片110中，基底100與晶種層102具有實質上相同的晶格常數，且抗擊穿層106與通道層108具有實質上相同的晶格常數。此外，晶種層102與抗擊穿層106之間配置晶格常數漸變的應力舒緩層104。更具體地說，本發明的鰭片110中，通道層108的鍺濃度等於抗擊穿層106的鍺濃度，抗擊穿層106的鍺濃度大於應力舒緩層104的鍺濃度（或平均鍺濃度），且應力舒緩104的鍺濃度（或平均鍺濃度）大於晶種層102的鍺濃度。在一實施例中，本發明的鰭片110具有下部矽、上部矽鍺以及中部鍺漸變的矽鍺。在另一實施例中，本發明的鰭片110具有下部矽、上部鍺以及中部鍺漸變的矽鍺。依此方式配置，可避免習知鰭片與基底之間的晶格失配現象。
此外，本發明藉由在通道層108的下方以及源極/汲極118之間配置抗擊穿層106。由於抗擊穿層106與源極/汲極118的導電類型相反，且抗擊穿層106的摻質濃度高於通道層108的摻質濃度，故可有效防止源極/汲極之間發生擊穿效應。此外，抗擊穿層106的底部低於源極/汲極118的底部，即使摻質向下擴散也可被有效防止，達到抗擊穿的效果。
在上述實施例中，雖然是以含矽基底以及含鍺鰭片為例來說明之，但並不用以限定本發明。本領域具有通常知識者應了解，本發明也可應用於其他材料基底（例如矽鍺基底、碳化矽基底、矽覆絕緣（SOI）基底等半導體基底）以及應用於其他材料鰭片（例如含碳鰭片），只要鰭片的下部材料與基底材料相同，且鰭片的上部材料具有漸變的應力變化即可。
綜上所述，在本發明之鰭狀場效電晶體中，藉由配置具有特殊組成的鰭片，不但可解決習知鰭片之晶格失配問題，且可避免擊穿現象，故可有效提升元件的效能，增加競爭力。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100‧‧‧基底
101‧‧‧虛設鰭片
102‧‧‧晶種層
103‧‧‧絕緣層
105‧‧‧溝渠
104‧‧‧應力舒緩層
106‧‧‧抗擊穿層
107‧‧‧界面
108‧‧‧通道層
110‧‧‧鰭片
112‧‧‧閘介電層
114‧‧‧閘極
118‧‧‧源極/汲極
圖1A至圖1E為依照本發明一實施例所繪示的一種鰭狀場效電晶體的製造方法的立體示意圖。 圖2為圖1E之沿I-I線的剖面示意圖。
100‧‧‧基底
102‧‧‧晶種層
103‧‧‧絕緣層
104‧‧‧應力舒緩層
106‧‧‧抗擊穿層
107‧‧‧界面
108‧‧‧通道層
110‧‧‧鰭片
112‧‧‧閘介電層
114‧‧‧閘極

Claims (20)

  1. 一種鰭狀場效電晶體，包括： 一基底； 至少一鰭片，其中部分該至少一鰭片嵌入於該基底中，且該至少一鰭片包括由下而上的一晶種層、一應力舒緩層以及一通道層；以及 至少一閘極，橫跨該至少一鰭片。
  2. 如申請專利範圍第1項所述的鰭狀場效電晶體，更包括一抗擊穿層，配置於該應力舒緩層與該通道層之間。
  3. 如申請專利範圍第2項所述的鰭狀場效電晶體，其中該通道層的鍺濃度等於該抗擊穿層的鍺濃度，該抗擊穿層的鍺濃度大於該應力舒緩層的鍺濃度，且該應力舒緩層的鍺濃度大於該晶種層的鍺濃度。
  4. 如申請專利範圍第2項所述的鰭狀場效電晶體，其中該應力舒緩層具有漸變的應力分布，且該應力舒緩層的鍺濃度自該晶種層往該抗擊穿層逐漸升高。
  5. 如申請專利範圍第2項所述的鰭狀場效電晶體，其中該抗擊穿層的摻質濃度大於該應力舒緩層或該通道層的摻質濃度。
  6. 如申請專利範圍第2項所述的鰭狀場效電晶體，更包括環繞該至少一鰭片的下部的一絕緣層，且該絕緣層的表面高於該抗擊穿層與該通道層的界面。
  7. 如申請專利範圍第1項所述的鰭狀場效電晶體，其中該通道層的鍺濃度的範圍為20%至100%。
  8. 如申請專利範圍第1項所述的鰭狀場效電晶體，其中該晶種層以及部分該應力舒緩層配置於該基底中。
  9. 如申請專利範圍第1項所述的鰭狀場效電晶體，其中該基底與該晶種層具有實質上相同的晶格常數，且該擊穿層與該通道層具有實質上相同的晶格常數。
  10. 一種鰭狀場效電晶體的製造方法，包括： 提供一基底，該基底上已形成有一絕緣層，該絕緣層中已形成有至少一溝渠，且該至少一溝渠延伸至部分該基底中； 於該至少一溝渠中依序形成一晶種層、一應力舒緩層以及一通道層； 移除部分該絕緣層，以裸露出部分該通道層；以及 形成至少一閘極，該至少一閘極橫跨該通道層。
  11. 如申請專利範圍第10項所述的鰭狀場效電晶體的製造方法，更包括於該應力舒緩層與該通道層之間形成一抗擊穿層。
  12. 如申請專利範圍第11項所述的鰭狀場效電晶體的製造方法，其中該通道層的鍺濃度等於該抗擊穿層的鍺濃度，該抗擊穿層的鍺濃度大於該應力舒緩層的鍺濃度，且該應力舒緩層的鍺濃度大於該晶種層的鍺濃度。
  13. 如申請專利範圍第11項所述的鰭狀場效電晶體的製造方法，其中該應力舒緩層具有漸變的應力分布，且該應力舒緩層的鍺濃度自該晶種層往該抗擊穿層逐漸升高。
  14. 如申請專利範圍第11項所述的鰭狀場效電晶體的製造方法，其中形成該晶種層、該應力舒緩層、該抗擊穿層以及該通道層的方法各自包括進行磊晶成長製程。
  15. 如申請專利範圍第11項所述的鰭狀場效電晶體的製造方法，其中該抗擊穿層的摻質濃度大於該應力舒緩層或該通道層的摻質濃度。
  16. 如申請專利範圍第15項所述的鰭狀場效電晶體的製造方法，其中該抗擊穿層的摻質包括砷、磷或硼。
  17. 如申請專利範圍第11項所述的鰭狀場效電晶體的製造方法，其中移除部分該絕緣層的步驟之後，剩餘的該絕緣層的表面高於該抗擊穿層與該通道層的界面。
  18. 如申請專利範圍第10項所述的鰭狀場效電晶體的製造方法，其中形成該至少一溝渠的方法包括： 提供具有至少一虛設鰭片的該基底，該絕緣層環繞該至少一虛設鰭片；以及 進行一蝕刻製程，以移除該至少一虛設鰭片以及部分該基底。
  19. 如申請專利範圍第10項所述的鰭狀場效電晶體的製造方法，其中該通道層的鍺濃度的範圍為20%至100%。
  20. 如申請專利範圍第10項所述的鰭狀場效電晶體的製造方法，其中該基底與該晶種層具有實質上相同的晶格常數，且該擊穿層與該通道層具有實質上相同的晶格常數。
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TWI781933B (zh) * 2016-06-30 2022-11-01 愛爾蘭商太浩研究公司 具有降低通道至基底漏電之摻雜亞鰭結構的鰭式場效電晶體

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