TW201714209A - 製造半導體裝置之方法 - Google Patents

製造半導體裝置之方法 Download PDF

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TW201714209A
TW201714209A TW105132604A TW105132604A TW201714209A TW 201714209 A TW201714209 A TW 201714209A TW 105132604 A TW105132604 A TW 105132604A TW 105132604 A TW105132604 A TW 105132604A TW 201714209 A TW201714209 A TW 201714209A
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Taiwan
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layer
dielectric layer
metal oxide
conductive material
metal
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TW105132604A
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English (en)
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鄧志霖
蔡榮訓
鄭凱方
黃心巖
陳海清
包天一
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台灣積體電路製造股份有限公司
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Publication of TW201714209A publication Critical patent/TW201714209A/zh

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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

於基板上形成多個高介電係數金屬閘極結構。高介電係數金屬閘極結構被多個間隙所隔開。高介電係數金屬閘極結構各包含第一介電層於高介電係數金屬閘極結構的上表面。以第一導電材料填充間隙。透過回蝕製程來於各間隙中移除部分的第一導電材料。使用旋轉塗佈沉積製程來形成金屬氧化層。於高介電係數金屬閘極結構上且於第一導電材料上形成金屬氧化層。於金屬氧化層上形成第二介電層。在第二介電層中蝕刻開口。開口被蝕刻貫穿第二介電層且貫穿金屬氧化層。以第二導電材料填充開口。

Description

製造半導體裝置之方法
本揭露實施例是有關於一種半導體技術，且特別是有關於一種製造半導體裝置之方法。
半導體積體電路(integrated circuit，IC)產業已歷經快速地成長。積體電路材料與設計的技術進步已產生了幾個世代的積體電路，其中每一世代相較於前一世代具有更小且更複雜的電路。然而，這樣的進步增加了加工與製造積體電路的複雜度，且為了實現這樣的進步，積體電路的加工與製造也需要取得同樣的進展。在積體電路演變的過程中，隨著幾何尺寸(如使用製造製程所可以創建的最小元件(或導線))減少，功能密度(如每單位晶片面積內互連元件的數量)已廣泛增加。
可形成多層互連結構作為半導體製造的一部分。除了其他的元件以外，互連結構包含金屬導線與介層窗/接觸以提供電性連接至電晶體元件，如閘極、源極與汲極。金屬導線與介層窗透過層間介電(interlayer dielectric，ILD)材料彼此電性絕緣。現有的半導體製造技術可使用氧 碳化矽(silicon oxycarbide，SiOC)來形成部分的層間介電質。然而，使用氧碳化矽來形成層間介電質可能會導致層間介電質中的孔洞被捕獲(trapped)，且會因為不期望的氧化而增加了電阻係數。如此之下，降低了半導體裝置的效能。
所以，雖然形成層間介電質的傳統方法與材料已普遍滿足它們的預期目的，但它們並沒有在各方面完全令人滿意。
本揭露提出一種製造半導體裝置的方法，包含：於基板上形成多個閘極結構，閘極結構被多個間隙所隔開；以導電材料填充多個間隙；於閘極結構上且於填充間隙的導電材料上形成金屬氧化層；於金屬氧化層上形成介電層；以及形成一個或多個導電接觸延伸貫穿介電層且貫穿金屬氧化層。
50‧‧‧半導體裝置
60‧‧‧基板
70‧‧‧源極/汲極
80‧‧‧閘極結構
90‧‧‧閘極間隔物
100、110、200、400‧‧‧層間介電層
120、150、420、440‧‧‧開口
130、220‧‧‧介電層
140‧‧‧接縫
160、230‧‧‧非晶矽層
210‧‧‧硬光罩層
250‧‧‧間隙
300、510‧‧‧導電材料
320‧‧‧凹口
350、500‧‧‧沉積製程
370‧‧‧金屬氧化層
380‧‧‧表面
410、430、480‧‧‧蝕刻製程
510A、510B‧‧‧導電接觸
550‧‧‧研磨製程
900‧‧‧方法
910、920、930、940、950、960‧‧‧步驟
從以下結合所附圖式所做的詳細描述，可對本揭露之態樣有更佳的了解。需注意的是，根據業界的標準實務，各特徵並未依比例繪示。事實上，為了使討論更為清楚，各特徵的尺寸都可任意地增加或減少。
[圖1]至[圖18]係根據本揭露的一些實施例之半導體裝置於各種製造階段的圖解的剖面側視圖。
[圖19]係繪示根據本揭露的一些實施例之製造半導體裝置的方法的流程圖。
本揭露提供了許多不同的實施例或例子，用以實作此揭露的不同特徵。為了簡化本揭露，一些元件與佈局的具體例子會在以下說明。當然，這些僅僅是例子而不是用以限制本揭露。例如，若在後續說明中提到了第一特徵形成在第二特徵上面，這可包括第一特徵與第二特徵是直接接觸的實施例；這也可以包括第一特徵與第二特徵之間還形成其他特徵的實施例，這使得第一特徵與第二特徵沒有直接接觸。此外，本揭露可能會在各種例子中重複圖示符號及/或文字。此重複是為了簡明與清晰的目的，但本身並不決定所討論的各種實施例及/或設置之間的關係。
再者，在空間上相對的用語，例如底下、下面、較低、上面、較高等，是用來容易地解釋在圖示中一個元件或特徵與另一個元件或特徵之間的關係。這些空間上相對的用語除了涵蓋在圖示中所繪的方向，也涵蓋了裝置在使用或操作上不同的方向。這些裝置也可被旋轉(例如旋轉90度或旋轉至其他方向)，而在此所使用的空間上相對的描述同樣也可以有相對應的解釋。
需要形成電互連以電性互連半導體裝置的各種微電子元件(如源極/汲極、閘極等)以作為半導體製造的一部分。一般而言，電互連，如金屬導線或介層窗，透過層間 介電材料彼此電性絕緣。傳統的半導體製造技術使用氧碳化矽作為層間介電質的材料。然而，使用氧碳化矽作為層間介電質的材料可能導致一些問題。舉例來說，使用化學氣相沉積(chemical vapor deposition，CVD)或原子層沉積(atomic layer deposition，ALD)製程來形成氧碳化矽材料。作為半導體按比例縮減製程的延續(如小於5奈米的技術節點)，這些製程可能不具有足夠的間隙填充效果。如此之下，孔洞可能形成於層間介電層內，這會降低半導體裝置效能。此外，氧碳化矽材料的形成也涉及含氧氣體。氧氣可氧化下方的金屬層(簡稱氧侵蝕)，且這可能導致電阻係數增加，這也是不受歡迎的。此外，氧碳化矽的形成可能遇到其他問題，例如因為受限的蝕刻選擇比而減少了製程視窗，又例如因為需要許多步驟(如研磨/平坦化製程)來形成氧碳化矽層而增加了成本。這些問題可能隨著元件尺寸越來越小而加劇。
為了解決上述討論之使用氧碳化矽來形成層間介電質的這些問題，本揭露旨在使用旋轉塗佈金屬氧化沉積製程來形成部分的層間介電質。本揭露的各種態樣現在將參照圖1至圖19來更詳細地討論。此處討論的實施例係使用N5(5奈米技術節點)中段(mid-end-of-line，MEOL)製程。
圖1至圖18係根據本揭露的各種態樣之半導體裝置50於各種製造階段的圖解的剖面側視圖。在所示的實施例中，於5奈米或更低的技術節點製造半導體裝置50。半導體裝置50可包含積體電路晶片、系統單晶片(system on chip，SoC)或其部分，且可包含各種被動與主動微電子元件，如電阻、電容、電感、二極體、金氧半導體場效電晶體(metal-oxide semiconductor field effect transistors，MOSFET)、互補式金氧半導體(complementary metal-oxide semiconductor，CMOS)電晶體、雙極接面電晶體(bipolar junction transistors，BJT)、橫向擴散金氧半導體(laterally diffused MOS，LDMOS)電晶體、高功率金氧半導體電晶體或其他種類的電晶體。
半導體裝置50包含基板60。在一些實施例中，基板60為摻雜p型摻雜物，如硼，的矽基板(如p型基板)。可選地，基板60可為其他合適的半導體材料。舉例來說，基板60可為摻雜n型摻雜物，如磷或砷，的矽基板(如n型基板)。基板60可包含其他元素半導體，如鍺或鑽石。基板60可選擇性地包含化合物半導體和/或合金半導體。再者，基板60可包含磊晶層(epitaxial layer，epi layer)，可應變以增進效能，且可包含絕緣層上覆矽(silicon-on-insulator，SOI)結構。
於基板60中形成多個已摻雜的區域。舉例來說，於基板60中形成電晶體的多個源極/汲極70。在一些實施例中，這些源極/汲極70可透過一個或多個離子佈植製程而形成。於基板60中也形成介電絕緣結構，如淺溝槽隔離(shallow trench isolation，STI)或深溝槽隔離(deep trench isolation，DTI)，但為求簡化，在此沒有具體地繪示出它們。
於基板60上形成多個閘極結構80。在所述的實施例中，閘極結構80係高介電係數金屬閘極(high-k metal gate，HKMG)結構。不像傳統的閘極結構具有多晶閘極電極，高介電係數金屬閘極結構具有包含金屬材料的閘極電極。舉例來說，在一些實施例中，金屬閘極電極可包含功函數金屬，如氮化鈦(titanium nitride，TiN)、鎢(tungsten，W)、氮化鎢(tungsten nitride，WN)或鎢鋁(tungsten aluminum，WA1)。金屬閘極電極也可包含鋁、鈦、鎢或銅來做為填充金屬。
也不像傳統的閘極結構具有二氧化矽閘極介電質，高介電係數金屬閘極結構具有高介電係數閘極介電質。高介電係數介電材料為介電係數大於二氧化矽的介電係數(約等於4)的材料。在一些實施例中，高介電係數金屬閘極結構的閘極介電質可包含氧化鉿(hafnium oxide，HfO2)，其介電係數的範圍為約18至約40，或在替代的實施例中，高介電係數金屬閘極結構的閘極介電質可包含氧化鋯(ZrO2)、氧化釔(Y2O3)、氧化鑭(La2O5)、氧化釓(Gb2O5)、氧化鈦(TiO2)、氧化鉭(Ta2O5)、氧化鉿鉺(HfErO)、氧化鉿鑭(HfLaO)、氧化鉿釔(HfYO)、氧化鉿釓(HfGbO)、氧化鉿鋁(HfAlO)、氧化鉿鋯(HfZrO)、氧化鉿鈦(HfTiO)、氧化鉿鉭(HfTaO)或氧化鍶鈦(SrTiO)。
高介電係數金屬閘極結構80的形成可能涉及閘極取代製程，其中首先形成假性(dummy)閘極電極(也可能是假性閘極介電質)，接著移除假性閘極電極，且假性閘 極電極隨後被金屬閘極電極(也可能是高介電係數閘極介電質)所取代。作為例示，形成高介電係數金屬閘極結構的細節詳述於2012年4月5日提申的美國專利申請號13/440,848，標題為Cost-effective gate replacement process，作者為Zhu等人，其為2014年6月17日公告的美國專利號8,753,931，其所揭露的內容以引用的方式併入本文。
閘極間隔物90設置於閘極結構80的側壁上。閘極間隔物可包含合適的介電材料。在所述的實施例中，閘極間隔物90包含氧碳化矽。在替代的實施例中，閘極間隔物90可包含其他合適的介電材料，如二氧化矽、碳化矽、氮氧化矽或其組合物。
於基板60上且於閘極間隔物90的側壁上設置層間介電層100。在所述的實施例中，層間介電層100包含氧碳化矽。在替代的實施例中，層間介電層100可包含其他合適的低介電係數介電材料。於層間介電層100上設置層間介電層110。在所述的實施例中，層間介電層110包含二氧化矽。在圖1所示的製造階段中，已執行平坦化製程，例如化學機械研磨(chemical mechanical polishing，CMP)製程，來平面化與平坦化層間介電層110與高介電係數金屬閘極結構80的表面。
現在請參照圖2，閘極結構80被回蝕(etch back)。換句話說，透過回蝕製程來移除部分的每一高介電係數金屬閘極結構80，如此可於高介電係數金屬閘極結構 80上方形成開口或溝槽120。
現在請參照圖3，於層間介電層110上且於高介電係數金屬閘極結構80上形成介電層130。也於開口120中形成介電層130。介電層130的形成也可稱為再填充製程。在所示的實施例中，介電層130包含氮化矽。透過原子層沉積製程來形成氮化矽，原子層沉積製程為共形的。共形的原子層沉積製程可能導致在部分的介電層130中的接縫140形成於高介電係數金屬閘極結構80上方。
現在請參照圖4，對介電層130執行平坦化/研磨製程，如化學機械研磨製程。化學機械研磨製程的結果，移除了部分的介電層130，且介電層130的剩餘部分具有實質上平面或平坦的表面，雖然接縫140在此時可能仍然存在。
現在請參照圖5，執行一個或多個蝕刻製程來移除設置於各高介電係數金屬閘極結構80上的部分的介電層130。也移除部分的閘極間隔物90、層間介電層100與層間介電層110。結果，於高介電係數金屬閘極結構80上形成開口150。
現在請參照圖6，於各個開口150中形成非晶矽層160。換句話說，於介電層130上(與部分的閘極間隔物90與層間介電層100上)形成非晶矽層160。透過於介電層130上且於層間介電層110上沉積非晶矽材料且執行化學機械研磨製程於被沉積的非晶矽材料直到非晶矽材料與層間介電層110共平面，可形成非晶矽層160。
現在請參照圖7，於層間介電層110上且於非晶矽層160上形成層間介電層200。層間介電層200可包含低介電係數介電材料。於層間介電層200上形成硬光罩層210。在一些實施例中，硬光罩層210可包含氮化鈦。於硬光罩層210上形成介電層220。在一些實施例中，介電層220可包含二氧化矽。接著於介電層220上形成非晶矽層230。因圖案化的目的而使用這些層210-230。
現在請參照圖8，執行圖案化的製程來移除設置於相鄰的高介電係數金屬閘極結構80之間的層間介電層110，也移除設置於被移除的層間介電層110下方的部分的層100。結果，於相鄰的高介電係數金屬閘極結構80之間形成間隙250。換句話說，高介電係數金屬閘極結構80彼此至少被間隙250所隔開。非晶矽層160仍存在。源極/汲極70透過間隙250而暴露，且在之後的製程中將於一個或多個源極/汲極70上形成導電接觸，以便提供電互連至源極/汲極。於其後可移除硬光罩層210、介電層220與非晶矽層230。
現在請參照圖9，於高介電係數金屬閘極結構80上形成導電材料300。透過合適的沉積製程可形成導電材料300。導電材料300填充間隙250。因此，導電材料300係與源極/汲極70電性與物理接觸。在一些實施例中，導電材料300包含鈷。在一些其他實施例中，導電材料300可包含鎢或釕。
現在請參照圖10，對導電材料300執行研磨/平坦化製程，如化學機械研磨製程。除了移除部分的導電材料 300，化學機械研磨製程也移除了非晶矽層160與層間介電層200(與部分的層間介電層110)。在化學機械研磨製程的最後，填充間隙250的導電材料300的部分的表面、層間介電層110的表面與設置於高介電係數金屬閘極結構80上的與介電層130的表面互為共平面。在此時也因為研磨，大部分移除了先前存在於層130內的接縫。
現在請參照圖11，蝕刻掉填充於各個間隙250中的部分的導電材料300。這可稱為鈷回蝕製程。回蝕製程形成凹口320(或開口)。在一些實施例中，回蝕製程具有大於約100埃的蝕刻深度(如凹口320的深度)。執行回蝕製程來避免或減少漏電的可能性。舉例來說，如果沒有回蝕導電材料300，則從高介電係數金屬閘極結構80的金屬閘極電極到導體(之後的製程所形成者)的漏電路徑將會更短，這意味著漏電流將更可能發生。於此，凹口320的蝕刻深度被配置的足夠深(如大於約100埃)以便最小化此漏電風險。
現在請參照圖12，執行沉積製程350來於層間介電層110、高介電係數金屬閘極結構80與導電材料300上形成金屬氧化層370。沉積製程350係旋轉塗佈沉積製程。在一些實施例中，以範圍從約500每分鐘旋轉數(revolutions-per-minute，RPM)到約3000每分鐘旋轉數的旋轉，且以範圍從約20秒到約200秒的週期來執行旋轉塗佈沉積製程。沉積製程350也可包含通入空氣或氮氣兩者之一的後烘(如在材料370已旋轉塗佈沉積之後)製程，其中後烘製程以範圍從約攝氏50度到約攝氏400度的溫度來執 行。執行這些製程條件以確保形成後的金屬氧化層370具有期望的厚度與品質。在一些實施例中，期望的厚度的範圍從約100埃到約1000埃。可理解的是，旋轉塗佈沉積製程並不涉及含氧氣體的使用。
在各種實施例中，金屬氧化層370可具有如下的材料組合物：氧化鋁、氧化鋯、氧化鋅、氧化鎢、氧化鉭、氧化鈦或氧化鉿。在一些實施例中，金屬氧化層370具有如下的特性：介電係數大於約7；漏電流範圍從約10-10到10-13安培/平方公分；以及介電崩潰(dielectric breakdown，EBD)範圍從約5-8毫伏/公分。
使用沉積製程350的金屬氧化層370的形成提供一些優點。舉例來說，金屬氧化材料的旋轉塗佈沉積具有良好的間隙填充效果，且確保在金屬氧化層370中將不會形成接縫或孔洞。相較之下，與透過沉積製程350的旋轉塗佈沉積來形成金屬氧化層370不同，傳統的方法通常透過化學氣相沉積或原子層沉積製程來形成氧碳化矽。透過化學氣相沉積或原子層沉積製程來形成氧碳化矽可能在氧碳化矽材料內捕獲(trap)孔洞。被捕獲的孔洞可能使製程控制更困難且可能導致可靠性的問題。
此外，傳統的形成氧碳化矽材料的化學氣相沉積或原子層沉積製程可能涉及含氧氣體(如氧氣或二氧化碳)。含氧氣體可能透過電漿反應氧化下方的導電材料(如導電材料300)，藉此造成電阻係數的增加，這是對於元件效能而言所不期望者。相較之下，於此所執行的沉積製程350 沒有使用含氧氣體，藉此消除了介於金屬氧化層370與導電材料300之間的介面的氧化的風險。
此外，在傳統的製造製程中，氧碳化矽層的表面形貌變化(surface topography variation)對後續的製程而言可能太多。所以，透過化學氣相沉積或原子層沉積形成氧碳化矽層之後，通常會在氧碳化矽層上執行研磨製程，如化學研磨製程。化學研磨製程使得氧碳化矽層平坦，但它也可能造成過多的氧碳化矽材料被移除。如此之下，化學機械研磨製程之後通常會執行其他的氧碳化矽沉積來確保氧碳化矽係足夠厚且具有平坦的表面。換句話說，形成氧碳化矽層的傳統方法可能涉及三個單獨的步驟：初始的氧碳化矽沉積製程、接續的化學機械研磨製程、接續的其他的氧碳化矽沉積製程。需要執行三個單獨的製程來形成氧碳化矽層既昂貴且更耗時。
相較之下，本揭露可在單一製程中形成金屬氧化層370-沉積製程370(使用旋轉塗佈沉積)。旋轉塗佈沉積的一個優點為金屬氧化層的表面380係足夠平坦，使得在附加的層可被形成在其上之前，不再需要後續的平坦化製程。換句話說，金屬氧化層370的表面380相較於傳統方法形成的氧碳化矽層係較平坦的(或具有較少的表面形貌變化)，使得任何後續的化學機械研磨製程為選擇性的而非必要性的。因為不需在金屬氧化層370上執行化學機械研磨製程，故將不會有任何厚度的損失，且如此也不需要金屬氧化材料的額外的沉積。在本方法中，於此的單一製造製程(如 沉積製程350)有效地取代涉及氧碳化矽形成的傳統製造中的三個單獨的製造製程。
現在請參照圖13，於金屬氧化層370的平坦表面380上形成其他的層間介電層400。透過習知技術中的合適的沉積製程，如化學氣相沉積，來形成層間介電層400。層間介電層400可包含合適的介電材料。
現在請參照圖14，執行一個或多個蝕刻製程410來於其中一個閘極結構80上形成開口420。開口420延伸貫穿層間介電層400，且貫穿金屬氧化層370，但停止於介電層130。換句話說，介電層130在製造的此步驟中作為蝕刻停止層。製造的此步驟也可稱為VG圖案化步驟(如閘極的圖案化導電介層窗/接觸)。
由此可見，本揭露的其他優點為其擴大了製程視窗。具體來說，由於介於介電層130與金屬氧化層370(相較於傳統製程中的介電層130與氧碳化矽層)之間的蝕刻選擇比的增加，擴大了製程視窗。更詳細地說，如同上面所討論的，介電層130包含氮化矽。當使用氧碳化矽層而非使用金屬氧化層370，必須配置蝕刻製程420使得介於氮化矽材料與氧碳化矽材料之間有足夠的蝕刻選擇比。換句話說，氮化矽材料與氧碳化矽材料需具有顯著地不同的蝕刻速率，使得當氮化矽材料實質上仍未被蝕刻時，氧碳化矽材料能被蝕刻掉。然而，這可證明為困難的，因為氮化矽與氧碳化矽都包含矽，這意味著以配置蝕刻製程420來移除氧碳化矽而不影響氮化矽是困難的。
相較之下，本揭露使用金屬氧化物來佈植層370。氮化矽與金屬氧化物之間沒有元件交疊。照此方法，更容易配置蝕刻製程420來移除層370的金屬氧化材料，而不影響層130的氮化矽材料。換句話說，改善了介於金屬氧化層370與介電層130之間的蝕刻選擇比，這允許更大的製程視窗。在一些實施例中，蝕刻選擇比可調整至15：1或更高。
現在請參照圖15，執行其他的蝕刻製程430來於兩個相鄰的高介電係數金屬閘極結構80之間形成開口440。換句話說，於其中一個源極/汲極70上方形成開口440。開口440延伸貫穿層間介電層400，但停止於金屬氧化層370。換句話說，金屬氧化層370作為此製造步驟中的蝕刻停止層。此製造步驟也可稱為VD圖案化步驟(如源極/汲極的圖案化導電介層窗/接觸)。
現在請參照圖16，執行額外的蝕刻製程480來使開口420、440更往下延伸。透過開口420而暴露的部分的介電層130被蝕刻掉，所以此時開口420延伸貫穿介電層130，藉此使高介電係數金屬閘極結構80暴露。透過開口440而暴露的部分的金屬氧化層370也被蝕刻掉，所以此時開口440延伸貫穿金屬氧化層370，藉此使導電材料300暴露。
現在請參照圖17，執行沉積製程500來於層間介電層400上形成導電材料510。也形成導電材料510來填充開口420、440。所以，導電材料510與閘極結構80(先前 透過開口420而暴露者)物理及電性接觸，且導電材料510與導電材料300(先前透過開口440而暴露者)物理及電性接觸。在一些實施例中，導電材料510包含鈷。在一些其他實施例中，導電材料510可包含鎢或釕。
現在請參照圖18，可執行研磨製程550來移除導電材料510與層間介電層400的多餘的部分，且平坦化導電材料510的剩餘的部分的表面。結果，形成導電接觸510A、510B，其與金屬氧化層370具有共平面的表面。導電接觸510A的下方提供電性連接至高介電係數金屬閘極結構80，且導電接觸510B的下方提供電性連接至源極/汲極70。
圖19係繪示根據本揭露的各種態樣之製造半導體裝置的方法900的流程圖。執行方法900的一個或多個步驟作為製造製程的一部分，其半導體技術節點為5奈米技術節點或更小。
方法900包含步驟910：於基板上形成多個閘極結構。閘極結構被多個間隙所隔開。在一些實施例中，閘極結構為高介電係數金屬閘極結構。在一些實施例中，分別形成閘極結構來於閘極結構的上表面具有氮化矽層。
方法900包含步驟920：以導電材料填充間隙。在一些實施例中，導電材料包含鈷。
方法900包含步驟930：在每個間隙中回蝕部分的導電材料。
方法900包含步驟940：於閘極結構上且於填充 間隙的導電材料上形成金屬氧化層。在一些實施例中，使用旋轉塗佈沉積製程來執行金屬氧化層的形成。旋轉塗佈沉積製程沒有使用含氧氣體。在一些實施例中，金屬氧化層的形成包含形成氧化鋁、氧化鋯、氧化鋅、氧化鎢、氧化鉭、氧化鈦或氧化鉿以作為金屬氧化材料。
方法900包含步驟950：於金屬氧化層上形成介電層。在一些實施例中，介電層包含低介電係數介電材料且形成介電層作為部分的層間介電層。在一些實施例中，執行於金屬氧化層上介電層的形成並沒有研磨金屬氧化層的表面。換句話說，於金屬氧化層的表面上形成介電層之前，金屬氧化層的表面不需研磨。
方法900包含步驟960：形成一個或多個導電接觸延伸貫穿介電層且貫穿金屬氧化層。在一些實施例中，一個或多個導電接觸的形成包含於閘極結構上蝕刻開口。開口被蝕刻貫穿氮化矽層。在一些實施例中，配置蝕刻來對於金屬氧化層與氮化矽層具有不同的蝕刻選擇比。
基於上述討論，可見本揭露提供優於傳統形成層間介電質的方法與裝置的優點。然而，可理解的是，其他實施例可能提供額外的優點，且並非所有的優點必然在此揭露，且並非所有的實施例需要有特定的優點。一個優點為旋轉塗佈金屬氧化沉積沒有使用含氧氣體，這減少了不經意地氧化下方的金屬材料的風險。其他優點為相較於傳統使用化學氣相沉積與原子層沉積方法來形成使用氧碳化矽材料的層間介電質，旋轉塗佈金屬氧化沉積具有較佳的間隙填充效 果。所以，原本氧碳化矽材料會具有孔洞被捕獲於金屬氧化材料內部，但本揭露之實施例則沒有孔洞被捕獲於金屬氧化材料內部。又一其他優點為能以執行單一製造製程(旋轉塗佈金屬氧化沉積)來取代習知地執行三個單獨的製程(氧碳化矽沉積、氧碳化矽的化學機械研磨、後續的氧碳化矽沉積)。這導致製造成本與耗時的減少。再一優點為相較於氮化矽層與氧碳化矽，介於氮化矽層(位於閘極上方)與金屬氧化物之間的蝕刻選擇比可增加。這幫助擴大製程視窗。
本揭露的一態樣涉及製造半導體裝置的方法。於基板上形成多個閘極結構。閘極結構被多個間隙所隔開。以導電材料填充間隙。於閘極結構上且於填充間隙的導電材料上形成金屬氧化層。於金屬氧化層上形成介電層。形成一個或多個導電接觸延伸貫穿介電層且貫穿金屬氧化層。
本揭露的其他態樣涉及半導體裝置的製造方法。於基板上形成多個高介電係數金屬閘極結構。高介電係數金屬閘極結構被多個間隙所隔開。高介電係數金屬閘極結構各包含第一介電層於高介電係數金屬閘極結構的上表面。以第一導電材料填充間隙。透過回蝕製程於各間隙中移除部分的第一導電材料。使用旋轉塗佈沉積製程來形成金屬氧化層。於高介電係數金屬閘極結構上且於第一導電材料上形成金屬氧化層。於金屬氧化層上形成第二介電層。在第二介電層中蝕刻開口。開口被蝕刻貫穿第二介電層且貫穿金屬氧化層。以第二導電材料填充開口。
本揭露的又一其他態樣涉及半導體裝置。於基 板上形成多個閘極結構。閘極結構被多個間隙所隔開。第一介電材料設置於基板上且部分地填充間隙。於各間隙中，導電材料設置於第一介電材料上。金屬氧化材料設置於導電材料上。
以上概述了數個實施例的特徵，因此熟習此技藝者可以更了解本揭露的態樣。熟習此技藝者應了解到，其可輕易地把本揭露當作基礎來設計或修改其他的製程與結構，藉此實現和在此所介紹的這些實施例相同的目標及/或達到相同的優點。熟習此技藝者也應可明白，這些等效的建構並未脫離本揭露的精神與範圍，並且他們可以在不脫離本揭露精神與範圍的前提下做各種的改變、替換與變動。
900‧‧‧方法
910、920、930、940、950、960‧‧‧步驟

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  1. 一種製造半導體裝置的方法，包含：形成複數個閘極結構於一基板上，該些閘極結構被複數個間隙所隔開；以一導電材料填充該些間隙；形成一金屬氧化層於該些閘極結構上且於填充該些間隙的該導電材料上；形成一介電層於該金屬氧化層上；以及形成一或複數個導電接觸延伸貫穿該介電層且貫穿該金屬氧化層。
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