TW201709533A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a substrate; a metal-oxide semiconductor (MOS) transistor disposed in the substrate; and a shallow trench isolation (STI) disposed in the substrate and around the MOS transistor, wherein the STI comprises a stress material.

Description

Semiconductor component and manufacturing method thereof

The present invention relates to a semiconductor component, and more particularly to a semiconductor component having a stress shallow trench isolation or a stress contact plug.

A conventional Metal Oxide Semiconductor (MOS) transistor generally includes a substrate, a source region, a drain region, a channel between the source region and the drain region, and a gate located in the channel. Above. Wherein, the gate electrode comprises a gate dielectric layer on the channel, a gate conductive layer on the gate dielectric layer, and a sidewall spacer on the sidewall of the gate conductive layer. In general, under a fixed electric field, the amount of drive current flowing through the channel of the MOS transistor is proportional to the carrier mobility in the channel. Therefore, how to increase the carrier mobility to increase the switching speed of the MOS transistor in the existing process equipment has become one of the major issues in the field of semiconductor technology.

The epitaxial growth process, for example, the germanium/drain process, is performed by epitaxially forming a germanium telluride epitaxial layer in a semiconductor substrate adjacent to each sidewall after the sidewall spacers are formed. It utilizes the different lattice constants of the bismuth telluride layer and the enthalpy, so that the bismuth epitaxial layer is structurally strained in the ruthenium substrate to form strain enthalpy. Since the lattice constant of the tantalum layer is larger than that of the tantalum layer, the band structure of the tantalum is changed, and the mobility of the carrier is increased, so that the switching speed of the MOS transistor can be increased to improve the integrated body. Circuit performance and speed.

In addition to the application of epitaxial layers, and as the semiconductor process enters the deep submicron era, the use of high stress films in semiconductor processes to drive the drive current of MOS transistors has become a hot topic. At present, the use of high-stress films to enhance the driving current of MOS transistors can be divided into two aspects: one is applied to the poly-stressor before the formation of metal bismuth such as nickel bismuth; on the other hand, It is applied to a contact etch stop layer (CESL) after formation of a metal halide such as nickel bismuth.

However, the use of epitaxial layers or high-stress films to enhance the carrier flow rate in the channel region of MOS transistors has reached a bottleneck, so how to additionally enhance the performance of the entire semiconductor device over the processes widely used today. It is an important issue today.

SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a semiconductor device which enhances carrier mobility of a MOS transistor channel region mainly by shallow trench isolation or contact plugs having stress.

A preferred embodiment of the invention discloses a semiconductor device comprising a substrate, a MOS transistor disposed in the substrate, and a shallow trench isolation disposed in the substrate and disposed around the MOS transistor. The shallow trench isolation is composed of a stress material.

Another embodiment of the invention discloses a semiconductor device including a substrate; a MOS transistor is disposed in the substrate; a dielectric layer is disposed on the substrate and covering the MOS transistor; and at least one stress insertion The plug is disposed in the dielectric layer and disposed around the MOS transistor. Wherein the contact plug is composed of a stress material.

Yet another embodiment of the present invention is directed to a method of fabricating a semiconductor device. First providing a substrate, then forming a MOS transistor in the substrate, forming a dielectric layer on the substrate and covering the MOS transistor, and forming at least one contact hole disposed in the dielectric layer and disposed on the substrate The MOS semiconductor is surrounded by a transistor. Finally, the contact hole is filled with a stress material.

Please refer to FIG. 1. FIG. 1 is a schematic view showing the fabrication of a semiconductor device according to a preferred embodiment of the present invention. As shown in FIG. 1, a substrate 10 is first provided, such as a germanium substrate or a silicon-on-insulator (SOI) substrate. Then, a shallow trench isolation (STI) process is performed. For example, one or more lithography and etching processes are used to form a recess 12 in the substrate to separate or surround each active region, and then a stress material 14 is formed. The surface of the substrate 10 is filled with the recess 12, and then a planarization process is performed, for example, a portion of the stress material 14 on the surface of the substrate 10 is removed by a chemical mechanical polishing process so that the stress material 14 in the recess 12 is flush with the surface of the substrate 10. A shallow trench isolation 16 structure filled with stress material 14 is formed.

In accordance with a preferred embodiment of the present invention, the stress material 14 filling the recess 12 may be selected from the group consisting of tantalum nitride, boron nitride, tantalum oxide, tantalum carbide, and tantalum carbon oxide, and filled with shallow trench isolation. The stress material 14 of 16 may be a single material layer, or a plurality of layers of the same or different material layer structures, all of which are within the scope of the present invention. The stress of tantalum nitride is between -3.5 GPa and 2.0 GPa; and the stress of boron nitride is between -1 GPa and -2 GPa. Since boron nitride is stable in air, in a vacuum or in an inert gas and is an insulator excellent in thermal conductivity, boron nitride is preferably used as the stress material for filling the groove 12 in the present invention.

Next, a MOS transistor process is performed, for example, a gate structure 18 is formed on the substrate 10 on both sides of the shallow trench isolation 16 in FIG. The gate structure 18 can include a gate dielectric layer 20 and a gate electrode 22. Then, a sidewall portion 24 and a main sidewall 26 are respectively formed on the sidewalls of the gate structures 18, and light-doped corresponding conductive types are respectively formed in the substrate 10 on both sides of the bias sidewalls 24 and the main sidewalls 26, respectively. Heterogeneous pole 28 and source/drainage 30.

A selective epitaxial growth process can then be performed to form an epitaxial layer (not shown) in the substrate 10 on either side of the main sidewalls 26. The material of the epitaxial layer may vary depending on the type of the transistor. For example, if the prepared transistor is an NMOS transistor, the epitaxial layer preferably comprises tantalum carbide; and if the prepared transistor is a PMOS transistor, the epitaxial layer preferably comprises germanium germanium.

Then, a metallization process can be performed. For example, a metal layer (not shown) composed of cobalt, titanium, nickel, platinum, palladium, molybdenum or a combination thereof is formed on the substrate 10 and covers the source/drain 30. And the epitaxial layer, and then using at least one rapid thermal anneal (RTP) process to react the metal layer with the source/drain 30 and the epitaxial layer to form a surface on the substrate 10 on both sides of the main sidewall 26 Deuterated metal layer 32. Finally, the unreacted metal is removed.

A stressor layer 34 can then be formed and cover the surface of the substrate 10 and the gate structure 18. The material of the stress layer 34 may also vary according to the type of the transistor. For example, if the prepared transistor is an NMOS transistor, the stress layer is preferably a tensile stress layer; The transistor is a PMOS transistor, and the stressor layer is preferably a compressive stress layer. The stress layer 34 can also serve as an etch stop layer when etching contact holes.

Then, an interlayer dielectric layer 36 is formed on the substrate 10 and covers the stress layer 34. Then, a plurality of contact holes are formed in the interlayer dielectric layer 36 and the stress layer 34, and a metal material such as tungsten is filled in to form a plurality of connections. Contact plug 38 of source/drain 30. Thus, the fabrication of a semiconductor device of a preferred embodiment of the present invention has been completed.

In this embodiment, the MOS transistors on both sides of the shallow trench isolation are preferably MOS transistors of the same conductivity type, for example, NMOS transistors or PMOS transistors, so as to fill the shallow trench isolation 16 The stress material 14 can simultaneously provide a tensile stress to the NMOS transistors on both sides, or simultaneously provide a compressive stress to the PMOS transistors on both sides.

2 and 3, FIG. 2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along line AA' of FIG. As shown in the figure, a substrate 60 such as a germanium substrate or a silicon-on-insulator (SOI) substrate or the like is provided first. The substrate 60 has at least one active region 92, and is provided with a shallow trench isolation 94 for isolation, and the shallow trench isolation 94 can also be a shallow shallow trench isolation disclosed in the preferred embodiment of the first embodiment of the present invention. structure.

At least one gate structure 68 is formed on the substrate 60. The gate structure 68 can include a gate dielectric layer 70 and a gate electrode 72. Then, a bias sidewall spacer 74 and a main sidewall spacer 76 are formed on the sidewalls of each gate structure 68, and a lightly doped drain 78 is formed in the substrate 60 on both sides of the offset sidewall spacer 74 and the main sidewall spacer 76. Source / drain 80.

A selective epitaxial growth process can then be performed to form an epitaxial layer (not shown) in the substrate 60 on either side of the main sidewall 76. The material of the epitaxial layer may vary depending on the type of the transistor. For example, if the prepared transistor is an NMOS transistor, the epitaxial layer preferably comprises tantalum carbide; and if the prepared transistor is a PMOS transistor, the epitaxial layer preferably comprises germanium germanium.

Then, a metallization process can be performed. For example, a metal layer (not shown) composed of cobalt, titanium, nickel, platinum, palladium, molybdenum or the like is formed on the substrate 60 and covers the source/drain 80 and the epitaxial layer. a layer, followed by at least one rapid thermal anneal (RTP) process to react the metal layer with the source/drain 80 and the epitaxial layer to form a deuterated metal layer on the surface of the substrate 60 on either side of the main sidewall 76 82. Finally, the unreacted metal is removed.

A stressor layer 84 can then be selectively formed and overlying the surface of the substrate 60 and gate structure 68. The material of the stress layer 84 may also be different depending on the type of the transistor. For example, if the prepared transistor is an NMOS transistor, the stress layer 84 is preferably a tensile stress layer; The prepared transistor is a PMOS transistor, and the stress layer 84 is preferably a compressive stress layer. The stress layer 34 can also serve as an etch stop layer when etching contact holes.

An interlayer dielectric layer 86 is then formed over the substrate 60 and overlying the stressor layer 84, and then one or more etching processes are performed to form a plurality of contact holes 88 in the interlayer dielectric layer 86 and the stress layer 84. A stressor material is then filled into the contact holes 88 to form a plurality of stressed stress plugs 90 in the contact holes 88. It should be noted that, unlike the contact plug generally connected to the source/drain 80 in the substrate, the stress plug 90 having stress in the embodiment is mainly disposed around the entire MOS transistor and is not electrically connected to the source/汲. The main purpose of the pole 80 is to apply the required stress to the channel region of the entire MOS transistor, rather than for electrical connection. Therefore, the position of the stress plug 90 of the present invention is preferably the extending direction of the parallel gate structure 68. , that is, the parallel channel width. Moreover, the MOS transistors on both sides of the stress plug 90 are preferably MOS transistors of the same conductivity type, for example, NMOS transistors or PMOS transistors, so that the stress plugs 90 can simultaneously provide NMOS on both sides. The transistor is subjected to a tensile stress, or a PMOS transistor on both sides is simultaneously supplied with a compressive stress.

In accordance with a preferred embodiment of the present invention, the stressor material filling the contact holes 88 may be selected from the group consisting of tantalum nitride, boron nitride, tantalum oxide, tantalum carbide, and tantalum carbonium oxide. The stress of tantalum nitride is between -3.5 GPa and 2.0 GPa; and the stress of boron nitride is between -1 GPa and -2 GPa. Since boron nitride is stable in air, in a vacuum or in an inert gas and is an insulator excellent in thermal conductivity, the present invention preferably uses boron nitride as a stress material for filling the contact hole 88. Thus, the fabrication of a semiconductor device of a preferred embodiment of the present invention has been completed.

Then, one or more etching processes are performed to form a plurality of contact holes (not shown) in the interlayer dielectric layer 86 and the stress layer 84. A conductive material is then filled into the contact holes to form a plurality of conductive plugs (not shown) in the contact holes. It should be noted that the contact plugs for electrical connection may be located at any position within the active region 92 for electrically connecting the source/drain 80, for example, to the gate structure 68 and the stress plug 90. The stress plug 90 is located between the gate structure 68 and the contact plug, or even the contact plug is disposed in the stress plug 90 and passes through the stress plug 90 to electrically connect the source/drain 80. Please also refer to Fig. 4, which is a view of the stress plug and the contact plug coexisting. As shown in the figure, the present invention can provide a plurality of contact plugs 96 between the stress plugs 90 and the gate structures 68 to obtain a situation in which the stress plugs 90 and the conductive plugs 96 coexist. It should be noted that the position where the conductive plug 96 is disposed is not limited to the one shown in the figure, and may be disposed at any position of the active region 92, for example, at a position adjacent to the end of the stress plug 90. It is within the scope of the invention.

In summary, the present invention preferably forms shallow trench isolation in the substrate or fills the stress material when forming contact holes in the interlayer dielectric layer to form a shallow trench isolation structure or contact plug with stress, so that In addition to the stress structures such as the epitaxial layer and the stress layer, the carrier mobility of the entire MOS transistor in the channel region is better improved. In addition, the above methods for forming shallow trench isolation or contact plugs with stress can be arbitrarily matched with various processes and applied to different components, such as memory components or high voltage components. Secondly, the transistor disclosed in the present invention may comprise a transistor formed by a polysilicon gate or a metal gate, and the metal gate may be selected from a gate first process and a gate gate according to process requirements. Process, pre-high dielectric constant (high-k first) process and post-high dielectric constant (high-k last) process. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Base
12‧‧‧ Groove
14‧‧‧stress materials
16‧‧‧Shallow trench isolation
18‧‧‧ gate structure
20‧‧‧ gate dielectric layer
22‧‧‧gate electrode
24‧‧‧ biased side wall
26‧‧‧Main side wall
28‧‧‧Lightly doped bungee
30‧‧‧Source/Bungee
32‧‧‧Deuterated metal layer
34‧‧‧stress layer
36‧‧‧Interlayer dielectric layer
38‧‧‧Contact plug
60‧‧‧Base
68‧‧‧ gate structure
70‧‧‧ gate dielectric layer
72‧‧‧ gate electrode
74‧‧‧ biased side wall
76‧‧‧Main side wall
78‧‧‧Lightly doped bungee
80‧‧‧Source/Bungee
82‧‧‧Deuterated metal layer
84‧‧‧stress layer
86‧‧‧Interlayer dielectric layer
88‧‧‧Contact hole
90‧‧‧stress plug
92‧‧‧active area
94‧‧‧Shallow trench isolation
96‧‧‧Contact plug

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic view showing the fabrication of a semiconductor device in accordance with a preferred embodiment of the present invention. Fig. 2 is a view showing a semiconductor element according to another embodiment of the present invention. Fig. 3 is a schematic cross-sectional view taken along line AA' of Fig. 2. Fig. 4 is a top view showing the stress plug and the contact plug coexisting at the same time according to another embodiment of the present invention.

10‧‧‧Base

12‧‧‧ Groove

14‧‧‧stress materials

16‧‧‧Shallow trench isolation

18‧‧‧ gate structure

20‧‧‧ gate dielectric layer

22‧‧‧gate electrode

24‧‧‧ biased side wall

26‧‧‧Main side wall

28‧‧‧Lightly doped bungee

30‧‧‧Source/Bungee

32‧‧‧Deuterated metal layer

34‧‧‧stress layer

36‧‧‧Interlayer dielectric layer

38‧‧‧Contact plug

Claims (16)

A semiconductor device comprising: a substrate; a transistor disposed in the substrate; a dielectric layer disposed on the substrate and covering the transistor; and at least one stress plug disposed in the dielectric layer and disposed on the substrate Around the transistor, the stress plug is composed of a stress material. The semiconductor device according to claim 1, wherein the stress material is selected from the group consisting of tantalum nitride, boron nitride, tantalum oxide, tantalum carbide, and tantalum carbonitride. The semiconductor device of claim 2, wherein the stress of the tantalum nitride is between -3.5 GPa and 2.0 GPa. The semiconductor device of claim 2, wherein the boron nitride stress is between -1 GPa and -2 GPa. The semiconductor device of claim 1, wherein the transistor comprises: a gate structure; a sidewall disposed on a sidewall of the gate structure; and a source/drain disposed in the gate structure Side of the substrate. The semiconductor device of claim 5, further comprising a stress layer disposed on the substrate and the surface of the gate structure. The semiconductor device of claim 5, wherein the gate structure is a metal gate or a polysilicon gate. The semiconductor device of claim 5, further comprising at least one conductive plug disposed on the substrate and connecting the source/drain, the stress plug surrounding the gate structure, and the conductive plug The device is disposed between the gate structure and the stress plug. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a transistor disposed in the substrate; forming a dielectric layer on the substrate and covering the transistor; and forming at least one contact hole disposed on the dielectric layer The middle portion is disposed around the transistor; and the contact hole is filled with a stress material. The method of claim 9, wherein the stress material is selected from the group consisting of tantalum nitride, boron nitride, tantalum oxide, tantalum carbide, and tantalum carbonitride. The method of claim 10, wherein the stress of the tantalum nitride is between -3.5 GPa and 2.0 GPa. The method of claim 10, wherein the boron nitride stress is between -1 GPa and -2 GPa. The method of claim 9, wherein the MOS transistor comprises: a gate structure; a sidewall disposed on a sidewall of the gate structure; and a source/drain provided at the gate In the substrate on both sides of the structure. The method of claim 13, further comprising forming a stressor layer on the substrate and the surface of the gate structure. The method of claim 13, wherein the gate structure is a metal gate or a polysilicon gate. The semiconductor device of claim 13, further comprising forming at least one conductive plug on the substrate and connecting the source/drain, the stress plug surrounding the gate structure, and the conductive plug A plug is disposed between the gate structure and the stress plug.