TWI520188B - Semiconductor structure and method of fabricating the same - Google Patents

Description

Semiconductor structure and its process

The present invention relates to a semiconductor structure and a process thereof, and more particularly to a semiconductor structure in which a gate line width is reduced and its process.

In recent years, as various consumer electronic products continue to be miniaturized, the size of semiconductor component designs has been shrinking to meet the trend of high integration, high efficiency, low power consumption, and product demand.

As the size of field effect transistors (FETs) components continues to shrink, the development of conventional planar field effect transistor components has faced process limitations. In order to overcome the process limitation, the replacement of planar transistor components with non-planar field effect transistor components, such as fin field effect transistor (Fin FET) components, has become the mainstream trend. . Since the three-dimensional structure of the fin field effect transistor element can increase the contact area between the gate and the fin structure, the control of the gate to the carrier channel region can be further increased, thereby reducing the bucking caused by the small-sized component. The drain induced barrier lowering (DIBL) effect can suppress the short channel effect (SCE). And because the fin field effect transistor element has a wider channel width at the same gate length, a doubled drain drive current can be obtained. Even the threshold voltage of the transistor element can be regulated by adjusting the work function of the gate.

In the fabrication of a conventional fin field effect transistor device, a sidewall of the gate and fin structure is covered with a spacer. During the formation of the spacer, the spacer material (mostly SiN) tends to remain on the sidewall of the fin structure, and the hole filling rate is not good, and it is difficult to fill the structure such as the groove or the trench. Moreover, the presence of the spacers hinders the subsequent formation of a lightly doped drain (LDD) by ion implantation, so that the dopant is not easily implanted in the sidewall of the fin structure, thus forming The gate element has an excessive electric field gradient that adversely affects its electrical properties.

Therefore, the present invention improves the process of the conventional fin field effect transistor component to further improve the performance of the component.

In view of the absence of the aforementioned prior art, the present invention specifically proposes a novel semiconductor structure and process thereof. The method of the invention solves the problem that the dopant is easily blocked by the spacer in the ion implantation process by performing the fabrication of the lightly doped gate structure after the gate reduction process. Furthermore, by forming the spacer structure with a low dielectric constant (low-k) material after forming the lightly doped drain, it is possible to further improve the electrical properties of the formed gate element.

One of the objectives of the present invention is to provide a non-planar semiconductor process, the process comprising the steps of: providing a substrate, forming at least one fin structure on the substrate, forming a gate covering a portion of the fin structures, forming a plurality of epitaxial structures covering the fin structures on both sides of the gate, and the fin structures on the two sides of the gate and the epitaxial structures respectively forming a source and a drain a gate reducing process to reduce the gate such that the gate is separated from the epitaxial structures on both sides of the gate, and an ion implantation process is performed to be located on both sides of the gate and the gate A lightly doped drain is formed in each of the fin structures between the epitaxial structures, and a spacer is formed on the sidewalls of the gate and the epitaxial structures.

Another object of the present invention is to provide a planarized semiconductor process, the process step of providing a substrate, forming a gate on the substrate, forming an epitaxial structure, and the epitaxial structures on both sides of the gate. Forming a source and a drain, respectively, performing a gate reduction process to reduce the gate, so that the gate is separated from the epitaxial structures on both sides of the gate, and an ion implantation process is performed on the gate After the reduction process, a lightly doped drain is formed in the substrate between the gate and the epitaxial structures on either side of the gate, and a spacer is formed on the sidewall of the gate.

A further object of the present invention is to provide a non-planarized semiconductor structure, the structure comprising a substrate and at least one fin structure disposed on the substrate and having a gate covering a portion of the fin structure and a portion of the substrate. a plurality of epitaxial structures covering the fin structures on both sides of the gate and separated from the gate structure and defining between each of the gates, the epitaxial structure, and the fin structure a recess, a source and a drain, respectively formed on the fins on both sides of the gate and the light-doped drains in the epitaxial structures, respectively formed at the gate and the a fin structure between the epitaxial structures on both sides of the gate; and a spacer formed on the sidewall of the gate and the epitaxial structures, wherein the spacer is filled in the recess It is flush with the top surface of the epitaxial structures.

The objectives and other objects of the present invention will become more apparent from the written description of the appended claims.

In the detailed description that follows, the component symbols are marked as part of the accompanying drawings and are described in the manner in which the particular embodiments of the embodiments can be practiced. Such embodiments will be described in sufficient detail to enable those of ordinary skill in the art to practice. The reader is aware that other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the embodiments. Therefore, the following detailed description is not to be considered as a limitation, and the embodiments included herein are defined by the scope of the accompanying claims.

Certain terms are used throughout the description of the invention and the scope of the appended claims. Those skilled in the art will appreciate that semiconductor component manufacturers may refer to a different component by different names, such as spacers and spacers, reduction processes, or pullbacks. Furthermore, in the following description, the preceding vocabulary such as "first", "second", "nth", and the like are used to give the same or similar elements a representative reference. It is not intended to limit the claimed elements or have any special patent features.

A plurality of embodiments will now be provided below in conjunction with the drawings to illustrate the semiconductor process of the present invention. 1-14 is a schematic cross-sectional view showing a non-planarized semiconductor process according to an embodiment of the present invention, and FIG. 15 is a schematic perspective view showing a gate element formed by the process according to the present invention; 21 is a cross-sectional view showing a planarization semiconductor process according to another embodiment of the present invention, and FIGS. 22-25 are diagrams showing an alternative metal gate (RMG) in a further embodiment of the present invention. A schematic cross-section of the process.

First, please refer to FIGS. 1-15, which are sequentially showing the flow of steps of a non-planar semiconductor process of the present invention. The non-planarized semiconductor process includes fabricating a fin field effect transistor (FinFET) structure or a tri-gate field-effect transistor (tri-gate FET) structure. In the present embodiment, a manufacturing process using bulk Si as a substrate is taken as an example. As shown in Fig. 1, a substrate 100 such as a substrate is first provided as a basis for the entire semiconductor structure. An NMOS region and a PMOS region may be defined in advance on the substrate 100, and corresponding P well and N well structures have been formed. Next, a patterned mask layer 102 is formed on the substrate 100 as an etch mask in the subsequent three-dimensional fin structure forming step. The mask layer 102 may comprise a single material layer or a stacked material layer, such as a pad oxide layer 104 (such as hafnium oxide) and a nitride layer 106 (such as tantalum nitride) on the pad oxide layer 104. The mask layer 102 can be patterned by performing an etch lithography process E1 on a deposited mask material layer and expose portions of the substrate 100. After forming the patterned mask layer, next, as shown in FIG. 2, the substrate 100 is subjected to an etching step using the patterned mask layer 102 as a mask, and the pattern defined by the mask layer 102 is transferred to the substrate 100. Raised, parallel fin structures 108a and 108b are formed. In the present embodiment, the mask layer 102 defines a two-fin pattern, but is not limited to this number.

After the fin structures 108a and 108b are formed, next, as shown in FIG. 3, an insulating structure 110 (e.g., an oxide layer) is formed between the fin structures by processes such as deposition, planarization, and etch back. For example, the insulating structure 110 can be formed by a general shallow trench isolation (STI) process, such as first depositing an insulating layer (not shown) to cover the fin structures 108a and 108b, and then etching back the insulating layer to form Insulation structure 110. As such, two fin structures 108a and 108b can be formed on the substrate 100 and an insulating structure 110 can be formed between the fin structures 108a and 108b, respectively. In a particular embodiment, the fin structures 108a and 108b may have a width of about 20 nanometers (nm), and a height protruding beyond the insulating structure 110 may be about 30 nanometers (nm). Thereafter, the mask layer 102 on the fin structure can be removed to form a three-gate field effect transistor in a subsequent process. In other embodiments, the mask layer 102 can also be left to form a fin field effect transistor structure in a subsequent process.

In addition to the above-described example in which bulk Si is used as a substrate, in another embodiment of the present invention, a silicon-on-insulator (SOI) may be used as the substrate. As shown in FIG. 4, first, an insulating substrate 200 is provided, which comprises a substrate 202, a bottom oxide layer 204 on the substrate 202, and a tantalum layer 206 on the bottom oxide layer 204. The tantalum layer 206 is a single crystal germanium layer for forming a level of each semiconductor element. Next, as shown in FIG. 5, the aforementioned mask layer is formed to pattern the tantalum layer 206 to form the fin structures 208a and 208b, and a portion of the bottom oxide layer 204 is exposed. In this embodiment, the second fin structures 208a and 208b are formed on an insulating structure (ie, the bottom oxide layer 204), so that the subsequently fabricated gate elements are well insulated from each other, thereby eliminating the above. Shallow trench isolation (STI) process. The method of patterning the enamel layer 206 has been described in detail in the foregoing embodiments, and will not be further described herein.

As for the two embodiments in which the tantalum substrate and the covered insulating substrate are respectively used as the substrate, as shown in FIG. 1, the insulating structure 110 formed by the tantalum substrate is only located in each fin structure (such as 108a and 108b). Between the bottom oxide layer 204 formed by the insulating insulating substrate 200, as shown in Fig. 5, is located directly below the fin structures (e.g., 208a and 208b). However, the difference between the two does not affect the subsequent semiconductor process of the present invention.

In the following process, the germanium substrate is still taken as an example for illustration. As shown in FIG. 6, a gate structure 112 is formed on a portion of the insulating structure 110 and a portion of the fin structures 108a and 108b. The gate structure 112 spans a plurality of fin structures, thereby forming a non-planarized gate element. The process of forming the gate structure 112 may include forming a gate dielectric layer (such as SiO) on portions of the insulating structure 110 and portions of the fin structures 108a and 108b through deposition, chemical mechanical polishing (CMP), and patterning. ₂ and/or a high dielectric constant high-k material 114, a gate electrode 116 is formed over the gate dielectric layer 114, and a cap layer 118 is formed over the gate electrode 116. The above-mentioned methods for forming the material layers are all well-known techniques in the art, and thus will not be further described herein.

In the present invention, the gate structure 112 undergoes a pullback process in subsequent processes to reduce its critical dimension (CD), and may also perform a replacement metal after the gate device is fabricated. The gate process replaces the gate electrode 116 with at least one work function metal and at least one low resistivity metal material. In this case, in the above steps, a gate first process is taken as an example, and the gate electrode 116 may be made of a polysilicon (poly-Si), a metal telluride or a metal, and a rear gate ( In the case of gate last), poly-Si, SiN or SiNO, SiCN, or U.S. Applied Materials can be used. An advanced pattern film (APF) is used to prepare a dummy gate. In addition, the corresponding cap layer 118 may be made of material such as tantalum nitride (SiN) or yttrium oxide (SiO ₂ ). The above-described reduction process and selective replacement metal gate process will be described in detail in the embodiments to be described later.

Following the above steps, after the fabrication of the gate structure 112 is completed, as shown in FIG. 7, an epitaxial process E2 is performed to form epitaxial structures 120a and 120b on the surface of the enamel material exposed around the gate structure 112. The top surface of the gate electrode 116 is higher than the top surface of the epitaxial structures 120a and 120b. At this stage, the epitaxial structures 120a and 120b are formed on the surfaces of the fin structures 108a and 108b that are not covered by the gate structure 112. The function of the epitaxial structures 120a and 120b is to increase the total volume and total surface area of the fin structures 108a and 108b as source/drain regions, and to promote the subsequent formation of titanium (Ti), cobalt (Co), and nickel ( Ni) The genus layer more readily conforms completely over the surface of the epitaxial structures 120a and 120b for a self-aligned metal salicide process. The materials of the epitaxial structures 120a and 120b may depend on the electrical properties of the multi-gate field effect transistor (such as PMOS or NMOS), which may be a germanium epitaxial layer (Si-Ge) or a germanium carbon epitaxy. Layer (SiC), or a group III-V compound in the periodic table of the elements.

In another embodiment of the invention, the epitaxial structures 120a and 120b on the fin structures 108a and 108b can act as stressors to create strained helium channels to increase the mobility of electron clusters and electron bunches. In this embodiment, as shown in FIG. 8, an etching process E3 is performed to etch a portion of the fin structures 108a and 108b on both sides of the gate 112. The etching process E3 is characterized in that it is due to the fins. The crystal faces of the structures 108a and 108b have different etch rate characteristics, and a groove R is etched on the sidewalls of the fin structures 108a and 108b, respectively. The etching process E3 may include a dry etching process and a wet etching process or only a wet etching process. As in one embodiment, the wet etch process includes etching with an etchant containing ammonia, hydrogen peroxide, and water. Alternatively, the etchant may include an ammonia etchant, a methylammonium hydroxide etchant, a hydroxide etchant, or an ethylene diamine catechol etchant.

According to the above embodiment, after the fin structures 108a and 108b are etched and the recesses R are formed, as shown in FIG. 9, an epitaxial process E4 is performed to conformally form a hexagonal cross-sectional shape in the recess R. Epitaxial structures 120a and 120b. Depending on the electrical properties of the multi-gate field effect transistor, the epitaxial structures 120a and 120b may comprise a germanium epitaxial layer (Si-Ge) suitable for use in a PMOS transistor, or the epitaxial structures 120a and 120b may comprise One carbon epitaxial layer (Si-C), suitable for In an NMOS transistor. The formed epitaxial structures 120a and 120b have different lattice constants from the fin structures 108a and 108b (usually germanium materials), so that the lattice structures of the fin structures 108a and 108b under the gate structure 112 are stressed. In addition, a strain enthalpy channel is generated to achieve an effect of improving mobility.

It should be noted that in the embodiment in which the gate electrode 116 is made of a general polysilicon material, in order to prevent the epitaxial structure 120 in the epitaxial process E2 or E4 from growing on the gate structure 112, the gate structure 112 and the fin structure 108 are bridged. The gate electrode 116 of the polysilicon is first subjected to a gate pre-pullback process before performing the epitaxial process. The process can include oxidizing or nitriding the gate structure 112 to form an oxide layer (not shown) or a nitride layer (not shown) on the exposed side of the gate electrode 116. Thus, in the subsequent epitaxial process E2 or E4, the epitaxial layer will not grow on the gate electrode 116 of the polysilicon material to avoid bridging the gate structure 112 and the fin structure 108.

After the fin structure and the epitaxial structure are completed, the following embodiment will be based on the embodiment shown in Fig. 7, and the steps of the method of the present invention will be shown in a sectional view to make it easier for the reader. The invention is fully understood. Figure 10 is a cross-sectional view taken along line A-A' of Figure 7, which illustrates a non-planarized semiconductor structure in accordance with an embodiment of the present invention, comprising: a fin structure 108, a gate structure 112, disposed on the fin structure 108, the gate structure 112 includes a cap layer 118, a gate electrode 116, and a gate oxide layer 114 and the like, and an epitaxial structure 120, respectively covering the fins on both sides of the gate structure 112 On the structure 108.

In the embodiment of the present invention, as shown in FIG. 10, an ion implantation process E5 is performed after the epitaxial structure 120 is formed to be in the epitaxial structure 120 and the fins. Appropriate dopants are implanted in structure 108 such that a predetermined source/drain region 122a/122b can be formed in fin structure 108. The dopants implanted will depend on the type of semiconductor. Taking NMOS transistors as an example, the dopants implanted in the source/drain regions 122a/122b are n-type dopants such as phosphorus (P) and arsenic (As). quality. Taking a PMOS transistor as an example, the dopant implanted in the source/drain regions 122a/122b is a P-type dopant such as boron (B).

After the source/drain regions 122a/122b are formed, and then referring to FIG. 11, in order to increase the speed of the gate elements, a gate pull back E6 is performed in the invention to reduce the line of the gate structure 112. width. The gate reduction process E6 can perform a wet etch process to etch the exposed sidewalls of the gate structure 112, reducing the overall gate structure in width. For example, when the dummy gate gate electrode is made of poly-Si, SiN or SiON, SiCN, or US applications When the material company provides an advanced pattern film (APF), it can use diluted potassium hydride, HF/EG (ethylene glycol) mixed acid or low temperature phosphoric acid (H ₃ PO). ₄ ), or etched by means of oxygen plasma (O ₂ plasma). Due to the protection of the cap layer 118, the gate reduction process E6 only etches the sidewalls of the gate structure 112 without damaging the epitaxial structure 120 or reducing the height of the gate structure 112. The gate reduction process E6 not only makes the gate structure 112 have a smaller line width between the epitaxial structures 120 on both sides, but also separates the gate structure 112 from the epitaxial structures 120 on both sides, and exposes the bottom fins. Structure 108, in turn, forms a recess 126 structure.

After the gate reduction process E6, then please refer to Figure 12, an ion cloth The implant process E7 is applied to implant dopants in the exposed fin structure 108 to form a lightly doped drain (LDD) 128 on either side of the gate electrode 116. With the fabrication of the source/drain regions 122a/122b described above, the dopants implanted will depend on the type of semiconductor, which may be implanted with n-type dopants such as phosphorus (P) and arsenic (As) in a lightly doped manner. (for NMOS), or P-type dopant (for NMOS) such as boron (B). For the present invention, since the gap structure is not formed on the gate structure 112 at this stage, and it is a reduced gate structure, it can be selectively matched with an oblique ion implantation process, so the dopant will not be Blocked by the spacers can be implanted directly into the underlying fin structure 108, which will help to more accurately and efficiently control the doping concentration and doping pattern of the formed lightly doped drain region 128.

In a further embodiment, after the lightly doped drain region 128 is formed, a metal salicide process can be performed to form a metal telluride 124 on the surface of the epitaxial structure 120, wherein the metal germanide process can include the former Cleaning processes, metal deposition processes, annealing processes, selective etching processes, and test processes, which are well known in the art, are not described here. Alternatively, the metal germanide process described above may also be performed after the subsequent replacement metal gate process is completed and the contact holes are dug.

In the foregoing embodiment, after forming the lightly doped drain region 128, then, as shown in Fig. 13, a layer of material 130 is blanketed over the entire substrate surface as a source of material for the subsequent spacer forming step. In particular, in a preferred embodiment of the present invention, the material layer 130 can be spin-coated (SOG) or flowable CVD (FCVD). Formed. Furthermore, these processes can use a low dielectric constant (low-K) material to form a material layer 130, such as a polysiloxane. In a further embodiment of the present invention, a spacer layer (not shown) such as Si3N4, SiON, SiCN or the like may be formed on the surface of the substrate before forming the material layer 130, which will help to make the subsequent material layer. 130 is more effective to adhere to the base surface, improving the overall reliability of the gate components.

Next, referring to FIG. 14, after the material layer 130 is formed, an etching process E8 is performed to etch the material layer 130, and a spacer 132 structure is formed on the sidewalls of the gate structure 112 and the epitaxial structure 120. The etching process E8 may include both an etch back process of the material layer 130 and a dry etching process for forming the spacers 132. The etchback process etches the thickness of the previously deposited material layer 130 to a predetermined value, and then performs the dry etching process to etch the remaining material layer 130 to form the spacer 132 structure. It should be noted that in the preferred embodiment, the spacers 132 formed will fill the recess 126 between the gate structure 112 and the epitaxial structure 120 on the fin structure and the fin structures 108. The gaps between the gaps 132 and the gaps 132 may have two portions 132a, and the respective portions 132a are respectively filled in the respective grooves 126, and the top surfaces of the portions 132a are respectively flush with the top surface of the bordering epitaxial structure 120 or slightly low.

Referring next to Figure 15, a schematic perspective view of a gate element formed in accordance with the process of the present invention is depicted. As shown in the figure, for the final structure formed in this embodiment, the sidewalls of the gate structure 112 may not be completely covered with the spacers 132 due to the etching relationship, and only below the top surface of the epitaxial structure 120. The height has a gap wall 132 present and fills the gap 132 in the recess 126 Will be flush with the surface of the epitaxial structure 120.

In combination with the formation of the spacers described above, it is possible for the present invention to use a spin-on glass process or a flow chemical vapor deposition process to create a concept of spacers using a low dielectric constant material. Forming the spacer structure with a low dielectric constant material can effectively reduce the generation of parasitic capacitance, and since the above process has a better filling rate, it has a better filling effect on the recessed structure, so the gap formed later The wall 132 can be completely filled into the recess 126 between the gate structure 112 and the epitaxial structure 120, which is a relatively advantageous manufacturing method.

For the purposes of the present invention, the method of the invention is equally applicable to the fabrication of planarized semiconductors. In the following embodiments, the flow of steps of the planarization semiconductor process of the present invention will be described with reference to Figs. Referring first to Figure 16, a substrate 300 will be provided first as a basis for the overall semiconductor structure. The substrate 300 may include, but is not limited to, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on insulator. -insulator, SOI) and other substrates. An NMOS region and a PMOS region may be defined in advance on the substrate 300, and corresponding P well and N well structures have been formed. Then, a patterned gate structure 302 is formed on the substrate 300. The process of forming the gate structure 302 may include: sequentially forming a gate oxide layer 304, a gate electrode 306, and a cap layer 308 on the substrate 300. The layer structure is followed by patterning the cap layer 308 and etching with the patterned cap layer 308 as a mask to form the patterned gate electrode 306 and the gate oxide layer 304. The method for forming the gate structure 302 described above is a well-known technique in the art, and thus will not be further described herein.

In the present invention, the gate structure 302 undergoes a pullback process in subsequent processes to reduce its critical dimension (CD), and may also perform a replacement metal after the gate device is fabricated. The gate process replaces the gate electrode with at least one work function and at least one low resistivity metal material. In this regard, in the above steps, the gate first process is taken as an example, and the gate electrode 306 may be made of a polysilicon material such as poly-Si, metal telluride or metal, and for the rear gate ( In the case of gate last), poly-Si, SiN or SiNO, SiCN, or U.S. Applied Materials can be used. An advanced pattern film (APF) is used to prepare a dummy gate. In addition, the cap layer 308 corresponding thereto may be made of material such as tantalum nitride (SiN) or yttrium oxide (SiO ₂ ). The above-described reduction process and replacement metal gate process will be described in detail in the embodiments to be described later.

After defining the pattern of the gate structure 302, as shown in FIG. 17, an etching process E9 is performed in the process to form a recess 310 in the substrate 300 for the formation of a subsequent epitaxial structure. The etching process E9 is selective to the substrate 300, and may include a first dry etching process and a first wet etching process, wherein the first dry etching process is mainly down etching, which may be performed using sulfur hexafluoride. The main (SF ₆ -base) etchant or an etchant based on nitrogen trifluoride (NF ₃ -base). The first wet etching process includes a downward etch and a side etch, so that a feature of the concave surface 310a recessed toward the gate structure 302 is formed in the substrate 300.

It should be noted that the cross-sectional structure of the above-mentioned FIG. 17 is similar to the structure shown in the previous FIG. 8 (the regrowth epitaxial structure 120 after etching the fin structure 108), so that the steps of FIG. 16 can also be used as the eighth step. The various process steps following the structure shown in the figure.

In the next process, please refer to FIG. 18, in which a selective epitaxial process (SEG) is used to grow the epitaxial structure 312 in the groove 310 formed. The epitaxial structure 312 serves as a stressor source for the strained helium channel. In this embodiment, the material of the epitaxial structure 312 may be germanium (SiGe for PMOS transistors) or tantalum carbide (SiC for NMOS transistors). That is, it will stress the adjacent sputum channel region 300a, thereby achieving the effect of increasing the carrier mobility.

In the embodiment of the present invention, referring to FIG. 18, an ion implantation process E10 is applied to the epitaxial structure 312 formed to form an N-type dopant (such as phosphorus, arsenic or antimony) and a P-type dopant. (such as boron, boron difluoride) and mixed with other common dopants (such as carbon, nitrogen, fluorine, antimony, antimony) are respectively implanted into the corresponding NMOS or PMOS epitaxial structure 312 to be on the side of the gate structure 302 The source/drain regions 314a/314b are defined in the edge epitaxial structure 312 to complete the overall crystal structure.

Next, referring to FIG. 19, similarly, in order to increase the speed of the gate element after the source/drain regions 314a/314b are formed, a gate reduction process E11 is performed in the invention to reduce the line width of the gate structure 302. . The gate reduction process E11 may perform a wet etch process to etch the sidewalls of the gate structure 302 such that the entire gate structure is reduced in width. Depending on the material of the gate electrode 306, the etching solution used may include diluted potassium hydroxide (diluted KOH), HF/EG (ethylene glycol) mixed acid, low-temperature phosphoric acid (H ₃ PO ₄ ), or oxygen. The way of plasma (O ₂ plasma) is this. Due to the protection of the cap layer 308, the gate reduction process E11 only etches the sidewalls of the gate structure 302 without damaging the epitaxial structure 312 or reducing the height of the gate structure 302. The gate reduction process E11 causes the gate structure 302 to have a smaller line width between the epitaxial structures 312 on both sides, thereby exposing a portion of the lower substrate 300b.

Similarly, in the embodiment in which the gate electrode 306 is made of a general polysilicon material, in order to prevent the epitaxial structure 312 from growing on the gate structure 302 during the epitaxial process, the gate structure 302 and the substrate 300 are bridged. The gate electrode 306 first performs a gate pre-shrinking process before performing the epitaxial process. The process can include oxidizing or nitriding the gate structure 302 to form an oxide or nitride layer (not shown) on the exposed surface of the gate electrode 306. Thus, in the subsequent epitaxial process, the epitaxial structure of the gate electrode 306 of the polysilicon material will not grow, thereby preventing the gate structure 302 from bridging with the substrate 300.

After the gate reduction process E11, and then referring to FIG. 20, an ion implantation process E12 is performed to implant dopants in the exposed substrate 300b to form lightly doped germanium on both sides of the gate structure 302. Polar Region (LDD) 318. With the fabrication of the source/drain regions 314a/314b described above, the dopants implanted will depend on the type of semiconductor, which may be implanted with n-type dopants such as phosphorus (P) and arsenic (As) in a lightly doped manner. (for NMOS), or P-type dopant (for NMOS) such as boron (B). For the present invention, since the barrier structure is not formed on the gate structure 302 at this stage, and It is a reduced gate structure, and can be selectively matched with a bevel ion implantation process, so that the dopant will not be blocked by the spacer and can be directly implanted into the underlying substrate 300b, which will help The doping concentration and doping pattern of the formed lightly doped drain region 318 are controlled more accurately and efficiently.

After forming the lightly doped drain region 318, next, as shown in Fig. 21, a spacer 320 structure is formed on the sidewall of the gate structure 302. The spacer 320 can be formed by depositing a material layer and etching it, which has been described in detail in the foregoing embodiments, and will not be further described herein.

In a further embodiment, after the spacers 320 are formed, a metal germanide process can be performed to form metal germanide 316 on the surface of the source/drain regions 314a/314b, or the metal germanide process described above may be left After the subsequent replacement metal gate process is completed, the contact hole is excavated. The metal telluride process may include a pre-cleaning process, a metal deposition process, an annealing process, a selective etching process, and a test process. These processes are well known in the art, and thus are not described herein. In this way, the complete gate element is completed.

In the following embodiments, the subsequent selective metal gate process in the semiconductor process of the present invention, that is, the step of integrating into the gate last, will be described with reference to FIGS. 22-25. The use of an alternative metal gate process will avoid the source/drain ultra-shallow junction activation tempering and the formation of high-heat budget processes such as metal telluride, and has a wide selection of materials, which is a considerable advantage. It should be noted that the replacement metal gate process can continue any of the aforementioned non-planarization and planarization semiconductor processes of the present invention, and there is no process. Compatibility issues. Figures 22-25 are based on the structure completed in Figure 14 above, where some components may differ but do not affect the overall process.

Referring to FIG. 22, a semiconductor device structure completed in the embodiment shown in FIG. 14 is illustrated, which includes a main portion such as a gate structure 112, a fin structure 108, and an epitaxial structure 120. In the first method, a deposition process is first performed to form a contact etch stop layer (CESL) (not shown) on the substrate surface, and an inter-layer dielectric (ILD) 134 is formed. The interlayer dielectric layer 134 blankets the entire substrate surface (including the entire gate structure 112 and the epitaxial structure 120 region) and extends beyond the gate structure 112 by a predetermined thickness.

Then see Figure 23. After the interlayer dielectric layer 134 is formed, a portion of the interlayer dielectric layer 134 and the cap layer 118 are removed by a planarization process E13 until the gate electrode 116 in the gate structure 112 is exposed. Gate electrode 116 is in this embodiment a dummy gate that will be removed in subsequent processes.

After the planarization process E13, as shown in FIG. 24, an etching process E14 is performed to etch the exposed gate electrode 116. The gate electrode 116 is removed at this step and the gate dielectric layer 114 underneath is exposed. This process forms a gate trench 136 for subsequent replacement of the gate metal material.

It should be noted that the preferred embodiment can be integrated with a pre-high-k first process. In such a process, the gate dielectric layer 114 includes a high dielectric constant (high-k) gate dielectric layer, which may be a metal oxide layer, such as a rare earth metal oxide layer. . The gate dielectric layer 114 is formed in the fin structure 108 prior to patterning of the gate structure 112 and is patterned along with the gate structure 112. The high dielectric constant gate dielectric layer 114 may be selected from hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (hafnium silicon oxynitride, HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ) Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), antimony Strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti ₁ -xO ₃ , PZT) and barium strontium titanate (Ba _{x )} A group consisting of Sr ₁ -xTiO ₃ , BST). In this embodiment, a gate barrier layer (such as TiN for titanium nitride) and an etch stop layer (such as tantalum nitride TaN) may be formed on the gate dielectric layer 114 in the gate trench 136 (not shown). Show), no more details here.

It is also worth noting that the preferred embodiment can be integrated with a post-high-K last process. In this process, the high dielectric constant gate dielectric layer will not be formed prior to patterning of the gate structure 112, but will be formed over the entire substrate surface after the dummy gate is removed to form the gate trench 136. Upper (including the surface of gate trench 136), as shown by gate dielectric layer 138 in FIG. Similarly, the formed high dielectric constant gate dielectric layer 138 may also be formed with a bottom barrier layer (such as titanium nitride TiN, not shown) and an etch stop layer (eg, Tantalum nitride material TaN, not shown), will not be described again here.

Referring to FIG. 25, after forming the gate dielectric layer 138, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer is performed. An atomic layer deposition (ALD) is formed to form a work function metal layer 140 in the gate trench 136. Depending on the type of gate element, the work function metal layer 140 can be a p-type work function metal layer having a p-type conductivity type, such as titanium nitride (TiN), titanium carbide (TiC), Tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), or aluminum titanium nitride (TiAlN), but is not limited thereto. Or an n-type work function metal layer having an n-type conductivity type, such as a titanium aluminide (TiAl) layer, a zirconium aluminide (ZrAl) layer, a tungsten aluminide (WAl) layer, aluminum A tantalum aluminide (TaAl) layer or a hafnium aluminide (HfAl) layer, but is not limited thereto. In addition, the work function metal layer 140 may be a single layer structure or a composite layer structure. For example, the work function metal layer 140 may simultaneously include a plurality of different work function metal layers, thereby optimally adjusting the electrical properties of the gate elements. .

After forming the success function metal layer 140, a top barrier layer (not shown) is selectively formed in the gate trench 136 to form a fill metal layer 142. The filling metal layer 142 is used to fill the gate trench 136 as a main body of the gate electrode, and may select a metal or metal oxide having excellent filling ability and lower resistivity, such as aluminum (Al), tungsten (W). , copper (Cu), titanium aluminide (TiAl) or Titanium alumina oxide (TiAlO), but is not limited thereto.

After the fabrication of the gate electrode is completed, finally, one or more planarization processes, such as a CMP process, are performed to remove the surface of the interlayer dielectric layer 134, the excess filler metal layer 142, and the work function metal layer 140. And the gate dielectric layer 138, and the fabrication of an alternative metal gate structure is completed. In addition, another embodiment of the present invention may completely remove the interlayer dielectric layer 134 and the contact hole etch stop layer (CESL) after completing the replacement metal gate structure, and then re-form the contact hole etch stop layer ( CESL) (not shown) and interlayer dielectric (ILD) (not shown) to ensure that the contact hole etch stop layer (CESL) provides complete and appropriate compression or tensile stress. It should be noted that the alternative metal gate process embodiments provided above are for illustrative purposes only, which merely highlights the basic steps in making the alternative metal gate components, possibly omitting some cumbersome steps or It is a necessary component, but does not affect the concept of the semiconductor process of the present invention that can be combined with an alternative metal gate process.

In combination with the method and various technical features provided by the embodiments of the present invention, the present invention also provides a novel non-planarized semiconductor structure having the same according to the above related embodiments of the present invention. The technical features formed by the process method are characterized in that, as shown in FIG. 9 and FIG. 14 , a substrate 100 is included: at least one fin structure 108 is disposed on the substrate; and a gate structure 112 covers the On a portion of the fin structure 108 and a portion of the substrate 100; a plurality of epitaxial structures 120 overlying the fin structures 108 on both sides of the gate structure 112 and separated from the gate structure 112 for a gate structure 112, an epitaxial structure 120, and a fin structure A recess 126 is defined between the 108; a source 122a and a drain 122b are formed in each of the fin structures 108 and the epitaxial structures 120 on both sides of the gate structure 112; the lightly doped bungee region 128 Formed in a fin structure 108 between each of the epitaxial structures 120 on both sides of the gate structure 112 and the gate; and a spacer 132 formed on the sidewalls of the gate structure 112 and each of the epitaxial structures 120, The spacer 132 filled in the recess 126 is flush with the top surface of the epitaxial structure 120.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Base

132‧‧‧ spacers

102‧‧‧mask layer

132a‧‧‧ parts

104‧‧‧Mat oxide layer

134‧‧‧Interlayer dielectric layer

106‧‧‧ nitride layer

136‧‧ ‧ gate ditches

108/108a/108b‧‧‧Fin structure

138‧‧‧ gate dielectric layer

110‧‧‧Insulation structure

140‧‧‧Work function metal layer

112‧‧‧ gate structure

142‧‧‧Filled metal layer

114‧‧‧ gate dielectric layer

200‧‧‧矽Insulation base

116‧‧‧gate electrode

202‧‧‧Base

118‧‧‧ cover

204‧‧‧ bottom oxide layer

120/120a/120b‧‧‧ epitaxial structure

206‧‧‧The enamel layer

122a/122b‧‧‧Source/Bungee Zone

208a/208b‧‧‧Fin structure

124‧‧‧Metal Telluride

300/300b‧‧‧Base

126‧‧‧ Groove

300a‧‧‧矽Channel area

128‧‧‧Lightly doped bungee zone

302‧‧‧ gate structure

130‧‧‧Material layer

304‧‧‧ gate dielectric layer

306‧‧‧gate electrode

310‧‧‧ Groove

308‧‧‧ cover

310a‧‧‧ concave

312‧‧‧ epitaxial structure

314a/314b‧‧‧ source/bungee area

316‧‧‧Metal Telluride

318‧‧‧Lightly doped bungee zone

320‧‧‧ spacer

E1‧‧‧ etching lithography process

E2‧‧‧Ethylene Process

E3‧‧‧ etching process

E4‧‧‧Ethylene Process

E5‧‧‧Ion implantation process

E6‧‧‧gate reduction process

E7‧‧‧Ion implantation process

E8‧‧‧ etching process

E9‧‧‧ etching process

E10‧‧‧Ion implantation process

E11‧‧‧ gate reduction process

E12‧‧‧Ion implantation process

E13‧‧‧ Flattening process

E14‧‧‧ etching process

The present specification contains the drawings and constitutes a part of the specification in the specification, and the reader will further understand the embodiments of the invention. The drawings depict some embodiments of the invention and, together with the description herein. In the drawings: FIGS. 1-14 are schematic cross-sectional views showing a non-planarized semiconductor process according to an embodiment of the present invention; and FIG. 15 is a perspective view showing a gate element formed by the process according to the present invention. 16-21 are schematic cross-sectional views showing a planarization semiconductor process in accordance with another embodiment of the present invention; and FIGS. 22-25 illustrate an alternative metal in a further embodiment of the present invention; Schematic diagram of the gate process.

It should be noted that all the illustrations in this specification are of the nature of the legend. For the sake of clarity and convenience of illustration, the various components in the drawings may be exaggerated or reduced in size and proportion. The same reference numbers are used in the drawings to refer to the corresponding or similar features in the modified or different embodiments.

108. . . Fin structure

112. . . Gate structure

114. . . Gate dielectric layer

116. . . Gate electrode

118. . . Cover

120. . . Epitaxial structure

122a/122b. . . Source/bungee area

124. . . Metal telluride

128. . . Lightly doped bungee zone

132. . . Clearance wall

132a. . . Part

E8. . . Etching process

Claims (35)

A non-planarized semiconductor process, the method comprising: providing a substrate; forming at least one fin structure on the substrate; forming a gate covering a portion of the fin structures; forming a plurality of epitaxial structures covering the gate The fin structures on the two sides of the pole; the fin structures on both sides of the gate and the epitaxial structures respectively form a source and a drain; performing a gate reduction process to reduce the gate a pole such that the gate is separated from the epitaxial structures on both sides of the gate; an ion implantation process is performed to the fin between the gate and the epitaxial structures on both sides of the gate Forming a lightly doped drain in each of the structures; and forming a spacer on the sidewall of the gate and the epitaxial structures. The non-planarized semiconductor process of claim 1, wherein the step of forming the spacer comprises: spin on glass (SOG) or flowable CVD (FCVD) Forming a spacer material layer; and etching the spacer material layer to form the spacers. The non-planarized semiconductor process of claim 2, wherein the spacer material layer comprises a polysiloxane low dielectric constant (low-K) material. The non-planarized semiconductor process of claim 2, further comprising forming a liner layer on the substrate before forming the spacers, the spacer layer being made of Si ₃ N ₄ , SiON or SiCN. The non-planarized semiconductor process of claim 1, wherein the substrate comprises a bulk silicon or a silicon-on-insulator (SOI). The non-planarized semiconductor process of claim 5, wherein the step of forming at least one fin structure on the substrate comprises: forming a mask layer on the substrate; and patterning the mask layer and The patterned mask layer is etched by the mask to form the fin structures. The non-planarized semiconductor process of claim 6, wherein the mask layer comprises a pad oxide layer and a nitride layer. The non-planarized semiconductor process of claim 5, wherein the overlying insulating substrate comprises: a substrate; a bottom oxide layer on the substrate; and a germanium layer on the bottom oxide layer. The non-planarized semiconductor process of claim 8, wherein the step of forming at least one fin structure on the substrate comprises: The tantalum layer is patterned to form the fin structures and expose a portion of the bottom oxide layer between the fin structures. The non-planarized semiconductor process of claim 1, wherein the step of forming a plurality of epitaxial structures over the fin structures on both sides of the gate comprises: performing an etching process, etching the gate The fin structures on both sides form at least one recess in the fin structures; and an epitaxial process is performed to form the epitaxial structures in the recesses. The non-planarized semiconductor process of claim 1, wherein the gate material comprises poly-Si. The non-planarized semiconductor process of claim 11, further comprising performing a gate pre-pullback process to oxidize or nitride the gate before the step of forming the plurality of epitaxial structures. Extremely exposed side. The non-planarized semiconductor process of claim 11, wherein the step of performing a gate reduction process to reduce the gate comprises etching the gate with diluted potassium hydroxide (diluted KOH). The non-planarized semiconductor process of claim 1, wherein the gate material comprises tantalum nitride (SiN), bismuth oxynitride (SiON), tantalum carbonitride (SiCN), or advanced patterning. Advanced pattern film (APF). The non-planarized semiconductor process of claim 14, wherein the step of performing a gate reduction process to reduce the gate comprises etching the gate with a material selected from the group consisting of: HF/EG (E.g. Alcohol) mixed acid, low temperature phosphoric acid (H ₃ PO ₄ ) and oxygen plasma (O ₂ plasma). The non-planarized semiconductor process of claim 1, wherein the gate is a dummy gate, and after forming the spacers, further comprising performing a replacement metal gate process, replacing the metal electrode layer The gate. The non-planarized semiconductor process of claim 16, wherein the replacement metal gate process comprises the steps of: covering an entire dielectric layer over the entire substrate surface; performing a planarization process to remove the interlayer a dielectric layer until the dummy gate is exposed; an etching process is performed to remove the exposed dummy gate to form a gate trench; a work function metal layer is formed in the gate trench; and the gate is formed A filler metal layer is formed in the trench. The non-planarized semiconductor process of claim 17, wherein the replacement metal gate process is a high-k first process, and the step further comprises forming the gate A high dielectric constant layer is previously formed on the substrate. The non-planarized semiconductor process of claim 17, wherein the replacement metal gate process is a post-high-k last process, and the step further comprises forming the work function. A high dielectric constant layer is formed in the gate trench before the metal layer. For example, the non-planarized semiconductor process described in claim 1 of the patent scope, wherein The epitaxial structure comprises a tantalum epitaxial layer (Si-Ge) or a tantalum carbon epitaxial layer (Si-C). A planarization semiconductor process, the method comprising: providing a substrate; forming a gate on the substrate; forming an epitaxial structure; forming a source and a drain in the epitaxial structures on both sides of the gate Performing a gate reduction process to reduce the gate so that the gate is separated from the epitaxial structures on both sides of the gate; performing an ion implantation process after the gate reduction process to be located at the gate Forming a lightly doped drain in the substrate between the poles and the epitaxial structures on both sides of the gate; and forming a spacer on the sidewall of the gate. The planarization semiconductor process of claim 21, wherein the substrate comprises a bulk silicon or a silicon-on-insulator (SOI). The planarization semiconductor process of claim 21, wherein the material of the gate comprises poly-Si. The planarization semiconductor process of claim 23, further comprising performing a gate pre-pullback process to oxidize or nitride the gate before the step of forming the plurality of epitaxial structures. Exposed side. For example, the planarization semiconductor process described in claim 23, wherein The step of performing a gate reduction process to reduce the gate includes etching the gate with diluted potassium hydroxide (diluted KOH). The planarization semiconductor process of claim 21, wherein the gate material comprises tantalum nitride (SiN), bismuth oxynitride (SiON), tantalum carbonitride (SiCN), or an advanced patterned film. (advanced pattern film, APF). The planarizing semiconductor process of claim 26, wherein the step of reducing the gate by a gate reduction process comprises etching the gate with a material selected from the group consisting of: HF/EG (ethylene glycol) Mixed acid, low temperature phosphoric acid (H ₃ PO ₄ ) and oxygen plasma (O ₂ plasma). The planarization semiconductor process of claim 21, wherein the gate is a dummy gate, and after forming the spacer, further comprising performing an alternative metal gate process, replacing the gate with a metal electrode layer pole. The planarization semiconductor process of claim 28, wherein the replacement metal gate process comprises the steps of: covering an entire dielectric layer over the substrate; performing a planarization process to remove the interlayer dielectric Layering until the dummy gate is exposed; performing an etching process to remove the exposed dummy gate to form a gate trench; forming a work function metal layer in the gate trench; and in the gate trench A fill metal layer is formed. The planarization semiconductor process of claim 29, wherein the replacement metal gate process is a pre-high dielectric constant layer (high-K) First) the process, the step further comprising forming a high dielectric constant layer on the substrate before forming the gate. The planarization semiconductor process of claim 29, wherein the replacement metal gate process is a post-high-k last process, and the step further comprises forming the work function metal A high dielectric constant layer is formed in the gate trench before the layer. The planarization semiconductor process of claim 21, wherein the epitaxial structure comprises a germanium epitaxial layer (Si-Ge) or a germanium carbon epitaxial layer (Si-C). A non-planarized semiconductor structure includes: a substrate; at least one fin structure disposed on the substrate; a gate covering a portion of the fin structure and a portion of the substrate, such that the fin structure is defined a channel region overlapping the gate electrode and a source region and a drain region respectively located on opposite sides of the gate; a plurality of epitaxial structures covering the source region and the drain region of the fin structures Each of the epitaxial structures on the fin structure and the gate respectively have a recess, and a top surface of the gate is higher than a top surface of each of the epitaxial structures; and a spacer is formed at The gate electrode and the sidewalls of the epitaxial structures, wherein the spacer has two portions, each of which is filled in each of the grooves, and the top surface of each portion is respectively opposite to the top of each of the epitaxial structures The face is flush or slightly lower. The non-planarized semiconductor structure of claim 33, wherein the fin structure further comprises a lightly doped drain, formed between the channel region and the source/drain region, respectively. The non-planarized semiconductor structure according to claim 33, wherein the spacer is made of a polysiloxane low dielectric constant (low-K) material.