TWI630647B - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor element includes the following steps. A core structure and a first material layer are sequentially formed on the substrate. The top surface of the first material layer is lower than the top surface of the core structure. A second pattern is formed on the exposed surface of the core structure. A method of forming a second pattern includes forming a second material layer on an exposed surface of the core structure and a surface of the first material layer, and anisotropically etching the second material layer to form a second pattern. The first material layer is patterned with the second pattern as a mask to form a first pattern. The step of forming the second material layer and the step of anisotropic etching the second material layer are performed in the same etching chamber.

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same.

As the semiconductor element progresses toward a high degree of integration, the critical dimension (CD) of the semiconductor element is gradually shortened. To overcome the limitations of light source resolution in lithography processes, a self-aligned double patterning (SADP) approach has been developed to allow semiconductor components to have smaller critical dimensions.

The self-aligned double patterning method includes forming a mask material layer on a surface of a core structure in different cavities and anisotropic etching of the mask material layer to form a mask pattern on sidewalls of the core structure. . In general, the mask pattern fails to cover the top surface of the core structure and requires the use of two different cavities to form the mask pattern described above.

The present invention provides a method of fabricating a semiconductor device in which a mask pattern can be formed on a sidewall and a top of a core structure in a single etching chamber.

The present invention provides a semiconductor device having a mask pattern covering a sidewall and a top surface of the core structure.

The method of manufacturing a semiconductor device of the present invention includes the following steps. A core structure is formed on the substrate. A first material layer is formed on the substrate. The top surface of the first material layer is lower than the top surface of the core structure. A second pattern is formed on the exposed surface of the core structure. A method of forming a second pattern includes forming a second material layer on an exposed surface of the core structure and a surface of the first material layer, and anisotropically etching the second material layer to form a second pattern. The first material layer is patterned with the second pattern as a mask to form a first pattern. The step of forming the second material layer and the step of anisotropic etching the second material layer are performed in the same etching chamber.

In an embodiment of the invention, the step of forming the second material layer may use a power ranging from 300 W to 1500 W, and the operating pressure may range from 4 mTorr to 50 mTorr.

In an embodiment of the invention, the method of forming a second material layer may include introducing a deposition gas into the etching chamber, and the method of anisotropically etching the second material layer may include etching the gas. It is passed into the etching chamber described above.

In an embodiment of the invention, the forming the second material layer and the method of anisotropically etching the second material layer may include alternately introducing a deposition gas and an etching gas into the etching cavity.

In an embodiment of the invention, the forming the second material layer and the method of anisotropically etching the second material layer may include introducing a deposition gas into the etching cavity together with the etching gas.

In an embodiment of the invention, the method of forming a first material layer may include forming a material layer on a substrate, and then removing a portion of the material layer by etch back to form a first material layer. The step of removing a portion of the material layer can be performed in the etching chamber described above.

In an embodiment of the invention, the method of patterning the first material layer with the second pattern as a mask may include anisotropic etching and may be performed in the etching chamber described above.

In an embodiment of the invention, the first material layer may have a first thickness on a top surface of the core structure greater than a second thickness of the second material layer on a surface of the first material layer.

In an embodiment of the invention, the ratio of the first thickness to the second thickness may range from 3 to 20.

In an embodiment of the invention, the second pattern covers a sidewall and a top surface of the core structure exposed by the first pattern, and the second pattern has a pointed top.

A semiconductor component includes a core structure, a first pattern, and a second pattern. The core structure is disposed on the substrate. The first pattern is disposed on a sidewall of the core structure. The top surface of the first pattern is lower than the top surface of the core structure. The second pattern covers the sidewalls and top surface of the core structure exposed by the first pattern. The second pattern has a pointed top and the material of the first pattern is different from the material of the second pattern.

In an embodiment of the invention, the sidewall of the top of the second pattern may be a slope or a curved surface.

In an embodiment of the invention, the sidewall of the second pattern may be coplanar with the sidewall of the first pattern.

Based on the above, by forming the second material layer in the etching cavity, the thickness of the second material layer on the top surface of the core structure can be made larger than its thickness on the first material layer. In this way, the second pattern formed by the patterning of the second material layer can still cover the top surface of the core structure. Therefore, the damage of the core structure to the plasma can be avoided during the etching of the second material layer. In particular, the second pattern is formed to have a pointed top. Furthermore, the step of forming the second material layer and the step of anisotropically etching the second material layer can be performed in the same etching cavity. Therefore, the time for transferring the wafer between different cavities can be eliminated, and the process of the semiconductor device can be shortened.

The above described features and advantages of the invention will be apparent from the following description.

1 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. 2 to 8 are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention. The method of manufacturing the semiconductor element 10 (shown in Fig. 8) of the present embodiment includes the following steps.

Referring to FIG. 1 and FIG. 2, step S100 is performed to form a core structure 102 on the substrate 100. In some embodiments, substrate 100 can include a semiconductor substrate, a silicon on insulator (SOI) substrate. For example, the material of the semiconductor substrate may include a doped or undoped semiconductor material such as germanium, antimony, gallium arsenide, tantalum carbide, indium arsenide or indium phosphide, and the like. Additionally, the substrate 100 can be formed to have active and/or passive components. The active component can include a transistor, a diode, etc., and the passive component can include a resistor, a capacitor, an inductor, and the like. In some embodiments, the core structure 102 can be an insulating structure. The insulating structure includes at least one insulating layer. The material of the at least one insulating layer may include tantalum oxide, tantalum nitride or a combination thereof. In other embodiments, the core structure 102 can be a gate structure. For example, the gate structure can include a gate dielectric layer, a work function layer, a gate layer, and a spacer. In addition, the gate layer may include a floating gate and a control gate, and the gate structure may further include an inter-gate dielectric layer between the floating gate and the control gate.

Referring to FIG. 1 , FIG. 3 and FIG. 4 , step S102 is performed to form a first material layer 104 on the substrate 100 . The first material layer 104 is formed such that its top surface is lower than the top surface of the core structure 102. The material of the first material layer 104 may include polycrystalline germanium, a metal or a metal compound. The metal may comprise aluminum, copper, tungsten, titanium, tantalum or combinations thereof. The metal compound may include a metal nitride such as titanium nitride, tantalum nitride or tungsten nitride. Referring to FIG. 3, the method of forming the first material layer 104 includes first forming a material layer 103 on the substrate 100. Referring to FIG. 4, a portion of the material layer 103 is then removed by etch back to form the first material layer 104.

Referring to FIG. 1 , FIG. 5 and FIG. 6 , step S104 is performed to form a second pattern 106 on the exposed surface of the core structure 102 . Step S104 includes sub-step S104a and sub-step S104b as described below.

Referring to FIGS. 1 and 5, sub-step S104a is performed to form a second material layer 105 on the exposed surface of the core structure 102 and the surface of the first material layer 104. The material of the second material layer 105 may be different from the material of the first material layer 104. In some embodiments, the material of the second material layer 105 can include an insulating material. The insulating material may include an inorganic insulating material or an organic insulating material. For example, the inorganic insulating material may include tantalum oxide, tantalum nitride, or a combination thereof. The organic insulating material may include an organic hydrocarbon, a carbon oxyhydroxide, nitrogen, sulfur, halogen, or a combination thereof. The method of forming the second material layer 105 includes a chemical vapor deposition method. It should be noted that the method of forming the second material layer 105 of the present embodiment is to pass a deposition gas into an etching chamber for performing a chemical vapor deposition process. For example, the deposition gas may include organic hydrocarbons, carbon oxyhydroxides, chlorides, fluorides, tellurides, cerium chloride compounds, cerium fluoride compounds, cerium nitride compounds, oxygen, ozone, argon, helium. Gas, nitrogen, carbon monoxide, methane or a combination thereof. The etched cavity has higher power and lower operating pressure than the deposition cavity. For example, the step of forming the second material layer 105 (sub-step 104a) can range from 300 W to 1500 W, and the operating pressure can range from 4 mTorr to 50 mTorr. As such, the first thickness T1 of the formed second material layer 105 on the top surface of the core structure 102 may be greater than the second thickness T2 on the surface of the first material layer 104. In some embodiments, the ratio of the first thickness T1 to the second thickness T2 may range from 3 to 20. Moreover, in some embodiments, the area of the upper surface of the formed second material layer 105 on the top structure TP1 (shown in the dashed area of FIG. 5) on the core structure 102 may be greater than the area of the lower surface. In other words, the cross section of the top portion TP1 of the second material layer 105 can be approximated by a trapezoid, and the length of the upper base of the trapezoid is greater than the length of the lower base.

Referring to FIG. 1 and FIG. 6, sub-step S104b is performed to anisotropically etch the second material layer 105 to form a second pattern 106. The method of performing sub-step S104b includes passing an etching gas into the etching chamber for an anisotropic etching process. In particular, sub-step S104a and sub-step S104b are performed in the same etch chamber. Therefore, the time required for the wafer to transfer between different cavities can be eliminated, and the process time can be shortened. In sub-step S104b, the etching gas may include carbon tetrafluoride, trifluoromethane, difluoromethane, oxygen, argon, nitrogen, chlorine, hydrogen bromide, carbon monoxide, sulfur hexafluoride, nitrogen trifluoride, octafluorocarbon. Four carbon, octafluoropentacarbon, hexafluoride four carbon or a combination thereof. In some embodiments, the power to anisotropically etch the second material layer 105 (sub-step S104b) may be greater than the power to form the second material layer (sub-step S104a). Further, the operating pressure for the anisotropic etching of the second material layer 105 (sub-step S104b) may be less than the operating pressure for forming the second material layer (sub-step S104a). For example, the power of the anisotropic etch of the second material layer 105 may range from 300 W to 2000 W, and the operating pressure may range from 5 mTorr to 100 mTorr. As such, in sub-step S104b, a portion of the surface of the second material layer 105 covering the first material layer 104 is removed, and the remaining portion is partially removed to form the second pattern 106. Since the first thickness T1 of the second material layer 105 on the top surface of the core structure 102 may be greater than the second thickness T2 thereof on the surface of the first material layer 104, the second material layer 105 is patterned. The second pattern 106 can still cover the top surface of the core structure 102. In particular, the second pattern 106 covers the sidewalls and top surface of the core structure 102 that are exposed by the first material layer 104. In other words, during etching of the second material layer 105, the core structure 102 can be prevented from being damaged by the plasma. Further, the second pattern 106 is formed to have a pointed top portion TP2. In some embodiments, the sidewalls of the top TP2 of the second pattern 106 are beveled.

FIG. 6A is a schematic cross-sectional view showing a second pattern according to another embodiment of the invention. Referring to FIG. 6A, in other embodiments, the sidewall of the top TP3 of the second pattern 106a may also be formed as a curved surface. In addition, the same components in FIG. 6A and FIG. 6 are denoted by the same reference numerals and will not be described again.

Referring again to FIGS. 1 , 5 , and 6 , in some embodiments, a method of forming a second material layer 105 and anisotropically etching the second material layer 105 to form the second pattern 106 includes depositing a gas with The etching gas alternately passes into the same etching chamber. In other words, sub-step S104a and sub-step S104b can be alternately performed in the same etch chamber. In such embodiments, starting with sub-step S104a, and ending at sub-step S104b. In addition, the number of repetitions of the sub-step S104a and the sub-step S104b can be adjusted according to the process requirements, and the present invention is not limited thereto. In other embodiments, a method of forming the second material layer 105 and anisotropically etching the second material layer 105 to form the second pattern 106 includes passing a deposition gas into the same etch chamber along with the etching gas. In other words, in such embodiments, sub-step S104a and sub-step S104b may be performed together in the same etch chamber.

6B is a cross-sectional view of a second pattern and a first material layer, in accordance with yet another embodiment of the present invention. Referring to FIG. 6B, in still other embodiments, the process of forming the second pattern 106b can be accompanied by removing portions of the first material layer 104b such that they have a substantially V-shaped surface. As such, the interface between the second pattern 106b and the first material layer 104b can be formed as a slope. In particular, the angle θ between the extending direction of the interface of the second pattern 106b and the first material layer 104b and the extending direction of the surface of the substrate 100 may be in the range of 20° to 35°. In addition, the same components in FIG. 6B and FIG. 6 are denoted by the same reference numerals and will not be described again.

Referring to FIG. 1 and FIG. 7 , step S106 is performed to pattern the first material layer 104 with the second pattern 106 as a mask to form the first pattern 108 . The method of patterning the first material layer 104 can include anisotropic etching. Moreover, the sidewalls of the first pattern 108 can be formed to be coplanar with the sidewalls of the second pattern 106. In some embodiments, the etching cavity used in step S102, the etching cavity used in step S104, and the etching cavity used in step S106 may be the same etching cavity. In this way, the material layer 103, the second material layer 105, and the first material layer 104 can be etched separately by selecting different etching gases according to different etching targets. In other embodiments, at least one of the etch chamber used in step S102, the etch chamber used in step S104, and the etch chamber used in step S106 may be different from the rest.

Referring to FIG. 1 and FIG. 8, step S108 is selectively performed to form a third material layer 110 on the substrate 100. The third material layer 110 is formed to cover the substrate 100, the second pattern 106, and the first pattern 108. The material of the third material layer 110, the material of the first pattern 108, and the material of the second pattern 106 may be different from each other. The material of the third material layer 110 may include hafnium oxide, tantalum nitride, or a combination thereof. Thus far, the fabrication of the semiconductor element 10 of the present embodiment has been completed.

Next, the structure of the semiconductor element 10 of the present embodiment will be described with reference to FIG.

Referring to FIG. 8 , the semiconductor component 10 includes a core structure 102 , a first pattern 108 , and a second pattern 106 . The core structure 102 is disposed on the substrate 100. The first pattern 108 is disposed on a sidewall of the core structure 102. The top surface of the first pattern 108 is lower than the top surface of the core structure 102. The second pattern 106 covers the sidewalls and top surface of the core structure 102 that are exposed by the first pattern 108. The second pattern 106 has a pointed top TP2. The material of the first pattern 108 is different from the material of the second pattern 106. Additionally, the sidewalls of the second pattern 106 can be coplanar with the sidewalls of the first pattern 108. The semiconductor component 10 may further include a third material layer 110. The third material layer 110 covers the substrate 100, the second pattern 106, and the first pattern 108.

In some embodiments, the sidewalls of the top TP2 of the second pattern 108 are beveled. In other embodiments (please refer to FIG. 6A), the sidewalls of the top TP3 of the second pattern 108a may also be curved. Moreover, in some embodiments (please refer to FIG. 6B), the interface of the second pattern 106b and the first material layer 104b may be a bevel. The angle θ between the extending direction of the slope and the surface of the substrate 100 may be in the range of 20° to 35°.

In summary, by forming a second material layer in the etched cavity, the thickness of the second material layer on the top surface of the core structure can be greater than its thickness on the first material layer. In this way, the second pattern formed by the patterning of the second material layer can still cover the top surface of the core structure. Therefore, the damage of the core structure to the plasma can be avoided during the etching of the second material layer. In particular, the second pattern is formed to have a pointed top. Furthermore, the step of forming the second material layer and the step of anisotropically etching the second material layer can be performed in the same etching cavity. Therefore, the time for transferring the wafer between different cavities can be eliminated, and the process of the semiconductor device can be shortened.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Semiconductor components

100‧‧‧Base

102‧‧‧core structure

103‧‧‧Material layer

104, 104b‧‧‧ first material layer

105‧‧‧Second material layer

106, 106a, 106b‧‧‧ second pattern

108‧‧‧ first pattern

110‧‧‧ third material layer

S100, S102, S104, S106, S108‧‧‧ steps

Sub-steps S104a, S104b‧‧

T1‧‧‧first thickness

T2‧‧‧second thickness

TP1, TP2, TP3‧‧‧ top

Θ‧‧‧ angle

1 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. 2 to 8 are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention. FIG. 6A is a schematic cross-sectional view showing a second pattern according to another embodiment of the invention. 6B is a cross-sectional view of a second pattern and a first material layer, in accordance with yet another embodiment of the present invention.

Claims (9)

A method of fabricating a semiconductor device, comprising: forming a core structure on a substrate; forming a first material layer on the substrate, wherein a top surface of the first material layer is lower than a top surface of the core structure; The exposed surface of the core structure forms a second pattern, wherein the method of forming the second pattern includes forming a second material layer on the exposed surface of the core structure and the surface of the first material layer And anisotropically etching the second material layer to form the second pattern; and patterning the first material layer with the second pattern as a mask to form a first pattern, wherein The step of forming the second material layer and the step of anisotropically etching the second material layer are performed in the same etching chamber. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the second material layer uses a power ranging from 300 W to 1500 W, and an operating pressure ranging from 4 mTorr to 50 mTorr. The method of manufacturing a semiconductor device according to claim 1, wherein the method of forming the second material layer comprises: introducing a deposition gas into the etching cavity, and performing non-equalization of the second material layer The method of etch etching includes passing an etching gas into the etching chamber, wherein the deposition gas and the etching gas are introduced into the etching chamber alternately or together. The method of manufacturing a semiconductor device according to claim 1, wherein the method of forming the first material layer comprises forming a material layer on the substrate, and then removing a portion of the material layer by etch back to form a The first material layer, wherein the step of removing a portion of the material layer is performed in the etching cavity. The method of manufacturing a semiconductor device according to claim 1, wherein the method of patterning the first material layer with the second pattern as a mask comprises anisotropic etching, and in the etching chamber In the body. The method of manufacturing a semiconductor device according to claim 1, wherein a first thickness of the second material layer on a top surface of the core structure is greater than a second material layer in the first material A second thickness on the surface of the layer, wherein the ratio of the first thickness to the second thickness ranges from 3 to 20. The method of manufacturing a semiconductor device according to claim 1, wherein the second pattern covers a sidewall and a top surface of the core structure exposed by the first pattern, and the second pattern has Pointed top. A semiconductor component comprising: a core structure disposed on a substrate; a first pattern disposed on a sidewall of the core structure, wherein a top surface of the first pattern is lower than a top surface of the core structure; And a second pattern covering the sidewall and the top surface of the core structure exposed by the first pattern, wherein the second pattern has a pointed top, and the material of the first pattern is different from The material of the second pattern, And a sidewall of the second pattern is coplanar with a sidewall of the first pattern. The semiconductor device of claim 8, wherein the sidewall of the top of the second pattern is a bevel or a curved surface.