TW201705437A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

To provide a semiconductor device and a manufacturing method of the same, which can restrict a thickness and properly bond semiconductor substrates with each other. A semiconductor device of the present embodiment comprises a first semiconductor substrate, a second semiconductor substrate, a first metal layer, a second metal layer, a third metal layer, a first alloy layer and a second alloy layer. The first semiconductor substrate and the second semiconductor substrate face each other. The first metal layer is provided on the first semiconductor substrate and faces the second semiconductor substrate. The second metal layer is provided on the second semiconductor substrate and faces the first metal layer. The third metal layer is arranged between the first metal layer and the second metal layer. The first alloy layer is arranged between the first metal layer and the third metal layer and contains a component of the first metal layer and a component of the third metal layer. The second alloy layer is arranged between the second metal layer and the third metal layer and contains a component of the second metal layer and the component of the third metal layer. At least one of the first and second metal layers protrudes on an outer edge of at least one of the first and second metal layers toward the third metal layer side.

Description

Semiconductor device and method of manufacturing same [related application]

This application is based on the priority of the application based on Japanese Patent Application No. 2015-53864 (application date: March 17, 2015) and Japanese Patent Application No. 2015-110513 (application date: May 29, 2015). right. This application contains all of the basic application by reference to these basic applications.

Embodiments of the present invention relate to a semiconductor device and a method of fabricating the same.

In recent years, a three-dimensional or two-dimensional laminated semiconductor device in which a plurality of semiconductor substrates (wafers) are laminated has been attracting attention from the viewpoint of high functionality of semiconductors and the like. In the manufacturing process of the laminated semiconductor device, in order to connect the fine and high-density wirings to each other, the semiconductor substrates are bonded to each other by using minute microbumps including solder and barrier layers.

When the number of layers of the semiconductor substrate is increased, the thickness of the laminated semiconductor device (package) is increased. In order to suppress the thickness of the laminated semiconductor device, it is necessary to narrow the interval between the semiconductor substrates. In order to narrow the interval between the semiconductor substrates, it is necessary to previously reduce the amount of solder between the semiconductor substrates. However, when the amount of solder is too small, the solder is consumed by alloying with the barrier layer, thereby making it difficult to secure the amount of solder required for bonding the semiconductor substrate.

Therefore, in the laminated semiconductor device, it is required to suppress the thickness of the semiconductor device and to appropriately bond the semiconductor substrates (wafers) to each other.

According to an embodiment of the present invention, a semiconductor device and a method of manufacturing the same are provided, which are capable of suppressing a thickness and appropriately bonding semiconductor substrates to each other.

The semiconductor device of the present embodiment includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer, a second metal layer, a third metal layer, a first alloy layer, and a second alloy layer. The first semiconductor substrate and the second semiconductor substrate face each other. The first metal layer is provided on the second semiconductor substrate side of the first semiconductor substrate. The second metal layer is provided on the first semiconductor substrate side of the second semiconductor substrate. The third metal layer is disposed between the first metal layer and the second metal layer. The first alloy layer is disposed between the first metal layer and the third metal layer, and includes a component of the first metal layer and a component of the third metal layer. The second alloy layer is disposed between the second metal layer and the third metal layer, and includes a component of the second metal layer and a component of the third metal layer. At least one of the first and second metal layers is recessed in a direction away from the third metal layer from the peripheral portion of the central portion.

1‧‧‧Semiconductor device

11‧‧‧1st semiconductor substrate

11a‧‧‧ surface

12‧‧‧2nd semiconductor substrate

12a‧‧‧ surface

15_1~7‧‧‧TSV

16‧‧‧Connection layer

17‧‧‧metal layer

101‧‧‧BGA substrate

102, 103_1~6, 104‧‧‧矽 wafer

105‧‧‧Bumps

106‧‧‧IC chip

107, 108‧‧‧Bumps

109‧‧‧Wiring

121‧‧‧1st pad electrode

122‧‧‧2nd pad electrode

131‧‧‧1st passivation layer

132‧‧‧2nd passivation layer

141‧‧‧1st base metal layer

142‧‧‧2nd base metal layer

151‧‧‧1st barrier layer

151a‧‧‧The Peripheral Department

151b‧‧‧Central Department

151c‧‧‧ surface

152‧‧‧2nd barrier layer

152a‧‧‧The Peripheral Department

152b‧‧‧Central Department

152c‧‧‧ surface

161‧‧‧1st alloy layer

162‧‧‧2nd alloy layer

163‧‧‧ solder layer

1010‧‧‧Resin

1010-2‧‧‧ Sealing resin

1501‧‧‧1st through electrode

1501a‧‧‧The Peripheral Department

1501b‧‧‧Central Department

1502‧‧‧2nd through electrode

1502a‧‧‧The Peripheral Department

1502b‧‧‧Central Department

1503, 1504‧‧‧ barrier metal film

D1‧‧‧ interval

D2‧‧‧ interval

D3‧‧ depth

D‧‧‧ Thickness direction

V‧‧‧ gap

Fig. 1 is a schematic cross-sectional view showing a semiconductor device 1 according to a first embodiment.

Fig. 2 is a view showing a state of occurrence of a void of a solder layer corresponding to a depth of a recess in a central portion of the barrier layer in the first embodiment.

3A and 3B are schematic cross-sectional views showing a method of manufacturing the semiconductor device 1 of Fig. 1.

4A and 4B are schematic cross-sectional views showing a method of manufacturing the semiconductor device 1 according to the first modification of the first embodiment.

5A and 5B are schematic cross-sectional views showing a method of manufacturing the semiconductor device 1 according to a second modification of the first embodiment.

6A and 6B are schematic cross-sectional views showing a method of manufacturing the semiconductor device 1 according to a third modification of the first embodiment.

Fig. 7 is a schematic cross-sectional view showing the semiconductor device 1 of the second embodiment.

Fig. 8 is a schematic cross-sectional view showing a semiconductor device 1 according to a modification of the second embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)

Fig. 1 is a schematic cross-sectional view showing a semiconductor device 1 according to a first embodiment. As shown in FIG. 1, the semiconductor device 1 includes a first semiconductor substrate 11 and a second semiconductor substrate 12 that face each other.

Further, the semiconductor device 1 includes the first pad electrode 121, the first passivation layer 131 as the insulating layer, and the first underlying metal layer 141 in this order on the surface 11a (upper surface in FIG. 1) of the first semiconductor substrate 11. And the first barrier layer 151 as an example of the first metal layer. The first barrier layer 151 is provided on the first semiconductor substrate 11 and faces the second semiconductor substrate 12 . In other words, the first barrier layer 151 is provided on the second semiconductor substrate 12 side of the first semiconductor substrate 11.

Further, the semiconductor device 1 includes the second pad electrode 122, the second passivation layer 132, the second underlying metal layer 142, and the second metal in this order on the surface 12a (lower surface in FIG. 1) of the second semiconductor substrate 12. The second barrier layer 152 of one of the layers. The second barrier layer 152 is provided on the second semiconductor substrate 12 and faces the first barrier layer 151 . In other words, the second barrier layer 152 is provided on the first semiconductor substrate 11 side of the second semiconductor substrate 12.

Further, the semiconductor device 1 includes a bonding layer 16 (joining portion) between the first barrier layer 151 and the second barrier layer 152. The bonding layer 16 is provided with the first alloy layer 161, the solder layer 163 which is one example of the third metal layer, and the second alloy layer 162 in this order from the first barrier layer 151 side. In other words, the solder layer 163 is disposed between the first barrier layer 151 and the second barrier layer 152. The first alloy layer 161 is disposed between the first barrier layer 151 and the solder layer 163. The second alloy layer 162 is disposed between the second barrier layer 152 and the solder layer 163.

The first pad electrode 121 is disposed on the surface 11a of the first semiconductor substrate 11. The first pad electrode 121 is electrically connected to an element or wiring (not shown) formed on the first semiconductor substrate 11 . Similarly, the second pad electrode 122 is disposed on the surface 12a of the second semiconductor substrate 12. The second pad electrode 122 is electrically connected to an element or wiring (not shown) formed on the second semiconductor substrate 12 . The first and second pad electrodes 121 and 122 may be, for example, a Cu electrode or the like.

The first passivation layer 131 is disposed on the peripheral edge portion so as to cover the peripheral edge portion (peripheral portion) of the first pad electrode 121. Similarly, the second passivation layer 132 is disposed on the peripheral edge portion so as to cover the peripheral edge portion of the second pad electrode 122. The first and second passivation layers 131 and 132 are, for example, SiN films. The first and second passivation layers 131 and 132 may further contain SiO ₂ or a polyimide resin.

The first base metal layer 141 is disposed on the central portion and the first passivation layer 131 so as to cover the central portion of the first pad electrode 121 and the first passivation layer 131. Similarly, the second underlying metal layer 142 is disposed on the central portion and the second passivation layer 132 so as to cover the central portion of the second pad electrode 122 and the second passivation layer 132.

By disposing the first passivation layer 131 on the peripheral edge portion of the first pad electrode 121, the peripheral edge portion (peripheral portion) of the first underlying metal layer 141 located above the first passivation layer 131 is opposed to the first base metal. The central portion of the layer 141 protrudes toward the solder layer 163 side. Similarly, by disposing the second passivation layer 132 on the peripheral edge portion of the second pad electrode 122, the peripheral portion of the second underlying metal layer 142 located above the second passivation layer 132 is opposed to the second underlying metal layer. The central portion of 142 protrudes toward the solder layer 163 side. The protruding shape of the peripheral edge portions of the base metal layers 141 and 142 is reflected in the protruding shape of the peripheral edge portions 151a and 152a of the barrier layers 151 and 152 described below.

The first and second underlying metal layers 141 and 142 may be, for example, an Au layer or the like.

The first barrier layer 151 is disposed on the first underlying metal layer 141 so as to cover the first underlying metal layer 141. The first barrier layer 151 prevents the solder layer 163 from diffusing toward the first base metal layer 141 side. The second barrier layer 152 is disposed on the second underlying metal layer 142 so as to cover the second underlying metal layer 142. The second barrier layer 152 prevents the solder layer 163 from diffusing toward the second base metal layer 142 side. The first and second barrier layers 151 and 152 may be, for example, a Ni layer.

The solder layer 163 may include, for example, a eutectic alloy containing a low melting point material such as Sn or Pb in the composition. Specifically, the solder layer 163 may be SnAg, SnCu, SnPb, or the like.

The first alloy layer 161 includes a component of the first barrier layer 151 and a component of the solder layer 163. Specifically, the first alloy layer 161 is based on the first barrier layer 151 (first half-lead) by the solder layer 163 When the bulk substrate 11) is bonded to the second barrier layer 152 (second semiconductor substrate 12), a layer formed by partially alloying one of the first barrier layers 151 and one of the solder layers 163 is formed. Similarly, the second alloy layer 162 includes components of the second barrier layer 152 and components of the solder layer 163. Specifically, when the first barrier layer 151 and the second barrier layer 152 are bonded by the solder layer 163, the second alloy layer 162 is formed by partially alloying one of the second barrier layers 152 and the solder layer 163. Layer.

The material of the first alloy layer 161 and the material of the second alloy layer 162 may be the same as each other. For example, the first and second alloy layers 161 and 162 may be an alloy layer of solder and Ni. In addition, when the first barrier layer 151 and the second barrier layer 152 are different in material from each other, the first alloy layer 161 and the second alloy layer 162 are different from each other in material.

The first barrier layer 151 protrudes toward the solder layer 163 side at the peripheral portion (peripheral portion) 151a. In other words, the first barrier layer 151 is such that the central portion 151b is recessed in a direction away from the solder layer 163 as compared with the peripheral edge portion 151a. In other words, the first barrier layer 151 has a concave step shape that is recessed toward the first semiconductor substrate 11 side in the central portion 151b.

The first barrier layer 151 is disposed above the first passivation layer 131 at the peripheral edge portion 151a thereof. In other words, the peripheral edge portion 151a of the first barrier layer 151 is covered with the peripheral edge portion of the first base metal layer 141 that protrudes toward the solder layer 163 side. By covering the peripheral edge portion of the first base metal layer 141, even if the peripheral edge portion 151a of the first barrier layer 151 is not thick relative to the central portion 151b, it can protrude toward the solder layer 163 side. Therefore, the protruding shape of the peripheral edge portion 151a can be easily formed without adjusting the thickness of the first barrier layer 151.

The second barrier layer 152 protrudes toward the solder layer 163 side at the peripheral portion (peripheral portion) 152a. In other words, the second barrier layer 152 has a central portion 152b that is recessed in a direction away from the solder layer 163 as compared with the peripheral edge portion 152a. In other words, the second barrier layer 152 has a concave step shape that is recessed toward the second semiconductor substrate 12 side at the center portion 152b.

The second barrier layer 152 is disposed above the second passivation layer 132 at its peripheral edge portion 152a (below the lower side in FIG. 1). In other words, the peripheral edge portion 152a of the second barrier layer 152 is protruded toward the solder layer 163 side. The peripheral portion of the second base metal layer 142. By covering the peripheral edge portion of the second base metal layer 142, even if the peripheral edge portion 152a of the second barrier layer 152 is thinner than the central portion 152b, it can protrude toward the solder layer 163 side. Therefore, the protruding shape of the peripheral edge portion 152a can also be easily formed.

The distance d1 between the central portion 151b of the first barrier layer 151 and the central portion 152b of the second barrier layer 152 is preferably 8 μm or more from the viewpoint of sufficiently ensuring the thickness of the solder layer 163. In addition, the peripheral edge portion 151a of the first barrier layer 151 and the peripheral edge portion 152a of the second barrier layer 152 are suppressed from the viewpoint of suppressing the interval between the first semiconductor substrate 11 and the second semiconductor substrate 12 (that is, the thickness of the semiconductor device 1). The interval d2 is preferably less than 8 μm.

When the bonding layer 16 is composed only of the alloy layers 161 and 162, it is difficult to appropriately bond the first semiconductor substrate 11 and the second semiconductor substrate 12. The reason is that the alloy layer 161, 162 and the barrier layers 151, 152 are alloyed to consume the solder layer 163, and voids or cracks are generated during alloying, so that electrical and mechanical connection functions are deteriorated. Further, when both surfaces of the barrier layers 151 and 152 are flat, in order to secure a sufficient thickness (quantity) of the solder layer 163 between the barrier layers 151 and 152, it is necessary to enlarge the barrier layers 151 and 152 to each other. The interval. However, it is difficult to suppress the thickness of the semiconductor device 1 by widening the gap between the barrier layers 151 and 152. Further, when the thickness of the solder layer 163 is increased, the solder layer 163 flows out from between the barrier layers 151 and 152 to reach the other solder layers 163 in the periphery, thereby increasing the risk of short-circuiting the pad electrodes 121 to each other.

On the other hand, in the present embodiment, since the solder layer 163 which is not consumed by the gold is left between the first alloy layer 161 and the second alloy layer 162, the first semiconductor substrate 11 and the second semiconductor can be used. The substrate 12 is suitably joined (electrically and mechanically connected). Further, in the present embodiment, by recessing the central portions 151b and 152b of the barrier layers 151 and 152, even if the distance d2 between the peripheral edge portions 151a and 152a of the barrier layers 151 and 152 is reduced, the central portion 151b may be The 152b stably maintains a sufficient thickness of the solder layer 163 between each other.

Therefore, according to the semiconductor device 1 of the present embodiment, the semiconductor device 1 can be suppressed. The thickness and the semiconductor substrates 11 and 12 are appropriately joined to each other.

Fig. 2 is a view showing a state of occurrence of a gap V (see Fig. 1) of the solder layer 163 corresponding to the recessed depth d3 in the central portions 151b and 152b of the barrier layers 151 and 152 in the first embodiment. Further, "○" in Fig. 2 indicates that the solder layer 163 does not generate the void V. "△" in Fig. 2 indicates that a portion V of the solder layer 163 is generated. "X" in Fig. 2 indicates that a large portion of the solder layer 163 generates a void V. As shown in FIG. 2, when the depth d3 is 4.0 μm, a gap V is generated in a portion of the solder layer 163 between the central portions 151b and 152b. Further, when the depth d3 is 4.2 μm or more, a large portion of the solder layer 163 between the central portions 151b and 152b may be formed with a void, and cracks may occur. On the other hand, when the depth d3 is 3.5 μm or less, voids or cracks are hardly generated. Therefore, the depth d3 of the recess in the central portions 151b and 152b of the barrier layers 151 and 152 is preferably 3.5 μm or less from the viewpoint of suppressing voids or cracks.

Next, a method of manufacturing the semiconductor device 1 having the above configuration will be described. 3 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device 1 of FIG. 1. Specifically, FIG. 3A is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 before bonding by the solder layer 163. 3B is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 joined by the solder layer 163.

First, as shown in FIG. 3A, the semiconductor substrates 11 and 12 on which the solder layers 163 are formed on the surfaces 151c and 152c of the barrier layers 151 and 152 are opposed to each other in a reflow furnace (not shown). Further, the solder layer 163 may be formed, for example, by an electrolytic plating process. The barrier layers 151, 152 and the solder layer 163 may also constitute microbumps.

Next, in a state where the solder layers 163 formed on the barrier layers 151 and 152 are in contact with each other, the two solder layers 163 are heated and melted. Then, by cooling and solidifying the molten solder layer 163, as shown in FIG. 3B, the semiconductor substrates 11, 12 are bonded to each other by the solder layer 163.

At this time, one portion of the first barrier layer 151 and the solder layer 163 on the first barrier layer 151 side The portion is alloyed into the first alloy layer 161. Further, a portion of the second barrier layer 152 and a portion of the solder layer 163 on the second barrier layer 152 side are alloyed into the second alloy layer 162. On the other hand, by recessing the central portions 151b, 152b of the barrier layers 151, 152, the thickness of the solder layer 163 between the central portions 151b, 152b is thick. Due to the thick thickness, even if a part of the solder layer 163 between the central portions 151b and 152b is alloyed with the barrier layers 151 and 152, the remaining portion is not alloyed to maintain a sufficient thickness. Moreover, since the solder layer 163 can be prevented from flowing out to the side of the first barrier layer 151 and reaching the surrounding first pad electrode 121, the adjacent first pad electrodes 121 can be prevented from being short-circuited.

As described above, according to the method of manufacturing the semiconductor device 1 of the first embodiment, the central portions 151b and 152b of the barrier layers 151 and 152 are recessed (that is, the peripheral portions 151a and 152a of the barrier layers 151 and 152 are protruded). While suppressing the thickness of the semiconductor device 1, the semiconductor substrates 11, 12 can be appropriately bonded to each other.

(First variation)

Next, as an example of the first modification of the first embodiment, an example of the semiconductor device 1 in which the surface of the second barrier layer 152 is flat will be described. In the first modification, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will not be repeated. FIG. 4 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device 1 according to the first modification of the first embodiment. Specifically, FIG. 4A is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 before bonding by the solder layer 163. 4B is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 joined by the solder layer 163.

As shown in FIG. 4, the semiconductor device 1 of the first modification differs from the semiconductor device 1 of FIG. 1 in that the surface 152c of the second barrier layer 152 is flat (that is, the central portion is not recessed). Further, as shown in FIG. 4A, in the first modification, a metal layer 17 having a high conductivity such as Au is provided on the surface 152c of the second barrier layer 152 before the bonding of the semiconductor substrates 11 and 12, instead of the solder layer 163.

In the first modification, the central portion 151b of the first barrier layer 151 is recessed. Therefore, as shown 4B, after the bonding of the semiconductor substrates 11, 12, the barrier layers 151, 152 are prevented from being spaced apart from each other, and the central portions 151b, 152b of the barrier layers 151, 152 are secured to each other without being alloyed. A solder layer 163 of thickness.

Therefore, in the first modification, the thickness of the semiconductor device 1 is also suppressed, and the semiconductor substrates 11 and 12 can be appropriately bonded to each other. Further, in the first modification, the conductivity of the solder layer 163 can be improved by including the solder layer 163 as a component of the metal layer 17 having high conductivity. Moreover, since the metal layer 17 is thinner than the solder layer 163, the thickness of the semiconductor device 1 can be further suppressed.

(2nd variation)

Next, an example of the semiconductor device 1 in which the passivation layers 131 and 132 are formed thick will be described as a second modification of the first embodiment. In the second modification, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will not be repeated. Fig. 5 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device 1 according to a second modification of the first embodiment. Specifically, FIG. 5A is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 before bonding by the solder layer 163. FIG. 5B is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 joined by the solder layer 163.

As shown in FIG. 5, the semiconductor device 1 of the second modification differs from the semiconductor device 1 of FIG. 1 in that the passivation layers 131 and 132 are formed thick.

In the second modification, the barrier layers 151 and 152 are also recessed in the central portions 151b and 152b. Therefore, as shown in FIG. 5B, after the bonding of the semiconductor substrates 11, 12, the barrier layers 151, 152 are suppressed from each other, and between the central portions 151b, 152b of the barrier layers 151, 152, the alloy is ensured. A sufficient thickness of solder layer 163 is consumed. Therefore, in the second modification, the thickness of the semiconductor device 1 is also suppressed, and the semiconductor substrates 11 and 12 can be appropriately bonded to each other.

(3rd variation)

Next, as a third variation of the first embodiment, the first variation and the second variation will be described. An example of the semiconductor device 1 of the combined example will be described. In the third modification, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will not be repeated. Fig. 6 is a schematic cross-sectional view showing a method of manufacturing the semiconductor device 1 according to a third modification of the first embodiment. Specifically, FIG. 6A is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 before bonding by the solder layer 163. FIG. 6B is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 joined by the solder layer 163.

As shown in FIG. 6, the semiconductor device 1 of the third modification is different from the semiconductor device 1 of FIG. 1 in that the surface 152c of the second barrier layer 152 is flat and the passivation layers 131 and 132 are thick. Further, as shown in FIG. 6A, in the third modification, a metal layer 17 having a high conductivity such as Au is provided on the surface 152c of the second barrier layer 152 before the bonding of the semiconductor substrates 11 and 12, instead of the solder layer 163. . That is, the third variation is a combination of the first variation and the second modification.

According to the third modification, the effects of both the first variation and the second modification can be exhibited.

(Second embodiment)

Next, an embodiment of the semiconductor device 1 including the through electrodes will be described as a second embodiment. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will not be repeated. Fig. 7 is a schematic cross-sectional view showing the semiconductor device 1 of the second embodiment.

As shown in FIG. 7, the semiconductor device 1 of the second embodiment has first and second through electrodes 1501 and 1502 instead of the barrier layers 151 and 152 as the first and second metal layers. The first through electrode 1501 penetrates the first semiconductor substrate 11 . The second through electrode 1502 penetrates the second semiconductor substrate 12 . Barrier metal films 1503 and 1504 are formed between the through electrodes 1501 and 1502 and the semiconductor substrates 11 and 12.

As shown in FIG. 7, the first through electrode 1501 protrudes toward the solder layer 163 side at the peripheral edge portion (peripheral portion) 1501a. In other words, the first through electrode 1501 is such that the central portion 1501b is recessed in a direction away from the solder layer 163 as compared with the peripheral portion 1501a. In other words, the first through electrode 1501 has a concave step shape that is recessed toward the first semiconductor substrate 11 side in the central portion 1501b.

The second through electrode 1502 protrudes toward the solder layer 163 side at the peripheral edge portion (peripheral portion) 1502a. In other words, the second through electrode 1502 has a central portion 1502b that is recessed in a direction away from the solder layer 163 as compared with the peripheral edge portion 1502a. In other words, the second through electrode 1502 has a concave step shape that is recessed toward the second semiconductor substrate 12 side at the central portion 1502b.

According to the semiconductor device 1 of the second embodiment, even if the peripheral portions 1501a and 1502a of the through electrodes 1501 and 1502 are narrowed from each other, the central portions 1501b and 1502b of the through electrodes 1501 and 1502 can be secured between each other. A sufficient thickness of solder layer 163 is consumed by alloying. Therefore, according to the second embodiment, in the three-dimensional mounting using the through electrodes 1501 and 1502, the thickness of the semiconductor device 1 can be suppressed, and the semiconductor substrates 11 and 12 can be appropriately joined to each other. Further, in the second embodiment, one of the through electrodes 1501 and 1502 may be changed to an electrode other than the through electrodes 1501 and 1502 such as a pad electrode.

(variation)

Next, as an example of the modification of the second embodiment, an example of three-dimensional mounting using a boring hole (TSV) will be described. In the description of the present modification, the same components as those in FIG. 7 are denoted by the same reference numerals, and the description thereof will not be repeated. Fig. 8 is a schematic cross-sectional view showing a semiconductor device 1 according to a modification of the second embodiment.

As shown in FIG. 8, the semiconductor device 1 of the present modification includes a BGA (Ball Grid Array) substrate 101 and a plurality of layers mounted (joined and connected) on the BGA substrate 101 via the bumps 107 and 108. (3 or more) of the wafers 102, 103_1 to 6, 104 (semiconductor substrate). Each of the germanium wafers 102, 103_1 to 6, 104 is stacked in such a manner that the thickness direction D of the semiconductor device 1 has a space. Wiring or semiconductor elements (elements) (not shown) may be formed on each of the wafers 102, 103_1, 6, and 104.

On the upper surface of the BGA substrate 101, an IC wafer 106 is formed. On the other hand, on the lower surface of the BGA substrate 101, bumps 105 are formed.

The lowermost germanium wafer 102 (hereinafter also referred to as a connection wiring wafer) of the plurality of germanium wafers has a wiring 109 for connection to the BGA substrate 101 on the lower surface. Wiring 109 is separated The first bump 107 is connected to the upper surface of the BGA substrate 101. Further, the wiring 109 is connected to the IC wafer 106 formed on the upper surface of the BGA substrate 101 via the second bumps 108. Further, the connection wiring wafer 102 is penetrated by the TSV 15_1.

The plurality of layers of the germanium wafers 103_1, 103_2, 103_3, 103_4, 103_5, and 103_6 (hereinafter also referred to as intermediate wafers) connected to the upper layer of the wiring wafer 102 are located between the upper layer of the germanium wafer and the lower layer of the germanium wafer (intermediate). Each of the intermediate wafers 103_1 to 6 is connected by TSVs 15_2 to 7.

The topmost wafer 104 (hereinafter also referred to as a base wafer) does not have a TSV.

The TSVs adjacent in the thickness direction D (upper and lower) are joined to each other by the same bonding layer 16 as in FIG.

The TSV in the middle and lower layers of the TSV adjacent to the thickness direction D is an example of the first through electrode 1501 shown in FIG. On the other hand, the TSV on the upper layer side is an example of the second through electrode 1502. For example, TSV 15_2 is the second through electrode 1502 with respect to the lower layer TSV 15_1, and is the first through electrode 1501 with respect to the upper layer TSV 15_3.

Further, the 矽 wafer through which the TSV on the lower layer side penetrates is an example of the first semiconductor substrate 11, and the 矽 wafer through which the TSV on the upper layer side penetrates is an example of the second semiconductor substrate 12. In other words, the first semiconductor substrate 11 and the second semiconductor substrate 12 are two adjacent semiconductor substrates of three or more semiconductor substrates (the germanium wafers 102, 101_1 to 6, 104). For example, the germanium wafer 103_1 is the second semiconductor substrate 12 with respect to the lower layer (one side in the thickness direction D), and the germanium wafer 103_2 with respect to the upper layer (the other side in the thickness direction D) is the first semiconductor substrate 11.

Further, a resin 1010 is provided between adjacent wafers. Further, the space between the resins 1010 is filled with the sealing resin 1010-2.

Such a semiconductor device 1 can be mounted on a circuit board (not shown) via the bumps 105.

According to the semiconductor device 1 of the present variation, even if the peripheral portion of the adjacent TSV 15 is made This interval is narrowed, and a sufficient thickness of the solder layer 163 which is not consumed by the alloying can be ensured between the central portions of the TSV 15. Therefore, according to the present modification, in the three-dimensional mounting using the TSV, the thickness of the semiconductor device 1 is suppressed, and the germanium wafers can be appropriately connected to each other.

The embodiments of the present invention have been described, but the embodiments are presented as examples and are not intended to limit the scope of the invention. The embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and variations thereof are included in the scope of the invention as set forth in the claims and equivalents thereof.

1‧‧‧Semiconductor device

11‧‧‧1st semiconductor substrate

11a‧‧‧ surface

12‧‧‧2nd semiconductor substrate

12a‧‧‧ surface

16‧‧‧Connection layer

121‧‧‧1st pad electrode

122‧‧‧2nd pad electrode

131‧‧‧1st passivation layer

132‧‧‧2nd passivation layer

141‧‧‧1st base metal layer

142‧‧‧2nd base metal layer

151‧‧‧1st barrier layer

151a‧‧‧The Peripheral Department

151b‧‧‧Central Department

152‧‧‧2nd barrier layer

152a‧‧‧The Peripheral Department

152b‧‧‧Central Department

161‧‧‧1st alloy layer

162‧‧‧2nd alloy layer

163‧‧‧ solder layer

D1‧‧‧ interval

D2‧‧‧ interval

D3‧‧ depth

V‧‧‧ gap

Claims (7)

A semiconductor device including: first and second semiconductor substrates facing each other; a first metal layer provided on the second semiconductor substrate side of the first semiconductor substrate; and a second metal layer provided on the second semiconductor layer a second semiconductor layer on the first semiconductor substrate side; a third metal layer disposed between the first metal layer and the second metal layer; and a first alloy layer disposed on the first metal layer and the third layer And a second alloy layer disposed between the metal layer and the component of the third metal layer; And a component of the metal layer and the component of the third metal layer; and at least one of the first and second metal layers is recessed in a direction away from the third metal layer from a peripheral portion thereof. The semiconductor device according to claim 1, comprising: a pad electrode disposed on a surface of the first semiconductor substrate facing the second semiconductor substrate and the second semiconductor substrate facing the first semiconductor substrate At least one of the surface; an insulating layer disposed on a peripheral portion of the pad electrode; and a base metal layer disposed on a central portion of the pad electrode and the insulating layer; and the third metal layer In the solder layer, at least one of the first and second metal layers is a barrier layer disposed on the underlying metal layer, and the barrier layer has a central portion that is farther away from the third metal than the peripheral portion. The direction of the layer is concave. The semiconductor device of claim 2, wherein the barrier layer is disposed above the insulating layer at a peripheral portion thereof. The semiconductor device according to claim 1, wherein the third metal layer is a solder layer, and at least one of the first and second metal layers is a through electrode penetrating the first or second semiconductor substrate. The semiconductor device of claim 1, wherein at least one of the first and second metal layers contains Ni. The semiconductor device according to claim 1, comprising three or more semiconductor substrates facing each other, wherein the first and second semiconductor substrates are any two adjacent semiconductor substrates among the three or more semiconductor substrates. A method of manufacturing a semiconductor device comprising: positioning a first semiconductor substrate having a first metal layer and a second semiconductor substrate having a second metal layer between the first metal layer and the second metal layer And bonding a third metal layer; and forming a semiconductor device having a first alloy layer, a second alloy layer, and a remaining portion of the third metal layer, wherein the first alloy layer is a portion of the first metal layer Alloying the portion of the third metal layer on the first metal layer side, wherein the second alloy layer alloys a portion of the second metal layer and a portion of the third metal layer on the second metal layer side And at least one of the first and second metal layers is recessed in a direction away from the third metal layer from the peripheral portion of the central portion.