CN105990292B - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing method Download PDFInfo
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- CN105990292B CN105990292B CN201510849120.3A CN201510849120A CN105990292B CN 105990292 B CN105990292 B CN 105990292B CN 201510849120 A CN201510849120 A CN 201510849120A CN 105990292 B CN105990292 B CN 105990292B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
The present invention provides a kind of semiconductor device and its manufacturing method.Semiconductor device has the 1st semiconductor substrate, the 2nd semiconductor substrate, the 1st metal layer, the 2nd metal layer, the 3rd metal layer, the 1st alloy-layer and the 2nd alloy-layer.1st semiconductor substrate and the 2nd semiconductor substrate are mutually opposite.The 2nd semiconductor substrate side of the 1st semiconductor substrate is arranged in 1st metal layer.The 1st semiconductor substrate side of the 2nd semiconductor substrate is arranged in 2nd metal layer.3rd metal layer configures between the 1st metal layer and the 2nd metal layer.1st alloy-layer configures between the 1st metal layer and the 3rd metal layer, and includes the ingredient of the 1st metal layer and the ingredient of the 3rd metal layer.2nd alloy-layer configures between the 2nd metal layer and the 3rd metal layer, and includes the ingredient of the 2nd metal layer and the ingredient of the 3rd metal layer.At least one party of 1st and the 2nd metal layer is that central portion is recessed compared to its peripheral part to the direction far from the 3rd metal layer.
Description
[related application]
Present application is enjoyed with Japanese patent application case 2015-53864 (applying date: on March 17th, 2015) and Japan
Patent application case 2015-110513 (applying date: on May 29th, 2015) is the priority of basic application case.Present application is logical
Cross referring to the basic application case and include all the elements of basic application case.
Technical field
Embodiments of the present invention are related to a kind of semiconductor device and its manufacturing method.
Background technique
In recent years, lamination has 3 dimensions of multiple semiconductor substrates (chip) or the stack-up type semiconductor device of 2.5 dimensions just partly to lead
It is attracted attention for the viewpoint of the multifunction of body etc..In the manufacture processing procedure of stack-up type semiconductor device, in order to by fine and
Highdensity wiring is connected to each other, and utilize the small dimpling block (microbump) being made of solder and barrier layer and incite somebody to action
Semiconductor substrate is engaged with each other.
If the lamination number of semiconductor substrate increases, the thickness of stack-up type semiconductor device (encapsulation) thickens.In order to inhibit
The thickness of stack-up type semiconductor device, it is necessary to make the mutual narrower intervals of semiconductor substrate.In order to keep semiconductor substrate mutual
Narrower intervals must reduce the amount of the solder between semiconductor substrate in the past.However, the situation very few in the amount of solder
Under, solder is consumed by the alloying with barrier layer, therefore ensures that the amount of solder required for the engagement of semiconductor substrate becomes
It is difficult.
Therefore, in stack-up type semiconductor device, it is desirable that inhibit the thickness of semiconductor device, and by semiconductor substrate (core
Piece) it suitably engages each other.
Summary of the invention
Embodiments of the present invention provide a kind of semiconductor device and its manufacturing method, are able to suppress thickness and suitably will
Semiconductor substrate is engaged with each other.
The semiconductor device of present embodiment has the 1st semiconductor substrate, the 2nd semiconductor substrate, the 1st metal layer, the 2nd gold medal
Belong to layer, the 3rd metal layer, the 1st alloy-layer and the 2nd alloy-layer.1st semiconductor substrate and the 2nd semiconductor substrate are mutually opposite.
The 2nd semiconductor substrate side of the 1st semiconductor substrate is arranged in 1st metal layer.The 2nd semiconductor substrate is arranged in 2nd metal layer
1st semiconductor substrate side.3rd metal layer configures between the 1st metal layer and the 2nd metal layer.1st alloy-layer is configured in the 1st gold medal
Belong between layer and the 3rd metal layer, and includes the ingredient of the 1st metal layer and the ingredient of the 3rd metal layer.2nd alloy-layer is configured the 2nd
It between metal layer and the 3rd metal layer, and include the ingredient of the 2nd metal layer and the ingredient of the 3rd metal layer.1st and the 2nd metal layer
At least one party is that central portion is recessed compared to its peripheral part to the direction far from the 3rd metal layer.
Detailed description of the invention
Fig. 1 is the schematic sectional view for indicating the semiconductor device 1 of the 1st embodiment.
Fig. 2 is indicated in the 1st embodiment, solder layer corresponding with the recessed depth in the central portion of barrier layer
The figure of the generation situation in gap.
Fig. 3 A, 3B are the schematic sectional views for indicating the manufacturing method of semiconductor device 1 of Fig. 1.
Fig. 4 A, 4B are the diagrammatic sectional views for indicating the manufacturing method of the semiconductor device 1 of the 1st change case of the 1st embodiment
Figure.
Fig. 5 A, 5B are the diagrammatic sectional views for indicating the manufacturing method of the semiconductor device 1 of the 2nd change case of the 1st embodiment
Figure.
Fig. 6 A, 6B are the diagrammatic sectional views for indicating the manufacturing method of the semiconductor device 1 of the 3rd change case of the 1st embodiment
Figure.
Fig. 7 is the schematic sectional view for indicating the semiconductor device 1 of the 2nd embodiment.
Fig. 8 is the schematic sectional view for indicating the semiconductor device 1 of change case of the 2nd embodiment.
Specific embodiment
Hereinafter, the embodiments of the present invention will be described with reference to the drawings.Present embodiment does not limit the present invention.
(the 1st embodiment)
Fig. 1 is the schematic sectional view for indicating the semiconductor device 1 of the 1st embodiment.As shown in Figure 1, semiconductor device 1 has
Standby mutually opposite the 1st semiconductor substrate 11 and the 2nd semiconductor substrate 12.
In addition, semiconductor device 1 sequentially has the 1st in the surface 11a (upper surface in Fig. 1) of the 1st semiconductor substrate 11
Pad electrode 121, the 1st passivation layer 131 of an example as insulating layer, the 1st substrate metal layer 141 and as the 1st metal layer
An example the 1st barrier layer 151.1st barrier layer 151 is arranged in the 1st semiconductor substrate 11, and faces the 2nd semiconductor substrate 12.
That is, 12 side of the 2nd semiconductor substrate of the 1st semiconductor substrate 11 is arranged in the 1st barrier layer 151.
In addition, semiconductor device 1 sequentially has the 2nd in the surface 12a (lower surface in Fig. 1) of the 2nd semiconductor substrate 12
Pad electrode 122, the 2nd passivation layer 132, the 2nd substrate metal layer 142 and an example as the 2nd metal layer the 2nd barrier layer
152.2nd barrier layer 152 is arranged in the 2nd semiconductor substrate 12, and faces the 1st barrier layer 151.That is, the 2nd barrier layer
152 are arranged in 11 side of the 1st semiconductor substrate of the 2nd semiconductor substrate 12.
In addition, semiconductor device 1 between the 1st barrier layer 151 and the 2nd barrier layer 152, has (the engagement of bonding layer 16
Portion).Bonding layer 16 sequentially have from 151 side of the 1st barrier layer the 1st alloy-layer 161, as the 3rd metal layer an example solder
The 163 and the 2nd alloy-layer 162 of layer.That is, the configuration of solder layer 163 is between the 1st barrier layer 151 and the 2nd barrier layer 152.
1st alloy-layer 161 configures between the 1st barrier layer 151 and solder layer 163.2nd alloy-layer 162 is configured in the 2nd barrier layer 152
Between solder layer 163.
1st pad electrode 121 configures on the surface 11a of the 1st semiconductor substrate 11.1st pad electrode 121 be formed in
The element or wiring (not shown) of 1st semiconductor substrate 11 are electrically connected.Similarly, the 2nd pad electrode 122 configuration is led the 2nd half
On the surface 12a of structure base board 12.2nd pad electrode 122 and the element or wiring (not shown) for being formed in the 2nd semiconductor substrate 12
Electrical connection.1st and the 2nd pad electrode 121,122 is such as can also be for Cu electrode.
1st passivation layer 131 is configured in a manner of being coated the peripheral part (peripheral portion) of the 1st pad electrode 121 in the peripheral part
On.Similarly, the 2nd passivation layer 132 is configured on the peripheral part in a manner of being coated the peripheral part of the 2nd pad electrode 122.1st
And the 2nd passivation layer 131,132 be, for example, SiN film.1st and the 2nd passivation layer 131,132 also may include in turn SiO2Or polyimides
Resin.
1st substrate metal layer 141 is in a manner of being coated the central portion and the 1st passivation layer 131 of the 1st pad electrode 121, configuration
On the central portion and the 1st passivation layer 131.Similarly, the 2nd substrate metal layer 142 is with the center of coating 2nd pad electrode 122
The mode of portion and the 2nd passivation layer 132 configures on the central portion and the 2nd passivation layer 132.
By configuring the 1st passivation layer 131 on the peripheral part of the 1st pad electrode 121, and it is located at the 1st passivation layer 131
The peripheral part (peripheral portion) of 1st substrate metal layer 141 on upper layer relative to the 1st substrate metal layer 141 central portion to solder layer
163 sides are prominent.Similarly, by configuring the 2nd passivation layer 132 on the peripheral part of the 2nd pad electrode 122, and it is blunt to be located at the 2nd
Change the peripheral part of the 2nd substrate metal layer 142 on the upper layer of layer 132 relative to the central portion of the 2nd substrate metal layer 142 to solder layer
163 sides are prominent.The protrusion shape of the peripheral part of substrate metal layer 141,142 is reflected in the peripheral part of following barrier layers 151,152
The protrusion shape of 151a, 152a.
1st and the 2nd substrate metal layer 141,142 is such as can also be Au layers.
1st barrier layer 151 is configured on the 1st substrate metal layer 141 in a manner of coating 1st substrate metal layer 141.1st
Barrier layer 151 prevents solder layer 163 from spreading to 141 side of the 1st substrate metal layer.2nd barrier layer 152 is to be coated the 2nd base metal
The mode of layer 142 configures on the 2nd substrate metal layer 142.2nd barrier layer 152 prevents solder layer 163 to the 2nd substrate metal layer
The diffusion of 142 sides.1st and the 2nd barrier layer 151,152 for example can also be Ni layers.
Solder layer 163 such as can also by ingredient include Sn, Pb low melting material eutectic alloy and constitute.It is specific and
Speech, solder layer 163 can also be SnAg, SnCu, SnPb etc..
1st alloy-layer 161 includes the ingredient of the 1st barrier layer 151 and the ingredient of solder layer 163.Specifically, the 1st alloy
Layer 161 be using solder layer 163 by the 1st barrier layer 151 (the 1st semiconductor substrate 11) and 152 (the 2nd semiconductor of the 2nd barrier layer
Substrate 12) engagement when, the layer that is formed and a part of alloying by a part of the 1st barrier layer 151 and solder layer 163.
Similarly, the 2nd alloy-layer 162 includes the ingredient of the 2nd barrier layer 152 and the ingredient of solder layer 163.Specifically, the 2nd alloy-layer
162 be when being engaged the 1st barrier layer 151 with the 2nd barrier layer 152 using solder layer 163, by by the one of the 2nd barrier layer 152
Part and a part of alloying of solder layer 163 and the layer formed.
The material of 1st alloy-layer 161 and the material of the 2nd alloy-layer 162 can also be same to each other.For example, the 1st and the 2nd alloy
Layer 161,162 can also be the alloy-layer of solder and Ni.In addition, the 1st barrier layer 151 and the 2nd barrier layer 152 in material mutually not
In identical situation, the 1st alloy-layer 161 and the 2nd alloy-layer 162 are also different in material.
1st barrier layer 151 is prominent to 163 side of solder layer in its peripheral part (peripheral portion) 151a.That is, the 1st barrier
Layer 151 is recessed compared to peripheral part 151a to the direction far from solder layer 163 for central portion 151b.If in turn in other words,
1st barrier layer 151 has the recessed step-difference shape recessed to 11 side of the 1st semiconductor substrate in central portion 151b.
1st barrier layer 151 is configured in its peripheral part 151a in the top of the 1st passivation layer 131.That is, the 1st barrier layer
151 peripheral part 151a is coated the peripheral part to 163 side of solder layer the 1st substrate metal layer 141 outstanding.By being coated the 1st base
The peripheral part of bottom metal layer 141, even if the peripheral part 151a of the 1st barrier layer 151 is relative to central portion 151b and thickness is not thick,
It can be prominent to 163 side of solder layer.The thickness that therefore, there is no need to adjust the 1st barrier layer 151 can also be simply forming peripheral part
The protrusion shape of 151a.
2nd barrier layer 152 is prominent to 163 side of solder layer in its peripheral part (peripheral portion) 152a.That is, the 2nd barrier
Layer 152 is recessed compared to peripheral part 152a to the direction far from solder layer 163 for central portion 152b.If in turn in other words,
2nd barrier layer 152 has the recessed step-difference shape recessed to 12 side of the 2nd semiconductor substrate in central portion 152b.
2nd barrier layer 152 is configured in its peripheral part 152a in the top (lower section in Fig. 1) of the 2nd passivation layer 132.Also
It is to say, the peripheral part 152a of the 2nd barrier layer 152 is coated the peripheral part to 163 side of solder layer the 2nd substrate metal layer 142 outstanding.
By being coated the peripheral part of the 2nd substrate metal layer 142, even if the peripheral part 152a of the 2nd barrier layer 152 is relative to central portion 152b
And thickness is not thick, it also can be prominent to 163 side of solder layer.Thus, it is also possible to be simply forming the protrusion shape of peripheral part 152a.
For substantially ensuring the viewpoint of thickness of solder layer 163, the central portion 151b and the 2nd barrier of the 1st barrier layer 151
The interval d1 of the central portion 152b of layer 152 is preferably 8 μm or more.In addition, may refrain from the 1st semiconductor substrate 11 and the 2nd semiconductor
For the viewpoint at the interval (that is, thickness of semiconductor device 1) of substrate 12, the peripheral part 151a of the 1st barrier layer 151 with
The interval d2 of the peripheral part 152a of 2nd barrier layer 152 is not preferably up to 8 μm.
In the case where if bonding layer 16 is only made of alloy-layer 161,162, it is difficult to by the 1st semiconductor substrate 11 and the 2nd
Semiconductor substrate 12 suitably engages.The reason is that, being consumed by the alloying of alloy-layer 161,162 and barrier layer 151,152
Solder layer 163, in addition, generate gap or crack in alloying, so electrically, mechanical linkage function is deteriorated.In addition, In
In the case that if the surface of barrier layer 151,152 is both flat, in order to ensure between barrier layer 151,152 adequately
The solder layer 163 of thickness (amount), and barrier layer 151,152 mutual intervals must be expanded.However, by by barrier layer 151,
152 mutual intervals expand, and are difficult to inhibit the thickness of semiconductor device 1.In addition, being welded if the thickness of solder layer 163 increases
Thus the bed of material 163 generates pad electrode 121 each other from other solder layers 163 for flowing out and reaching surrounding between barrier layer 151,152
Short circuit risk improve.
In contrast, in the present embodiment, due to that can retain between the 1st alloy-layer 161 and the 2nd alloy-layer 162
The unconsumed solder layer 163 of alloying, so can suitably engage the 1st semiconductor substrate 11 with the 2nd semiconductor substrate 12
(electrically, mechanically connecting).In addition, in the present embodiment, by central portion 151b, 152b for making barrier layer 151,152
It is recessed, even if reduce barrier layer 151,152 the mutual interval d2 of peripheral part 151a, 152a, also can central portion 151b,
152b stably keeps the solder layer 163 of sufficient thickness each other.
Therefore, semiconductor device 1 according to the present embodiment inhibits the thickness of semiconductor device 1, and can be by semiconductor
Substrate 11,12 suitably engages each other.
Fig. 2 is indicated in the 1st embodiment, with the recessed depth in central portion 151b, 152b of barrier layer 151,152
Spend the figure of the generation situation of the gap V (referring to Fig.1) of the corresponding solder layer 163 of d3.In addition, the "○" of Fig. 2 indicates solder layer 163
Gap V is not generated." △ " of Fig. 2 indicates that a part of solder layer 163 produces gap V.The "×" of Fig. 2 indicates solder layer 163
Major part produce gap V.As shown in Fig. 2, there are the solders between central portion 151b and 152b if depth d3 is 4.0 μm
The case where a part of layer 163 generates gap V.In addition, there are central portion 151b and 152b if depth d3 is 4.2 μm or more
Between solder layer 163 most of the case where generating gap, in addition, there is also generate crack.In contrast, if depth
D3 is 3.5 μm hereinafter, being then nearly free from gap or crack.Therefore, for the viewpoint that may refrain from gap or crack, barrier layer
151, the recessed depth d3 in 152 central portion 151b, 152b is preferably 3.5 μm or less.
Secondly, being illustrated to the manufacturing method of the semiconductor device 1 with the composition.Fig. 3 is to indicate partly leading for Fig. 1
The schematic sectional view of the manufacturing method of body device 1.Specifically, Fig. 3 A is to indicate the semiconductor before engaging using solder layer 163
The schematic sectional view of substrate 11,12.Fig. 3 B is to indicate that the outline of the semiconductor substrate 11,12 after being engaged using solder layer 163 is cutd open
View.
Firstly, as shown in Figure 3A, making to be formed with partly leading for solder layer 163 in surface 151c, 152c of barrier layer 151,152
Structure base board 11,12 is mutually opposite in reflow soldering (not shown) each other.In addition, solder layer 163 for example can also be by electrolysis plating
Processing procedure and formed.Barrier layer 151,152 and solder layer 163 also may make up dimpling block.
Secondly, in the state of making the solder layer 163 for being formed in barrier layer 151,152 be in contact with each other, by two solder layers 163
It heats and melts.Then, by cooling down and solidifying molten solder layer 163, and it is as shown in Figure 3B, utilize solder layer 163
Semiconductor substrate 11,12 is engaged with each other.
At this point, the position alloy of the solder layer 163 of a part of the 1st barrier layer 151 and 151 side of the 1st barrier layer turns to the 1st
Alloy-layer 161.In addition, a part of the 2nd barrier layer 152 and the position alloy of the solder layer 163 of 152 side of the 2nd barrier layer turn to
2nd alloy-layer 162.On the other hand, by keeping central portion 151b, 152b of barrier layer 151,152 recessed, and central portion 151b,
The thickness of solder layer 163 between 152b is thicker.Since thickness is thicker, even if between central portion 151b, 152b
163 a part of solder layer and barrier layer 151,152 alloyings, and the non-alloying of remainder is also able to maintain that sufficient thickness.
In addition, flowed out to the side of the 1st barrier layer 151 due to can be avoided solder layer 163 and reach the 1st pad electrode 121 on periphery,
So the adjacent mutual short circuit of the 1st pad electrode 121 can be prevented.
As previously discussed, according to the manufacturing method of the semiconductor device 1 of the 1st embodiment, by making barrier layer 151,152
Central portion 151b, 152b recess (that is, keeping peripheral part 151a, 152a of barrier layer 151,152 prominent), and inhibit half
The thickness of conductor device 1, and semiconductor substrate 11,12 can suitably be engaged each other.
(the 1st change case)
Secondly, the 1st change case as the 1st embodiment, the semiconductor device 1 flat to the surface of the 2nd barrier layer 152
Example be illustrated.In addition, being omitted about constituting portion corresponding with Fig. 1 using identical symbol when illustrating 1 change case
Repeat description.Fig. 4 is the diagrammatic sectional view for indicating the manufacturing method of the semiconductor device 1 of the 1st change case of the 1st embodiment
Figure.Specifically, Fig. 4 A is the schematic sectional view for indicating the semiconductor substrate 11,12 before engaging using solder layer 163.Fig. 4 B is
Indicate the schematic sectional view of the semiconductor substrate 11,12 after engaging using solder layer 163.
As shown in figure 4, semiconductor device 1 of the semiconductor device 1 of the 1st change case relative to Fig. 1, in the 2nd barrier layer 152
Surface 152c flat (that is, central portion is not recessed) aspect it is different.In addition, as shown in Figure 4 A, in the 1st change case
In, before the engagement of semiconductor substrate 11,12, in the metal layer of the high conductivities such as the surface 152c setting Au of the 2nd barrier layer 152
17 replace solder layer 163.
In the 1st change case, the central portion 151b of the 1st barrier layer 151 is recessed.Therefore, as shown in Figure 4 B, semiconductor-based
After the engagement of plate 11,12, inhibit barrier layer 151,152 mutual intervals, and the central portion 151b of barrier layer 151,152,
152b can ensure the solder layer 163 of the unconsumed sufficient thickness of alloying each other.
Therefore, in the 1st change case, also inhibit semiconductor device 1 thickness, and can by semiconductor substrate 11,12 that
This is suitably engaged.In addition, in the 1st change case, by making solder layer 163 include the ingredient of the metal layer 17 of high conductivity,
Also it can be improved the conductivity of solder layer 163.In addition, due to metal layer 17 compared with solder layer 163 thinner thickness, so can
Further suppress the thickness of semiconductor device 1.
(the 2nd change case)
Secondly, the 2nd change case as the 1st embodiment, fills the semiconductor for being formed thicker by passivation layer 131,132
1 example is set to be illustrated.In addition, when illustrating 2 change case, about constituting portion corresponding with Fig. 1 using identical symbol and
The repetitive description thereof will be omitted.Fig. 5 is to indicate that the outline of the manufacturing method of the semiconductor device 1 of the 2nd change case of the 1st embodiment cuts open
View.Specifically, Fig. 5 A is the schematic sectional view for indicating the semiconductor substrate 11,12 before engaging using solder layer 163.Fig. 5 B
It is the schematic sectional view for indicating the semiconductor substrate 11,12 after engaging using solder layer 163.
As shown in figure 5, semiconductor device 1 of the semiconductor device 1 of the 2nd change case relative to Fig. 1, by passivation layer 131,
The 132 aspect differences for being formed thicker.
In the 2nd change case, barrier layer 151,152 is also recessed in central portion 151b, 152b.Therefore, as shown in Figure 5 B,
After the engagement of semiconductor substrate 11,12, inhibit barrier layer 151,152 mutual intervals, and in the center of barrier layer 151,152
Between portion 151b, 152b, it can be ensured that the solder layer 163 of the unconsumed sufficient thickness of alloying.Therefore, become the 2nd
Change in example, also inhibit the thickness of semiconductor device 1, and semiconductor substrate 11,12 can suitably be engaged each other.
(the 3rd change case)
Secondly, the 3rd change case as the 1st embodiment, to the semiconductor for combining the 1st change case with the 2nd change case
The example of device 1 is illustrated.In addition, using identical symbol about constituting portion corresponding with Fig. 1 when illustrating 3 change case
And the repetitive description thereof will be omitted.Fig. 6 is the outline for indicating the manufacturing method of the semiconductor device 1 of the 3rd change case of the 1st embodiment
Cross-sectional view.Specifically, Fig. 6 A is the schematic sectional view for indicating the semiconductor substrate 11,12 before engaging using solder layer 163.Figure
6B is the schematic sectional view for indicating the semiconductor substrate 11,12 after engaging using solder layer 163.
As shown in fig. 6, semiconductor device 1 of the semiconductor device 1 of the 3rd change case relative to Fig. 1, in the 2nd barrier layer 152
Surface 152c it is flat, and the thicker aspect of passivation layer 131,132 is different.In addition, as shown in Figure 6A, in the 3rd change case, In
Before the engagement of semiconductor substrate 11,12, in the surface 152c of the 2nd barrier layer 152, the metal layer 17 of the high conductivities such as Au is set
Instead of solder layer 163.That is, the 3rd change case is the combination of the 1st change case and the 2nd change case.
According to the 3rd change case, the effect of the two of the 1st change case and the 2nd change case can be played.
(the 2nd embodiment)
Secondly, being illustrated as the 2nd embodiment to the embodiment for the semiconductor device 1 for having through electrode.This
Outside, when illustrating 2 embodiment, repetition is omitted using identical symbol about constituting portion corresponding with the 1st embodiment
Explanation.Fig. 7 is the schematic sectional view for indicating the semiconductor device 1 of the 2nd embodiment.
As shown in fig. 7, there is the semiconductor device 1 of the 2nd embodiment the 1st, the 2nd through electrode 1501,1502 to replace
Barrier layer 151,152, as the 1st, the 2nd metal layer.1st through electrode 1501 penetrates through the 1st semiconductor substrate 11.2nd perforation electricity
Pole 1502 penetrates through the 2nd semiconductor substrate 12.Between through electrode 1501,1502 and semiconductor substrate 11,12, it is formed with barrier
Metal film 1503,1504.
As shown in fig. 7, the 1st through electrode 1501 is in peripheral part (peripheral portion) 1501a, it is prominent to 163 side of solder layer.Also
It is to say, the 1st through electrode 1501 is that central portion 1501b is recessed compared to peripheral part 1501a to the direction far from solder layer 163.
If in turn in other words, the 1st through electrode 1501 has in central portion 1501b to recessed recessed in 11 side of the 1st semiconductor substrate
Step-difference shape.
2nd through electrode 1502 is prominent to 163 side of solder layer in peripheral part (peripheral portion) 1502a.That is, the 2nd passes through
Energization pole 1502 is that central portion 1502b is recessed compared to peripheral part 1502a to the direction far from solder layer 163.If changing sentence in turn
It talks about, then the 2nd through electrode 1502 has the recessed step-difference shape recessed to 12 side of the 2nd semiconductor substrate in central portion 1502b.
According to the semiconductor device 1 of the 2nd embodiment, the even peripheral part 1501a of through electrode 1501,1502,
The mutual narrower intervals of 1502a, also can be between central portion 1501b, 1502b of through electrode 1501,1502, it is ensured that
The solder layer 163 of the unconsumed sufficient thickness of alloying.Therefore, according to the 2nd embodiment, using through electrode 1501,
In 1502 three-dimensional installation, inhibit the thickness of semiconductor device 1, and semiconductor substrate 11,12 can suitably be engaged each other.
In addition, a side of through electrode 1501,1502 can also be changed to the through electrodes such as pad electrode in the 2nd embodiment
1501, the electrode other than 1502.
(change case)
Secondly, the change case as the 2nd embodiment, is illustrated the example of the three-dimensional installation using silicon perforation (TSV).
In addition, when illustrating this change case, about constituting portion corresponding with Fig. 7 using identical symbol and the repetitive description thereof will be omitted.Fig. 8
It is the schematic sectional view for indicating the semiconductor device 1 of change case of the 2nd embodiment.
As shown in figure 8, the semiconductor device 1 of this change case has BGA (Ball Grid Array, ball grid array) substrate
101 and carry on BGA substrate 101 across convex block 107,108 (engagement, connection) multilayer (3 or more) silicon chip
102,103_1~6,104 (semiconductor substrates).Each silicon chip 102,103_1~6,104 are in the thickness side of semiconductor device 1
Has spaced mode lamination configuration to D.It can form wiring (not shown) at each silicon chip 102,103_1~6,104 or partly lead
Volume elements part (element).
In the upper surface of BGA substrate 101, it is formed with IC (integrated circuit, integrated circuit) chip 106.Separately
On the one hand, in the lower surface of BGA substrate 101, it is formed with convex block 105.
Undermost silicon chip 102 (hereinafter also referred to as connection wiring chip) has use in lower surface in multilayer silicon chip
With the wiring 109 being connect with BGA substrate 101.Wiring 109 is connect across the 1st convex block 107 with the upper surface of BGA substrate 101.
In addition, wiring 109 is connect across the 2nd convex block 108 with the IC chip 106 for the upper surface for being formed in BGA substrate 101.In addition, even
Wiring chip 102 is connect to be penetrated through by TSV15_1.
Multilayer silicon chip 103_1,103_2,103_3,103_4,103_5, the 103_6 on the upper layer of connection wiring chip 102
(hereinafter also referred to as intermediate chip) is located between the silicon chip on upper layer and the silicon chip of lower layer (centre).Each intermediate chip 103_1
~6 are penetrated through by TSV15_2~7.
The silicon chip 104 (hereinafter also referred to as base chip) of top layer does not have TSV.
It is engaged each other by bonding layer 16 same as figure 7 in thickness direction D (upper and lower) adjacent TSV.
The TSV of lower layer side is an example of the 1st through electrode 1501 shown in Fig. 7 in the adjacent TSV of thickness direction D.Separately
On the one hand, the TSV of upper layer side is an example of the 2nd through electrode 1502.For example, TSV15_2 is the relative to the TSV15_1 of lower layer
2 through electrodes 1502, the TSV15_3 relative to upper layer are the 1st through electrode 1501.
In addition, being an example of the 1st semiconductor substrate 11 by the silicon chip that the TSV of lower layer side is penetrated through, passed through by the TSV of upper layer side
Logical silicon chip is an example of the 2nd semiconductor substrate 12.That is, the 1st semiconductor substrate 11 and the 2nd semiconductor substrate 12 are
Adjacent arbitrary 2 semiconductor substrates in 3 or more semiconductor substrates (silicon chip 102,101_1~6,104).Example
Such as, silicon chip 103_1 is the 2nd semiconductor substrate 12 relative to the silicon chip 102 of lower layer (side of thickness direction D), relative to
The silicon chip 103_2 on upper layer (other side of thickness direction D) is the 1st semiconductor substrate 11.
In addition, being provided with resin 1010 between adjacent silicon chip.In addition, the space between resin 1010 is set by sealing
Rouge 1010-2 filling.
Such semiconductor device 1 can carry circuit substrate (not shown) across convex block 105.
According to the semiconductor device 1 of this change case, even if making the mutual narrower intervals in the peripheral part of adjacent TSV15,
It can be between the central portion of TSV15, it is ensured that the solder layer 163 of the unconsumed sufficient thickness of alloying.Therefore, according to
This change case inhibits the thickness of semiconductor device 1, can suitably connect silicon chip each other in the three-dimensional installation using TSV
It connects.
Several embodiments of the invention are described, but these embodiments are prompted as example, not
The range of intended limitation invention.These embodiments can be implemented in such a way that others are various, in the purport for not departing from invention
In range, it is able to carry out various omissions, displacement, change.The variation of these embodiments or embodiment be included in invention
Range or purport include in invention documented by claims and its impartial range similarly.
[explanation of symbol]
1 semiconductor device
11 the 1st semiconductor substrates
12 the 2nd semiconductor substrates
151 the 1st barrier layers
152 the 2nd barrier layers
161 the 1st alloy-layers
162 the 2nd alloy-layers
163 solder layers
Claims (7)
1. a kind of semiconductor device, it is characterised in that have:
Mutually the 1st and the 2nd opposite semiconductor substrate；
The 2nd semiconductor substrate side of the 1st semiconductor substrate is arranged in 1st metal layer；
The 1st semiconductor substrate side of the 2nd semiconductor substrate is arranged in 2nd metal layer；
3rd metal layer configures between the 1st metal layer and the 2nd metal layer；
1st alloy-layer, configure between the 1st metal layer and the 3rd metal layer, and include the 1st metal layer at
Divide the ingredient with the 3rd metal layer；And
2nd alloy-layer, configure between the 2nd metal layer and the 3rd metal layer, and include the 2nd metal layer at
Divide the ingredient with the 3rd metal layer；And
At least one party of described 1st and the 2nd metal layer is side of the central portion compared to its peripheral part and to separate 3rd metal layer
To recess；
If the 1st metal layer and the 2nd metal layer are set as d1, by the 1st metal layer at the interval of the central portion
Be set as d2 at the interval of the peripheral part with the 2nd metal layer, the depth of the recess be set as to d3, then meet d1 >=8 μm,
8 μm of d2 <, d3≤3.5 μm.
2. semiconductor device according to claim 1, it is characterised in that have:
Pad electrode configures on the surface in face of the 1st semiconductor substrate of the 2nd semiconductor substrate and faces institute
State at least one party on the surface of the 2nd semiconductor substrate of the 1st semiconductor substrate；
Insulating layer configures on the peripheral part of the pad electrode；And
Substrate metal layer configures on the central portion of the pad electrode and on the insulating layer；And
3rd metal layer is solder layer,
At least one party of 1st and the 2nd metal layer is barrier layer of the configuration on the substrate metal layer,
The barrier layer is that central portion is recessed compared to its peripheral part to the direction far from the 3rd metal layer.
3. semiconductor device according to claim 2, it is characterised in that: described in the thickness ratio of the peripheral part of the barrier layer
The thickness of the peripheral part of insulating layer is thicker.
4. semiconductor device according to claim 1, it is characterised in that: the 3rd metal layer is solder layer,
At least one party of 1st and the 2nd metal layer is the through electrode for penetrating through the 1st or the 2nd semiconductor substrate.
5. semiconductor device according to claim 1, it is characterised in that: at least one party of the 1st and the 2nd metal layer contains
There is Ni.
6. semiconductor device according to claim 1, it is characterised in that have the semiconductor-based of 3 or more of mutual opposite direction
Plate,
Adjacent any 2 in semiconductor substrate that 1st and the 2nd semiconductor substrate is described 3 or more are semiconductor-based
Plate.
7. a kind of manufacturing method of semiconductor device, it is characterised in that have:
By the 1st semiconductor substrate with the 1st metal layer and with the 2nd semiconductor substrate of the 2nd metal layer, existed using configuration
1st metal layer is engaged with the 3rd metal layer between the 2nd metal layer；And
Semiconductor device is formed, which has the remainder of the 1st alloy-layer, the 2nd alloy-layer and the 3rd metal layer
Point, the 1st alloy-layer is the portion of the 3rd metal layer by a part of the 1st metal layer Yu the 1st metal layer side
Position alloying forms, and the 2nd alloy-layer is the described 3 by a part of the 2nd metal layer and the 2nd metal layer side
The position alloying of metal layer forms；And
At least one party of described 1st and the 2nd metal layer is side of the central portion compared to its peripheral part and to separate 3rd metal layer
To recess；
If the 1st metal layer and the 2nd metal layer are set as d1, by the 1st metal layer at the interval of the central portion
Be set as d2 at the interval of the peripheral part with the 2nd metal layer, the depth of the recess be set as to d3, then meet d1 >=8 μm,
8 μm of d2 <, d3≤3.5 μm.
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| JP2015110513A JP6431442B2 (en) | 2015-03-17 | 2015-05-29 | Semiconductor device and manufacturing method thereof |
| JP2015-110513 | 2015-05-29 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6424049B1 (en) * | 1999-02-23 | 2002-07-23 | Rohm Co., Ltd. | Semiconductor device having chip-on-chip structure and semiconductor chip used therefor |
| CN101894814A (en) * | 2009-02-24 | 2010-11-24 | 宇芯先进技术有限公司 | Solder bump ubm structure |
| JP5272922B2 (en) * | 2009-06-24 | 2013-08-28 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| CN103426849A (en) * | 2012-05-18 | 2013-12-04 | 台湾积体电路制造股份有限公司 | Three-dimensional chip stack and method of forming the same |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02271533A (en) * | 1989-04-12 | 1990-11-06 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH03218644A (en) * | 1990-01-24 | 1991-09-26 | Sharp Corp | Connection structure of circuit board |
| JP3412969B2 (en) * | 1995-07-17 | 2003-06-03 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JP4656275B2 (en) * | 2001-01-15 | 2011-03-23 | 日本電気株式会社 | Manufacturing method of semiconductor device |
| US7300857B2 (en) * | 2004-09-02 | 2007-11-27 | Micron Technology, Inc. | Through-wafer interconnects for photoimager and memory wafers |
| TWI414580B (en) * | 2006-10-31 | 2013-11-11 | Sumitomo Bakelite Co | Adhesive tape and semiconductor device using the same |
| CN101529590B (en) * | 2006-10-31 | 2012-03-21 | 住友电木株式会社 | Semiconductor electronic component and semiconductor device using the same |
| JP2010118522A (en) * | 2008-11-13 | 2010-05-27 | Renesas Technology Corp | Semiconductor device and method for manufacturing the semiconductor device |
| JP2011009363A (en) * | 2009-06-24 | 2011-01-13 | Nec Corp | Semiconductor device, method of manufacturing the same, and composite circuit device using the same |
| US8354750B2 (en) * | 2010-02-01 | 2013-01-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress buffer structures in a mounting structure of a semiconductor device |
| US8360303B2 (en) * | 2010-07-22 | 2013-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Forming low stress joints using thermal compress bonding |
| US8581420B2 (en) * | 2010-10-18 | 2013-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Under-bump metallization (UBM) structure and method of forming the same |
| JP2013021058A (en) * | 2011-07-08 | 2013-01-31 | Elpida Memory Inc | Manufacturing method of semiconductor device |
| KR101936232B1 (en) * | 2012-05-24 | 2019-01-08 | 삼성전자주식회사 | Electrical interconnection structures and methods for fabricating the same |
| US9230934B2 (en) * | 2013-03-15 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Surface treatment in electroless process for adhesion enhancement |
-
2015
- 2015-05-29 JP JP2015110513A patent/JP6431442B2/en active Active
- 2015-11-25 TW TW104139212A patent/TWI603457B/en active
- 2015-11-27 CN CN201510849120.3A patent/CN105990292B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6424049B1 (en) * | 1999-02-23 | 2002-07-23 | Rohm Co., Ltd. | Semiconductor device having chip-on-chip structure and semiconductor chip used therefor |
| CN101894814A (en) * | 2009-02-24 | 2010-11-24 | 宇芯先进技术有限公司 | Solder bump ubm structure |
| JP5272922B2 (en) * | 2009-06-24 | 2013-08-28 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| CN103426849A (en) * | 2012-05-18 | 2013-12-04 | 台湾积体电路制造股份有限公司 | Three-dimensional chip stack and method of forming the same |
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| TWI603457B (en) | 2017-10-21 |
| CN105990292A (en) | 2016-10-05 |
| JP6431442B2 (en) | 2018-11-28 |
| TW201705437A (en) | 2017-02-01 |
| JP2016174134A (en) | 2016-09-29 |
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