JP2016174134A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which can restrict a thickness and properly bond semiconductor substrates with each other.SOLUTION: A semiconductor device of the present embodiment comprises a first semiconductor substrate, a second semiconductor substrate, a first metal layer, a second metal layer, a third metal layer, a first alloy layer and a second alloy layer. The first semiconductor substrate and the second semiconductor substrate face each other. The first metal layer is provided on the first semiconductor substrate and faces the second semiconductor substrate. The second metal layer is provided on the second semiconductor substrate and faces the first metal layer. The third metal layer is arranged between the first metal layer and the second metal layer. The first alloy layer is arranged between the first metal layer and the third metal layer and contains a component of the first metal layer and a component of the third metal layer. The second alloy layer is arranged between the second metal layer and the third metal layer and contains a component of the second metal layer and the component of the third metal layer. At least one of the first and second metal layers protrudes on an outer edge of at least one of the first and second metal layers toward the third metal layer side.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  In recent years, a three-dimensional or 2.5-dimensional stacked semiconductor device in which a plurality of semiconductor substrates (chips) are stacked has attracted attention from the viewpoint of increasing the functionality of semiconductors. In the manufacturing process of the stacked semiconductor device, the semiconductor substrates are joined to each other with a micro-bump composed of a solder and a barrier layer in order to connect fine and high-density wirings.

  As the number of stacked semiconductor substrates increases, the thickness of the stacked semiconductor device (package) increases. In order to suppress the thickness of the stacked semiconductor device, it is necessary to narrow the interval between the semiconductor substrates. Conventionally, it has been necessary to reduce the amount of solder between the semiconductor substrates in order to narrow the interval between the semiconductor substrates. However, when the amount of solder is too small, the solder is consumed by alloying with the barrier layer, making it difficult to secure the amount of solder necessary for joining the semiconductor substrates.

  For this reason, in the stacked semiconductor device, it is required to suppress the thickness of the semiconductor device and appropriately join the semiconductor substrates (chips).

JP 2012-204444 A

  Provided are a semiconductor device capable of suppressing the thickness and appropriately joining semiconductor substrates, and a manufacturing method thereof.

The semiconductor device according to the present embodiment includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer, a second metal layer, a third metal layer, a first alloy layer, and a second alloy layer. Prepare. The first semiconductor substrate and the second semiconductor substrate oppose each other. The first metal layer is provided on the first semiconductor substrate and faces the second semiconductor substrate. The second metal layer is provided on the second semiconductor substrate and faces the first metal layer. The third metal layer is disposed between the first metal layer and the second metal layer. The first alloy layer is disposed between the first metal layer and the third metal layer, and includes a component of the first metal layer and a component of the third metal layer.
The second alloy layer is disposed between the second metal layer and the third metal layer, and includes a component of the second metal layer and a component of the third metal layer. At least one of the first and second metal layers protrudes toward the third metal layer at the periphery.

1 is a schematic cross-sectional view of a semiconductor device 1 showing a first embodiment. In 1st Embodiment, it is a figure which shows the generation | occurrence | production state of the void of a solder layer according to the depth of the recess in the center part of a barrier layer. FIG. 2 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device 1 of FIG. 1. FIG. 10 is a schematic cross-sectional view of the method for manufacturing the semiconductor device 1 showing a first modification of the first embodiment. FIG. 10 is a schematic cross-sectional view of the method for manufacturing the semiconductor device 1 showing a second modification of the first embodiment. FIG. 10 is a schematic cross-sectional view of the method for manufacturing the semiconductor device 1 showing a third modification of the first embodiment. It is a schematic sectional drawing of the semiconductor device 1 which shows 2nd Embodiment. It is a schematic sectional drawing of the semiconductor device 1 which shows the modification of 2nd Embodiment.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a schematic cross-sectional view of a semiconductor device 1 showing the first embodiment. As shown in FIG. 1, the semiconductor device 1 includes a first semiconductor substrate 11 and a second semiconductor substrate 12 that face each other.

  The semiconductor device 1 includes, in order, a first pad electrode 121, a first passivation layer 131 that is an example of an insulating layer, and a first base metal layer on a surface 11a (an upper surface in FIG. 1) of the first semiconductor substrate 11. 141 and a first barrier layer 151 which is an example of a first metal layer. The first barrier layer 151 is provided on the first semiconductor substrate 11 and faces the second semiconductor substrate 12.

  Further, in the semiconductor device 1, the second pad electrode 122, the second passivation layer 132, the second base metal layer 142, and the second metal are sequentially formed on the surface 12a (the lower surface in FIG. 1) of the second semiconductor substrate 12. A second barrier layer 152 which is an example of a layer. The second barrier layer 152 is provided on the second semiconductor substrate 12 and faces the first barrier layer 151.

  In addition, the semiconductor device 1 includes the bonding layer 16 (bonding portion) between the first barrier layer 151 and the second barrier layer 152. The bonding layer 16 includes, in order from the first barrier layer 151 side, a first alloy layer 161, a solder layer 163 that is an example of a third metal layer, and a second alloy layer 162. That is, the solder layer 163 is disposed between the first barrier layer 151 and the second barrier layer 152. The first alloy layer 161 is disposed between the first barrier layer 151 and the solder layer 163. The second alloy layer 162 is disposed between the second barrier layer 152 and the solder layer 163.

  The first pad electrode 121 is disposed on the surface 11 a of the first semiconductor substrate 11. The first pad electrode 121 is electrically connected to a device or wiring (not shown) formed on the first semiconductor substrate 11. Similarly, the second pad electrode 122 is disposed on the surface 12 a of the second semiconductor substrate 12. The second pad electrode 122 is electrically connected to a device or wiring (not shown) formed on the second semiconductor substrate 12. The first and second pad electrodes 121 may be, for example, Cu electrodes.

The first passivation layer 131 is disposed on the peripheral portion so as to cover the peripheral portion (peripheral portion) of the first pad electrode 121. Similarly, the second passivation layer 132 is disposed on the peripheral edge so as to cover the peripheral edge of the second pad electrode 122. The first and second passivation layers 131 and 132 are, for example, SiN films. The first and second passivation layers 131 and 132 may further contain SiO ₂ or polyimide resin.

  The first base metal layer 141 is disposed on the central portion and the first passivation layer 131 so as to cover the central portion of the first pad electrode 121 and the first passivation layer 131. Similarly, the second base metal layer 142 is disposed on the central portion and the second passivation layer 132 so as to cover the central portion of the second pad electrode 122 and the second passivation layer 132.

  Since the first passivation layer 131 is disposed on the peripheral portion of the first pad electrode 121, the peripheral portion (peripheral portion) of the first base metal layer 141 located above the first passivation layer 131 is the first It protrudes toward the solder layer 163 with respect to the central portion of the base metal layer 141. Similarly, since the second passivation layer 132 is disposed on the peripheral portion of the second pad electrode 122, the peripheral portion of the second base metal layer 142 positioned above the second passivation layer 132 is formed on the second base layer. The metal layer 142 protrudes toward the solder layer 163 side with respect to the central portion. The protruding shape of the peripheral portion of the base metal layers 141 and 142 is reflected in the protruding shape of the peripheral portions 151a and 152a of the barrier layers 151 and 152 described later.

  For example, the first and second base metal layers 141 and 142 may be Au layers.

  The first barrier layer 151 is disposed on the first base metal layer 141 so as to cover the first base metal layer 141. The first barrier layer 151 prevents the solder layer 163 from diffusing to the first base metal layer 141 side. The second barrier layer 152 is disposed on the second base metal layer 142 so as to cover the second base metal layer 142. The second barrier layer 152 prevents the solder layer 163 from diffusing to the second base metal layer 142 side. The first and second barrier layers 151 and 152 may be Ni layers, for example.

  For example, the solder layer 163 may be made of a eutectic alloy containing a low melting point material such as Sn or Pb as a component. Specifically, the solder layer 163 may be SnAg, SnCu, SnPb, or the like.

  The first alloy layer 161 includes a component of the first barrier layer 151 and a component of the solder layer 163. Specifically, the first alloy layer 161 is formed when the first barrier layer 151 (first semiconductor substrate 11) and the second barrier layer 152 (second semiconductor substrate 12) are joined by the solder layer 163. This is a layer formed by alloying part of the barrier layer 151 and part of the solder layer 163. Similarly, the second alloy layer 162 includes a component of the second barrier layer 152 and a component of the solder layer 163. Specifically, the second alloy layer 162 includes a part of the second barrier layer 152 and a part of the solder layer 163 when the first barrier layer 151 and the second barrier layer 152 are joined by the solder layer 163. Is a layer formed by alloying.

  The material of the first alloy layer 161 and the material of the second alloy layer 162 may be the same. For example, the first and second alloy layers 161 and 162 may be an alloy layer of solder and Ni. When the first barrier layer 151 and the second barrier layer 152 are different from each other in material, the first alloy layer 161 and the second alloy layer 162 are also different from each other in material.

  The first barrier layer 151 protrudes toward the solder layer 163 at the peripheral edge (peripheral part) 151a. That is, the first barrier layer 151 is recessed on the first semiconductor substrate 11 side in the central portion 151b inside the peripheral edge portion 151a. In other words, the first barrier layer 151 has a concave step shape that is recessed toward the first semiconductor substrate 11 at the central portion 151b.

  The first barrier layer 151 is disposed above the first passivation layer 131 at the peripheral edge portion 151a. That is, the peripheral portion 151 a of the first barrier layer 151 covers the peripheral portion of the first base metal layer 141 protruding toward the solder layer 163 side. By covering the peripheral edge portion of the first base metal layer 141, the peripheral edge portion 151a of the first barrier layer 151 can protrude toward the solder layer 163 side even if it is not thicker than the central portion 151b. Therefore, the protruding shape of the peripheral edge portion 151a can be easily formed without requiring adjustment of the thickness of the first barrier layer 151.

  The second barrier layer 152 protrudes toward the solder layer 163 at the peripheral edge (peripheral part) 152a. That is, the second barrier layer 152 is recessed toward the second semiconductor substrate 12 in the central portion 152b inside the peripheral edge portion 152a. In other words, the second barrier layer 152 has a concave step shape that is recessed toward the second semiconductor substrate 12 at the central portion 152b.

  The second barrier layer 152 is arranged above the second passivation layer 132 (downward in FIG. 1) at the peripheral edge 152a. That is, the peripheral edge 152a of the second barrier layer 152 covers the peripheral edge of the second base metal layer 142 protruding toward the solder layer 163 side. By covering the peripheral portion of the second base metal layer 142, the peripheral portion 152a of the second barrier layer 152 can protrude toward the solder layer 163 side even if the thickness is not thicker than the central portion 152b. Therefore, it is possible to easily form the protruding shape of the peripheral portion 152a.

  From the viewpoint of sufficiently ensuring the thickness of the solder layer 163, the distance d1 between the central portion 151b of the first barrier layer 151 and the central portion 152b of the second barrier layer 152 is preferably 8 μm or more. Further, from the viewpoint of suppressing the distance between the first semiconductor substrate 11 and the second semiconductor substrate 12 (that is, the thickness of the semiconductor device 1), the peripheral portion 151a of the first barrier layer 151 and the peripheral portion 152a of the second barrier layer 152 are used. Is preferably less than 8 μm.

  If the bonding layer 16 includes only the alloy layers 161 and 162, it is difficult to appropriately bond the first semiconductor substrate 11 and the second semiconductor substrate 12. This is because the alloy layers 161 and 162 are those in which the solder layer 163 is consumed by alloying with the barrier layers 151 and 152, and voids and cracks are generated during alloying. This is because the mechanical and mechanical connection functions are deteriorated. Also, if the surfaces of the barrier layers 151 and 152 are both flat, in order to secure a sufficient thickness (amount) of the solder layer 163 between the barrier layers 151 and 152, the barrier layers 151 and 152 It is necessary to widen the interval. However, it is difficult to suppress the thickness of the semiconductor device 1 by increasing the distance between the barrier layers 151 and 152. Further, when the thickness of the solder layer 163 increases, the solder layer 163 flows out from between the barrier layers 151 and 152 and reaches the other solder layer 163 in the surrounding area, thereby increasing a risk that a short circuit between the pad electrodes 121 occurs.

  On the other hand, in the present embodiment, the solder layer 163 that has not been consumed by alloying can be left between the first alloy layer 161 and the second alloy layer 162, so that the first semiconductor substrate 11 and the second alloy layer The semiconductor substrate 12 can be appropriately joined (electrically and mechanically connected). In the present embodiment, the central portions 151b and 152b of the barrier layers 151 and 152 are recessed, so that even if the interval d2 between the peripheral portions 151a and 152a of the barrier layers 151 and 152 is reduced, the central portion A sufficiently thick solder layer 163 can be stably held between 151b and 152b.

  Therefore, according to the semiconductor device 1 of the present embodiment, the thickness of the semiconductor device 1 can be suppressed, and the semiconductor substrates 11 and 12 can be bonded appropriately.

  FIG. 2 is a diagram showing a state of occurrence of voids V (see FIG. 1) in the solder layer 163 according to the depth d3 of the recesses in the central portions 151b and 152b of the barrier layers 151 and 152 in the first embodiment. is there. Note that “◯” in FIG. 2 indicates that no void V was generated in the solder layer 163. “Δ” in FIG. 2 indicates that a void V is generated in a part of the solder layer 163. “X” in FIG. 2 indicates that a void V has occurred in most of the solder layer 163. As shown in FIG. 2, when the depth d3 is 4.0 μm, a void V may be generated in a part of the solder layer 163 between the central portions 151b and 152b. Further, when the depth d3 is 4.2 μm or more, voids may occur in most of the solder layer 163 between the central portions 151b and 152b, and cracks may occur. On the other hand, when the depth d3 is 3.5 μm or less, voids and cracks hardly occur. Therefore, from the viewpoint of suppressing voids and cracks, the depth d3 of the recesses in the central portions 151b and 152b of the barrier layers 151 and 152 is preferably 3.5 μm or less.

  Next, a method for manufacturing the semiconductor device 1 having the above configuration will be described. FIG. 3 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device 1 of FIG. Specifically, FIG. 3A is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 before joining with the solder layer 163. FIG. 3B is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 after being joined by the solder layer 163.

  First, as shown in FIG. 3A, the semiconductor substrates 11 and 12 having the solder layer 163 formed on the surfaces 151c and 152c of the barrier layers 151 and 152 are opposed to each other in a reflow furnace (not shown). Note that the solder layer 163 may be formed by, for example, an electrolytic plating process. The barrier layers 151 and 152 and the solder layer 163 may constitute micro bumps.

  Next, in a state where the solder layers 163 formed on the barrier layers 151 and 152 are in contact with each other, both the solder layers 163 are heated and melted. Then, the melted solder layer 163 is cooled and solidified, thereby joining the semiconductor substrates 11 and 12 with the solder layer 163 as shown in FIG. 3B.

  At this time, a part of the first barrier layer 151 and a portion of the solder layer 163 on the first barrier layer 151 side are alloyed into the first alloy layer 161. Further, a part of the second barrier layer 152 and a portion of the solder layer 163 on the second barrier layer 152 side are alloyed into the second alloy layer 162. On the other hand, since the central portions 151b and 152b of the barrier layers 151 and 152 are recessed, the thickness of the solder layer 163 between the central portions 151b and 152b is thick. Even if the solder layer 163 between the central portions 151b and 152b is partially alloyed with the barrier layers 151 and 152, the remaining portion is not alloyed and can maintain a sufficient thickness. Further, it is possible to avoid the solder layer 163 from flowing out to the side of the first barrier layer 151 and reaching the peripheral first pad electrode 121, so that a short circuit between the adjacent first pad electrodes 121 can be prevented.

  As described above, according to the manufacturing method of the semiconductor device 1 of the first embodiment, the central portions 151b and 152b of the barrier layers 151 and 152 are recessed (that is, the peripheral portion 151a of the barrier layers 151 and 152). , 152a is protruded), the thickness of the semiconductor device 1 can be suppressed, and the semiconductor substrates 11 and 12 can be appropriately bonded to each other.

(First modification)
Next, an example of the semiconductor device 1 in which the surface of the second barrier layer 152 is flat will be described as a first modification of the first embodiment. In the description of the first modification, the same reference numerals are used for the components corresponding to those in FIG. FIG. 4 is a schematic cross-sectional view of the method for manufacturing the semiconductor device 1 showing a first modification of the first embodiment. Specifically, FIG. 4A is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 before joining by the solder layer 163. FIG. FIG. 4B is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 after being joined by the solder layer 163.

  As shown in FIG. 4, in the semiconductor device 1 of the first modified example, the surface 152c of the second barrier layer 152 is flat (that is, the peripheral portion does not protrude) compared to the semiconductor device 1 of FIG. The point is different. Further, as shown in FIG. 4A, in the first modification, a high conductivity metal such as Au is used instead of the solder layer 163 on the surface 152c of the second barrier layer 152 before joining the semiconductor substrates 11 and 12. Layer 17 is provided.

  In the first modification, the central portion 151b of the first barrier layer 151 is recessed. For this reason, as shown in FIG. 4B, after bonding the semiconductor substrates 11 and 12, the gap between the barrier layers 151 and 152 is suppressed, and alloying is performed between the central portions 151b and 152b of the barrier layers 151 and 152. A sufficiently thick solder layer 163 that has not been consumed can be secured.

  Therefore, also in the first modification, the thickness of the semiconductor device 1 can be suppressed, and the semiconductor substrates 11 and 12 can be appropriately bonded to each other. In the first modification, the conductivity of the solder layer 163 can also be improved by including the component of the metal layer 17 having a high conductivity in the solder layer 163. Further, since the metal layer 17 is thinner than the solder layer 163, the thickness of the semiconductor device 1 can be further suppressed.

(Second modification)
Next, an example of the semiconductor device 1 in which the passivation layers 131 and 132 are formed thick will be described as a second modification of the first embodiment. In the description of the second modification, the same reference numerals are used for the components corresponding to those in FIG. FIG. 5 is a schematic cross-sectional view of the method for manufacturing the semiconductor device 1 showing a second modification of the first embodiment. Specifically, FIG. 5A is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 before joining with the solder layer 163. FIG. 5B is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 after being joined by the solder layer 163.

  As shown in FIG. 5, the semiconductor device 1 of the second modification is different from the semiconductor device 1 of FIG. 1 in that the passivation layers 131 and 132 are formed thick.

  Also in the second modification, the barrier layers 151 and 152 are recessed in the central portions 151b and 152b. For this reason, as shown in FIG. 5B, after bonding the semiconductor substrates 11 and 12, the distance between the barrier layers 151 and 152 is suppressed, and between the central portions 151 b and 152 b of the barrier layers 151 and 152, It is possible to secure a solder layer 163 having a sufficient thickness that is not consumed by the conversion. Therefore, also in the second modification, the thickness of the semiconductor device 1 can be suppressed, and the semiconductor substrates 11 and 12 can be appropriately bonded to each other.

(Third Modification)
Next, as a third modification of the first embodiment, an example of the semiconductor device 1 in which the first modification and the second modification are combined will be described. In the description of the third modification, the same reference numerals are used for the components corresponding to those in FIG. FIG. 6 is a schematic cross-sectional view of the method for manufacturing the semiconductor device 1 showing a third modification of the first embodiment. Specifically, FIG. 6A is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 before joining with the solder layer 163. FIG. 6B is a schematic cross-sectional view showing the semiconductor substrates 11 and 12 after being joined by the solder layer 163.

  As shown in FIG. 6, the semiconductor device 1 of the third modification example has a flat surface 152c of the second barrier layer 152 and thicker passivation layers 131 and 132 than the semiconductor device 1 of FIG. The point is different. Further, as shown in FIG. 6A, in the third modification, a metal having a high conductivity such as Au is used instead of the solder layer 163 on the surface 152c of the second barrier layer 152 before joining the semiconductor substrates 11 and 12. Layer 17 is provided. That is, the third modification is a combination of the first modification and the second modification.

  According to the 3rd modification, there can exist both the effects of the 1st modification and the 2nd modification.

(Second Embodiment)
Next, as a second embodiment, an embodiment of a semiconductor device 1 having a through electrode will be described. In the description of the second embodiment, the same reference numerals are used for the components corresponding to the first embodiment, and a duplicate description is omitted. FIG. 7 is a schematic cross-sectional view of the semiconductor device 1 according to the second embodiment.

  As shown in FIG. 7, the semiconductor device 1 of the second embodiment includes first and second through electrodes 1501 and 1502 as first and second metal layers instead of the barrier layers 151 and 152. The first through electrode 1501 penetrates the first semiconductor substrate 11. The second through electrode 1502 penetrates the second semiconductor substrate 12. Barrier metal films 1503 and 1504 are formed between the through electrodes 1501 and 1502 and the semiconductor substrates 11 and 12.

  As shown in FIG. 7, the first through electrode 1501 protrudes toward the solder layer 163 at the peripheral edge (peripheral part) 1501 a. That is, the first through electrode 1501 is recessed on the first semiconductor substrate 11 side in the central portion 1501b inside the peripheral edge portion 1501a. In other words, the first through electrode 1501 has a concave step shape that is recessed toward the first semiconductor substrate 11 at the central portion 1501b.

  The second through electrode 1502 protrudes toward the solder layer 163 side at the peripheral edge (peripheral part) 1502a. That is, the second through electrode 1502 is recessed on the second semiconductor substrate 12 side in the central portion 1502b inside the peripheral edge portion 1502a. In other words, the second through electrode 1502 has a concave step shape that is recessed toward the second semiconductor substrate 12 at the central portion 1502b.

  According to the semiconductor device 1 of the second embodiment, even if the interval between the peripheral portions 1501a and 1502a of the through electrodes 1501 and 1502 is narrowed, an alloy is formed between the central portions 1501b and 1502b of the through electrodes 1501 and 1502. It is possible to secure a solder layer 163 having a sufficient thickness that is not consumed by the conversion. Therefore, according to the second embodiment, in the three-dimensional mounting using the through electrodes 1501 and 1502, the thickness of the semiconductor device 1 can be suppressed and the semiconductor substrates 11 and 12 can be appropriately bonded to each other. In the second embodiment, one of the through electrodes 1501 and 1502 may be changed to an electrode other than the through electrodes 1501 and 1502 such as a pad electrode.

(Modification)
Next, as a modification of the second embodiment, an example of three-dimensional mounting using through silicon vias (TSV) will be described. In the description of this modification, the same reference numerals are used for the components corresponding to those in FIG. FIG. 8 is a schematic cross-sectional view of the semiconductor device 1 showing a modification of the second embodiment.

  As shown in FIG. 8, the semiconductor device 1 according to the present modification includes a BGA (Ball Grid Array) substrate 101 and a plurality of layers (3, 3) mounted (bonded and connected) on the BGA substrate 101 via bumps 107 and 108. And two or more) silicon chips 102, 103_1 to 6, 104 (semiconductor substrate). The silicon chips 102, 103 </ b> _ <b> 1 to 6, 104 are stacked so as to have a gap in the thickness direction D of the semiconductor device 1. Each silicon chip 102, 103_1 to 6, 104 may be provided with a wiring or a semiconductor element (device) (not shown).

  An IC chip 106 is formed on the upper surface of the BGA substrate 101. On the other hand, bumps 105 are formed on the lower surface of the BGA substrate 101.

  The lowermost silicon chip 102 (hereinafter also referred to as a connection wiring chip) among the plurality of layers of silicon chips includes a wiring 109 for connection to the BGA substrate 101 on the lower surface. The wiring 109 is connected to the upper surface of the BGA substrate 101 via the first bump 107. The wiring 109 is connected to the IC chip 106 formed on the upper surface of the BGA substrate 101 via the second bump 108. Moreover, the connection wiring chip 102 is penetrated by TSV15_1.

  A plurality of upper-layer silicon chips 103_1, 103_2, 103_3, 103_4, 103_5, and 103_6 (hereinafter also referred to as intermediate chips) of the connection wiring chip 102 are positioned between the upper-layer silicon chip and the lower-layer silicon chip (intermediate). To do. Each intermediate chip 103_1-6 is penetrated by TSV15_2-7.

  The uppermost silicon chip 104 (hereinafter also referred to as a base chip) does not include a TSV.

  TSVs that are adjacent in the thickness direction D (up and down) are joined by a joining layer 16 similar to that in FIG.

  Of the TSVs adjacent in the thickness direction D, the TSV on the lower layer side is an example of the first through electrode 1501 shown in FIG. On the other hand, the TSV on the upper layer side is an example of the second through electrode 1502. For example, TSV15_2 is the second through electrode 1502 for the lower layer TSV15_1 and the first through electrode 1501 for the upper layer TSV15_3.

The silicon chip penetrated by the lower TSV is an example of the first semiconductor substrate 11, and the silicon chip penetrated by the upper TSV is an example of the second semiconductor substrate 12.
That is, the first semiconductor substrate 11 and the second semiconductor substrate 12 are any two adjacent semiconductor substrates among three or more semiconductor substrates (silicon chips 102, 101_1 to 6, 104). For example, the silicon lip 103_1 is the second semiconductor substrate 12 with respect to the silicon chip 102 in the lower layer (one in the thickness direction D) and the first semiconductor substrate 11 with respect to the silicon chip 103_2 in the upper layer (the other in the thickness direction D). It is.

  A resin 1010 is provided between adjacent silicon chips. The space between the resins 1010 is filled with a sealing resin 1010-2.

  Such a semiconductor device 1 can be mounted on a circuit board (not shown) via bumps 105.

  According to the semiconductor device 1 of the present modified example, the solder layer 163 having a sufficient thickness that is not consumed by alloying is formed between the central portions of the TSVs 15 even when the intervals between the peripheral portions of the adjacent TSVs 15 are narrowed. It can be secured. Therefore, according to this modification, in the three-dimensional mounting using TSV, the thickness of the semiconductor device 1 can be suppressed and the silicon chips can be connected appropriately.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 1st semiconductor substrate 12 2nd semiconductor substrate 151 1st barrier layer 152 2nd barrier layer 161 1st alloy layer 162 2nd alloy layer 163 Solder layer

Claims (7)

First and second semiconductor substrates facing each other;
A first metal layer provided on the first semiconductor substrate and facing the second semiconductor substrate;
A second metal layer provided on the second semiconductor substrate and facing the first metal layer;
A third metal layer disposed between the first metal layer and the second metal layer;
A first alloy layer disposed between the first metal layer and the third metal layer and including a component of the first metal layer and a component of the third metal layer;
A second alloy layer disposed between the second metal layer and the third metal layer and including a component of the second metal layer and a component of the third metal layer;
At least one of the first and second metal layers is a semiconductor device that protrudes toward the third metal layer at the periphery thereof. A pad electrode disposed on at least one of a surface of the first semiconductor substrate facing the second semiconductor substrate and a surface of the second semiconductor substrate facing the first semiconductor substrate;
An insulating layer disposed on a peripheral edge of the pad electrode;
A base metal layer disposed on a central portion of the pad electrode and on the insulating layer,
The third metal layer is a solder layer;
At least one of the first and second metal layers is a barrier layer disposed on the base metal layer;
The semiconductor device according to claim 1, wherein the barrier layer protrudes toward the third metal layer at a peripheral edge portion thereof.   The semiconductor device according to claim 2, wherein the barrier layer is disposed above the insulating layer at a peripheral portion thereof. The third metal layer is a solder layer;
2. The semiconductor device according to claim 1, wherein at least one of the first and second metal layers is a through electrode penetrating the first or second semiconductor substrate.   The semiconductor device according to claim 1, wherein at least one of the first and second metal layers contains Ni. Comprising three or more semiconductor substrates facing each other;
The semiconductor device according to claim 1, wherein the first and second semiconductor substrates are any two adjacent semiconductor substrates among the three or more semiconductor substrates. Bonding a first semiconductor substrate having a first metal layer and a second semiconductor substrate having a second metal layer with a third metal layer disposed between the first metal layer and the second metal layer;
A first alloy layer obtained by alloying a part of the first metal layer with a portion of the third metal layer on the first metal layer side, a part of the second metal layer, and the second metal layer; Forming a semiconductor device having a second alloy layer alloyed with a portion of the third metal layer on the side, and the remainder of the third metal layer,
At least one of the first metal layer and the second metal layer protrudes toward the third metal layer at the peripheral edge thereof.

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