TW201703160A - Dual-side exposed package and a manufacturing method - Google Patents

Abstract

A dual-side exposed package and a manufacturing method are disclosed. A chip having source and gate electrodes on top surface is flipped and attached on a lead frame. A first package layer is deposited encapsulating the chip and lead frame. The first package layer and the chip are ground reducing their thicknesses. A metal layer is deposited from the back of the chip followed by attaching a metal clip on back of ground chip. A second package layer is deposited on top surface of lead frame and then is ground exposing the meal clip at the backside of the chip, while the bottom surface of the lead frame is also exposed. The final device is separated from the lead frame by cutting the lead frame and the second package layer, which includes a thinned chip with source, gate, and drain exposed, thus reducing the resistance and improving the thermal performance.

Description

Double-sided exposed package structure of ultra-thin chip and manufacturing method thereof

The present invention relates to a double-sided exposed package structure of an ultra-thin chip and a method of fabricating the same.

For power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), impedance and thermal performance are two very important performance parameters. To improve impedance and thermal performance, it is common practice to use thinner chips in the package structure and The source or drain of the FET is exposed outside the package structure, but when the wafer is ground to less than 200 μm, it is easy to crack and chip during the grinding and subsequent cutting and packaging processes, so it is necessary to develop A new packaging process for semiconductor wafer packages with low impedance and high thermal performance.

The invention provides a double-sided exposed package structure of an ultra-thin chip and a manufacturing method thereof, which adopts a thinned chip structure, reduces resistance, and exposes a source, a gate and a drain of a semiconductor component to a molding compound. This double-sided exposed package structure greatly improves the heat dissipation performance of the components.

In order to achieve the above object, the present invention provides a method for manufacturing a double-sided exposed package structure of an ultra-thin chip, comprising the steps of: preparing a chip of a top mask source electrode and a gate electrode; providing a wire frame for pouring the chip The chip is bonded to the top surface of the lead frame; the first molding compound is injected from the top surface of the lead frame to mold the chip on the lead frame; the first molding compound and the back surface of the chip are ground, and the molding compound and the chip are thinned. Thickness, exposing the back side of the chip to the top of the first molding compound; depositing a mask layer on the top surface of the lead frame, the mask layer not covering the area of the back surface of the chip; depositing a back metal layer on the back side of the chip; Attaching the back side of the chip; injecting a second molding compound from the top surface of the lead frame, performing a top exposed molding on the lead frame and the chip, exposing the clip on the back side of the connecting chip to the top of the second molding compound, exposing the bottom surface of the lead frame At the bottom of the second molding compound; the lead frame and the second molding compound are cut to form a plurality of double-sided exposed semiconductor package structures.

Depositing the mask layer on the top surface of the lead frame covers all other areas except the back side of the chip, and the step of removing the mask layer after the step of depositing a back metal layer on the back side of the chip.

Before the step of cutting the lead frame and the second molding compound, the step of tin-plating the surface of the lead frame exposed by the plastic seal is further included.

The step of preparing a chip further comprises the steps of: forming a source electrode and a gate electrode of the chip on a top surface of the wafer including the plurality of chips; grinding the back surface of the wafer, thinning the thickness of the wafer; cutting the wafer, and cutting the chip Separated from the wafer.

The thickness of the source metal layer and the gate metal layer is 10-20 um.

The back side of the wafer is ground and the thickness of the wafer is ground to 300-400 um.

The lead frame is a flat plate structure, and the lead frame comprises a plurality of base island regions, wherein the base island region comprises a source connection region and a gate connection region, and a source connection region side and a gate connection region respectively The bungee connection area on one side.

The first molding compound injected from the top surface of the lead frame encloses the chip, and the drain connection region is on the periphery of the first molding compound, and the wire clip connects the back surface of the chip and the drain connection region.

The thickness of the first molding compound is 450 to 500 um from the top surface of the wire frame and the die bond.

The back metal layer deposited on the back side of the chip is a titanium nickel silver alloy, and the back metal layer is in electrical contact with the drain region of the back side of the chip to form a drain electrode of the chip.

The back metal layer has a thickness of 20 um.

The first molding compound and the second molding compound are epoxy molding compounds.

The bridge portion of the clip exposed to the second molding compound forms a drain of the double-sided exposed package structure of the ultra-thin chip, and the drain connection region of the lead frame exposed to the second molding compound forms a double-sided exposed package of the ultra-thin chip The drain of the structure, the source connection region of the lead frame exposed to the second molding compound forms the source of the double-sided exposed package structure of the ultra-thin chip, and the gate connection region of the lead frame exposed to the second molding compound forms an ultra-thin The two sides of the chip expose the gate of the package structure.

Grinding the first molding compound and the back surface of the chip, grinding the thickness of the first molding compound to less than or equal to 50 um, the thickness of the first molding compound is equal to the thickness of the chip plus the thickness of the source metal layer or the gate metal layer on the chip .

The invention also provides a double-sided exposed package structure of an ultra-thin chip, comprising: a chip, the top surface of the chip is provided with a source metal layer and a gate metal layer, and the back surface of the chip is provided with a back metal layer, the thickness of the chip The thickness of the top and back metal layers of the chip is less than or equal to 70 um; a lead frame comprising a plurality of island regions, the base island region comprising a source connection region and a gate connection region, and respectively located at a drain connection region on one side of the source connection region and one side of the gate connection region, the source connection region is bonded to the source metal layer on the top surface of the chip, and the source of the gate connection region and the top surface of the chip a metal layer is bonded; the first molding compound covers the chip, and the drain connection region is on the periphery of the first molding compound, wherein the back surface of the chip is exposed to the first molding compound; the first clamping member, the clip is a bridge structure, the bridge portion of the clip contacts the back metal layer on the back side of the chip, the bridge portion of the clip connects the drain connection region on the lead frame; the second molding compound, the second molding compound covers the chip, a plastic sealing material, clamp And a lead frame, wherein the deck portion of the clip is exposed to the second molding compound, and the source connection region, the gate connection region and the drain connection region of the lead frame are exposed to the second molding compound.

Electroplating nickel/gold or electroplated copper pillars on the top surface of the wafer to form a source metal layer and a gate metal layer on the chip, the source metal layer being in electrical contact with the source region on the top surface of the chip to form a source of the chip The electrode, the gate metal layer is in electrical contact with the gate region on the top surface of the chip to form a gate electrode of the chip, and the source metal layer and the gate metal layer have a thickness of 10-20 um.

The back metal layer is a titanium nickel silver alloy, and the back metal layer is in electrical contact with the drain region of the back surface of the chip to form a drain electrode of the chip, and the back metal layer has a thickness of 20 μm.

The wire frame is a flat plate structure, and the wire frame is made of a conductive material.

The thickness of the first molding compound is less than or equal to 50 um, and the thickness of the first molding compound is equal to the thickness of the chip plus the thickness of the source metal layer or the gate metal layer on the chip.

The bridge portion of the clip exposed to the second molding compound forms a drain of the double-sided exposed package structure of the ultra-thin chip, and the drain connection region of the lead frame exposed to the second molding compound forms a double-sided exposed package of the ultra-thin chip The drain of the structure, the source connection region of the lead frame exposed to the second molding compound forms the source of the double-sided exposed package structure of the ultra-thin chip, and the gate connection region of the lead frame exposed to the second molding compound forms an ultra-thin The two sides of the chip expose the gate of the package structure.

The invention adopts a thinned chip structure, reduces the resistance, and exposes the source, the gate and the drain of the semiconductor component to the outside of the molding compound. The double-sided exposed package structure greatly improves the heat dissipation of the component. performance.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be specifically described based on the first to twelfth drawings.

The invention provides a method for manufacturing a double-sided exposed package structure of an ultra-thin chip, comprising the steps of: preparing a chip, a top mask source electrode and a gate electrode of the chip; providing a lead frame, and flipping the chip by flip chip Bonding to the top surface of the wire frame; plasticating the chip on the wire frame; grinding the plastic compound and the back side of the chip, thinning the thickness of the molding compound and the chip, exposing the back side of the chip; depositing a mask on the top surface of the wire frame a photo resist, the mask layer covers all other areas except the back side of the chip; a back metal layer is deposited on the back side of the chip; the back side of the chip and the lead frame are connected by wire clip attachment; and the molding compound is injected from the top surface of the lead frame a top exposed plastic package of the lead frame and the chip, exposing the clip connecting the back surface of the chip and the lead frame to the top of the molding compound, exposing the bottom surface of the lead frame to the bottom of the molding compound; and forming a lead frame of the plastic molded outer envelope formed by the plastic sealing Tin plating on the surface; (this is an optional step to prevent oxidation of the exposed portion of the lead frame and SMT (surface mounting technology) mount).

The lead frame and the molding compound are cut to form a plurality of double-sided exposed semiconductor package structures.

The step of preparing a chip further comprises the steps of: forming a source electrode and a gate electrode of the chip on a top surface of the wafer including the plurality of chips; grinding the back surface of the wafer, thinning the thickness of the wafer; cutting the wafer, and removing the chip from the wafer Separation.

As shown in FIG. 1, the semiconductor wafer 1 includes a plurality of dies 11, and a source region (not shown) and a gate region (not shown) of the chip 11 are located on the top surface of the chip. The drain region (not shown) of the chip 11 is located on the bottom surface (back surface) of the chip, and nickel/gold (Ni/Au) or electroplated copper pillar (Cu pillar) is electroplated on the top surface of the wafer 1 to form a source metal on the chip. The layer 101 and the gate metal layer 102, the source metal layer 101 is in electrical contact with the source region of the chip to form the source electrode of the chip 11, and the gate metal layer 102 is in electrical contact with the gate region of the chip to form the gate electrode of the chip 11. The thickness of the source metal layer 101 and the gate metal layer 102 formed by electroplating is greater than 5 um, preferably about 10-20 um. After the plating is completed, the bottom surface of the wafer 1 is ground, and the thickness of the wafer 1 is ground to about 300 to 400 um. As shown in Fig. 2, the wafer 1 is diced into individual chips 11, and the thickness of the individual chips 11 is approximately 300 to 400 um.

As shown in FIG. 3, the lead frame 2 is made of a conductive material, and the lead frame 2 is a flat plate structure having a top surface 201 and a bottom surface 202, and the lead frame includes a plurality of base island regions 21 connected together. The array, base island region 21 includes a source connection region 211 and a gate connection region 212. In the preferred embodiment shown in FIG. 3, the island region 21 further includes a drain connection region 213 on the side of the source connection region 211 and the gate connection region 212, respectively. In other preferred embodiments, the base island region of the lead frame 2 may be selected to not provide the drain connection region 213 on the side of the source connection region 211 and the gate connection region 212, and the position of the drain connection region is made. Leave blank (not shown).

As shown in FIG. 4, the chip 11 is bonded to the island region 21 on the lead frame 2 by means of a flip chip, and the source metal layer 101 on the chip 11 is bonded to the lead frame 2. The source connection region 211 bonds the gate metal layer 102 on the chip 11 to the gate connection region 212 on the lead frame 2.

As shown in FIG. 5, the chip on the lead frame is plastic-sealed, the formed molding compound 3 is wrapped around the chip 11, and the drain connection region 213 is on the periphery of the first molding compound 3. The thickness of the first molding compound 3 is about 450~500 um from the top surface of the wire frame and the bonding of the chip to completely cover the chip, and the first molding compound 3 is generally an epoxy molding compound.

As shown in FIG. 6, the first molding compound 3 and the chip 11 are ground, and the thickness of the first molding compound 3 is ground to about 50 um (or less than 50 um) to expose the drain region on the back surface of the chip 11, and the first after grinding. The thickness of the molding compound 3 is equal to the thickness of the polished chip 11 plus the thickness of the source metal layer 101 / gate metal layer 102 on the chip 11 from the top surface of the wire frame bonded to the chip, such as when the chip 11 is on the chip 11. The thickness of the source metal layer 101 / gate metal layer 102 is 20 um, the thickness of the chip 11 after polishing is 30 um, and the thickness of the first molding compound 3 is 50 um from the top surface of the bonding of the lead frame and the chip = chip The thickness of 11 is 30 um + the thickness of the source metal layer 101 / gate metal layer 102 on the chip 11 is 20 um. Transferring the polishing process from a larger area wafer to a smaller area chip greatly reduces the wafer cracking caused by uneven pressure applied during the grinding process, and an ultra-thin chip of less than 50 μm can be obtained during the grinding process. The first molding compound 3 can protect the chip 11 from cracking and chipping.

As shown in FIG. 7, the mask layer 4 covers all other areas of the lead frame 2 except the drain region of the back surface of the chip 11. The mask layer 4 may be made of a photoresist, and the mask layer 4 serves to ensure In the subsequent metal deposition process, only the back metal layer is deposited on the back portion of the chip 11, and after the deposition of the back metal layer 103 is completed, the mask layer 4 is removed.

As shown in FIG. 10, a back metal layer 103 is deposited on the back surface of the chip 11, and the back metal layer 103 is a titanium (Ti) nickel (Ni) silver (Ag) alloy having a thickness of more than 5 um, preferably 10-20 um thick. Left and right, the back metal layer 103 is in electrical contact with the drain region of the back surface of the chip to form the drain electrode of the chip 11.

As shown in FIGS. 8 and 10, the back surface of the chip 11 and the lead frame 2 are connected by a clip 5, which is a bridge structure, and the bridge portion 501 of the clip 5 contacts the back metal layer on the back side of the chip 11. The leg portion 502 of the clip 5 is connected to the drain connection region 213 on the lead frame 2. An array of clips formed by a plurality of clips 5 can be mounted on the corresponding array of lead frames 2 carrying the chips 11 on which the back metal layer 103 has been plated to improve the efficiency of the package. The clip 5 shown in Fig. 10 has two leg portions 502 that are symmetrical with respect to the deck portion 501, and a clip for a single-sided bridge can also be used. Also. In other preferred embodiments, the base region of the lead frame 2 is not provided with a drain connection region 213 on the side of the source connection region 211 and the gate connection region 212. When the position of the drain connection region is left blank (not shown), the leg portion 502 of the clamp 5 extends to a plane (not shown) that is coplanar with the bottom surfaces of the source connection region 211 and the gate connection region 212. As shown in FIG. 9, the second molding compound 6 is injected from the top surface of the lead frame 2, and the lead frame 2 and the chip 11 are subjected to a top exposed molding, which will connect the back surface of the chip 11 and the bridge portion of the wire clamp 5 of the lead frame 2. 501 is exposed on the top of the second molding compound 6, and the bottom surface of the lead frame 2 is exposed at the bottom of the second molding compound 6.

As shown in FIG. 10, according to the method of FIGS. 1 to 9, the present invention provides a double-sided exposed package structure of an ultra-thin chip, comprising: a chip 11, a top surface of which is provided with a source metal layer 101 and a gate metal layer 102, the back surface of the chip 11 is provided with a back metal layer 103, the thickness of the chip plus the thickness of the top and back metal layers of the chip is less than or equal to 70um; a wire frame 2, the wire frame 2 comprises a plurality of connections Together with the base island region 21 (shown in FIG. 3), the base island region 21 includes a source connection region 211 and a gate connection region 212, and a source connection region 211 side and a gate connection region 212, respectively. a side drain connection region 213, a source connection region 211 is bonded to the source metal layer 101 on the top surface of the chip, and a gate connection region 212 is bonded to the source metal layer 102 on the top surface of the chip; the first molding compound 3, the first A molding compound 3 covers the chip 11, and the drain connection region 213 is on the periphery of the first molding compound 3, wherein the back surface of the chip 11 is exposed to the first molding compound 3; a wire clamp 5, which is a bridge structure. The bridge portion 501 of the clip 5 contacts the back metal layer 103 on the back side of the chip 11, the clip 5 The bridge leg portion 502 is connected to the drain connection region 213 on the lead frame 2; the second molding compound 6 covers the chip 11, the second molding compound 3, the clip 5 and the lead frame 2, wherein the line The deck portion 501 of the clip 5 is exposed to the second molding compound 6, and the source connection region 211, the gate connection region 212, and the drain connection region 213 of the lead frame 2 are exposed to the second molding compound 6.

As shown in FIGS. 11 and 12, the bridge portion 501 of the clip 5 exposed to the second molding compound 6 forms the drain 703 of the double-sided exposed package structure 7 of the ultra-thin chip, exposed to the second molding compound 6 The drain connection region 213 of the lead frame 2 (which connects the leg portion 502 of the clip 5) forms the drain 703 of the double-sided exposed package structure 7 of the ultra-thin chip, exposed to the lead frame 2 of the second molding compound 6 The source connection region 211 forms the source 701 of the double-sided exposed package structure 7 of the ultra-thin chip, and the gate connection region 212 of the lead frame 2 exposed to the second molding compound 6 forms the double-sided exposed package structure 7 of the ultra-thin chip. Gate 702.

The double-sided exposed package structure of the ultra-thin chip provided by the invention exposes the source, the gate and the drain to the outside of the molding compound, and the double-sided exposed package structure greatly improves the heat dissipation performance of the component, and A thinned chip structure is used to reduce the resistance.

Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the description Various modifications and alterations of the present invention will be apparent to those skilled in the <RTIgt; Therefore, the scope of the invention should be limited by the scope of the appended claims.

1‧‧‧ wafer
101‧‧‧ source metal layer
102‧‧‧ gate metal layer
103‧‧‧Back metal layer
11‧‧‧chip
2‧‧‧ lead frame
201‧‧‧ top surface
202‧‧‧ bottom
21‧‧‧Base Island District
211‧‧‧Source connection area
212‧‧‧gate connection area
213‧‧‧汲 connection area
3‧‧‧First molding compound
4‧‧‧mask layer
5‧‧‧Clamps
501‧‧‧ Bridge section
502‧‧‧ Bridge foot section
6‧‧‧Second molding compound
701‧‧‧ source
702‧‧‧ gate
703‧‧‧汲polar

Figure 1 is a schematic illustration of plating a source electrode and a gate electrode on a wafer. Figure 2 is a schematic diagram of a single chip. Figure 3 is a schematic illustration of a lead frame. Figure 4 is a schematic illustration of the flip chip bonding of the chip to the lead frame. Figure 5 is a schematic illustration of the molding of the chip on the lead frame. Figure 6 is a schematic illustration of a abrasive molding compound and a chip. Figure 7 is a schematic view showing the provision of a mask layer on the lead frame. Figure 8 is a schematic view showing the back side of the chip and the lead frame connected by wire clip attachment. Figure 9 is a schematic illustration of the top exposed plastic package of the leadframe and chip. Figure 10 is a cross-sectional view of a single semiconductor package structure. Figure 11 is a top plan view of a single semiconductor package structure. Figure 12 is a schematic illustration of the underside of a single semiconductor package structure.

101‧‧‧ source metal layer

102‧‧‧ gate metal layer

103‧‧‧Back metal layer

11‧‧‧chip

2‧‧‧ lead frame

211‧‧‧Source connection area

212‧‧‧gate connection area

213‧‧‧汲 connection area

3‧‧‧First molding compound

5‧‧‧Clamps

501‧‧‧ Bridge section

502‧‧‧ Bridge foot section

6‧‧‧Second molding compound

Claims (20)

A method of manufacturing a double-sided exposed package structure of an ultra-thin chip, comprising the steps of: preparing a chip of a top mask source electrode and a gate electrode; providing a lead frame, and bonding the chip to the chip by flip chip bonding a top surface of the lead frame; injecting a first molding compound from a top surface of the lead frame, molding the chip on the lead frame; grinding the first molding compound and a back surface of the chip, thinning the molding compound and the chip a thickness of the chip is exposed on the top of the first molding compound; a mask layer is deposited on the top surface of the lead frame, the mask layer does not cover the area of the back surface of the chip; and a back metal is deposited on the back surface of the chip a layer is attached to the back surface of the chip by a wire clip; a second molding compound is injected from a top surface of the lead frame, and the lead frame and the chip are top exposed plastically sealed, and the clip attached to the back surface of the chip is exposed a top portion of the second molding compound, exposing a bottom surface of the lead frame to a bottom portion of the second molding compound; and cutting the lead frame and the second molding compound to form a plurality of double The semiconductor package is exposed. A method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to claim 1, wherein the mask layer is deposited on a top surface of the lead frame to cover all other areas except the back surface of the chip, on the back side of the chip After the step of depositing the back metal layer, the step of removing the mask layer is further included. The method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to claim 1, wherein before the step of cutting the lead frame and the second molding compound, the method further comprises: The step of tinning the surface of the wire frame. The method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to claim 1, wherein the step of preparing the chip further comprises the steps of: forming a chip on a top surface of a wafer including a plurality of the chips; The source electrode and the gate electrode; grinding the back side of the wafer, thinning the thickness of the wafer; and dicing the wafer to separate the chip from the wafer. The method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to claim 1, wherein the source metal layer and the gate metal layer have a thickness of 10 to 20 μm. A method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to claim 4, wherein the back surface of the wafer is ground to grind the thickness of the wafer to 300 to 400 um. The method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to claim 1, wherein the lead frame is a flat plate structure, the lead frame comprising a plurality of island regions, the base island region including a source connection region And a gate connection region, and a drain connection region on a side of the source connection region and a side of the gate connection region, respectively. The method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to claim 7, wherein the first molding compound injected from a top surface of the lead frame encloses the chip, and the drain connection region is The periphery of the first molding compound, the clip is connected to the back surface of the chip and the drain connection region. The method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to claim 6, wherein the thickness of the first molding compound is 450 to 500 um from a top surface of the wire frame bonded to the chip. The method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to claim 1, wherein the back metal layer deposited on the back surface of the chip is a titanium-nickel-silver alloy, the back metal layer and the back surface of the chip The polar regions are electrically contacted to form the drain electrode of the chip. A method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to claim 10, wherein the back metal layer has a thickness of 20 μm. The method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to claim 1, wherein the first molding compound and the second molding compound are epoxy molding compounds. The method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to claim 8, wherein the bridge portion of the clip exposed to the second molding compound forms a double-sided exposed package structure of the ultra-thin chip. a drain, the drain connection region of the lead frame exposed to the second molding compound forms a drain of the double-sided exposed package structure of the ultra-thin chip, the source of the lead frame exposed to the second molding compound The pole connection region forms a source of the double-sided exposed package structure of the ultra-thin chip, and the gate connection region of the lead frame exposed to the second mold compound forms a gate of the double-sided exposed package structure of the ultra-thin chip. A method of manufacturing a double-sided exposed package structure of an ultra-thin chip according to any one of claims 1 to 13, wherein the first molding compound and the back surface of the chip are ground, the first molding compound is The thickness is ground to less than or equal to 50 um, and the thickness of the first molding compound is equal to the thickness of the chip plus the thickness of the source metal layer or the gate metal layer on the chip. A double-sided exposed package structure of an ultra-thin chip, comprising: a chip, a top surface of the chip is provided with a source metal layer and a gate metal layer, and a back metal layer is disposed on a back surface of the chip, and the thickness of the chip is added The top surface of the chip and the back metal layer have a thickness of less than or equal to 70 um; a lead frame comprising a plurality of island regions, the base island region including a source connection region and a gate connection region, and respectively located at the source a side of the pole connection region and a drain connection region on a side of the gate connection region, the source connection region being bonded to the source metal layer on the top surface of the chip, the gate connection region and the source of the top surface of the chip a first metal molding compound coating the chip, and the drain connection region is on a periphery of the first molding compound, wherein a back surface of the chip is exposed to the first molding compound; The clip is a bridge structure, the bridge portion of the clip contacts the back metal layer on the back side of the chip, and the bridge portion of the clip connects the drain connection region on the lead frame; the second molding compound, The second molding compound covers the a sheet, the first molding compound, the clip, and the lead frame, wherein a deck portion of the clip is exposed to the second molding compound, the source connection region of the lead frame, the gate connection region, and the The drain connection region is exposed to the second molding compound. The double-sided exposed package structure of the ultra-thin chip according to claim 15, wherein the source metal layer and the gate metal layer on the chip are formed by plating nickel/gold or electroplated copper pillars on the top surface of the wafer. The source metal layer is in electrical contact with the source region on the top surface of the chip to form a source electrode of the chip, and the gate metal layer is in electrical contact with the gate region on the top surface of the chip to form a gate electrode of the chip. The source metal layer and the gate metal layer have a thickness of 10-20 um. The double-sided exposed package structure of the ultra-thin chip according to claim 15, wherein the back metal layer is a titanium-nickel-silver alloy, and the back metal layer is in electrical contact with the drain region of the back surface of the chip to form the chip. The electrode of the back electrode has a thickness of 20 μm. The double-sided exposed package structure of the ultra-thin chip according to claim 15, wherein the lead frame is a flat plate structure, and the lead frame is made of a conductive material. The double-sided exposed package structure of the ultra-thin chip according to claim 15, wherein the first molding compound has a thickness of 50 um or less, and the thickness of the first molding compound is equal to the thickness of the chip plus the chip. The thickness of the source metal layer or the gate metal layer. The double-sided exposed package structure of the ultra-thin chip of claim 15, wherein the bridge portion of the clip exposed to the second molding compound forms a bungee of the double-sided exposed package structure of the ultra-thin chip The drain connection region of the lead frame exposed to the second molding compound forms a drain of the double-sided exposed package structure of the ultra-thin chip, and the source connection region of the lead frame exposed to the second molding compound Forming a source of the double-sided exposed package structure of the ultra-thin chip, the gate connection region of the lead frame exposed to the second molding compound forms a gate of the double-sided exposed package structure of the ultra-thin chip.