TWI441267B - A wafer level chip encapsulation method of encapsulating the backside and sidewalls of the chip - Google Patents

Description

Wafer-level packaging method for encapsulating the bottom and periphery of a wafer

The present invention relates to a wafer level packaging method (WLP), and more particularly to a wafer level packaging method for encapsulating the bottom and periphery of a wafer.

As shown in FIG. 1, a schematic view of a conventional semiconductor wafer 200 is provided, and a molding body 300 is provided only around the periphery of the wafer 200. Specifically, a plurality of metal wirings 210 and a passivation layer 220 on the top surface of the wafer 200 are formed on one of the dies 100, and the solder balls 230 are respectively implanted on the top electrodes thereof, and then the wafers 200 are packaged; As shown in FIG. 2, in step A1, the bottom surface of the cymbal sheet 100 is attached to the dicing film 400, and the metal wiring 210, the passivation layer 220 and the solder ball 230 on the top of the plurality of wafers 200 are directed upward; In step A2, the dicing sheet 100 is diced, that is, the dicing track 110 is formed between the respective wafers 200 connected to the dicing film 400; in step A3, a molding compound such as a plastic resin is injected into the plurality of dicing streets 110 to form a The sealing body 300 is described; in step A4, the dicing die 110 is diced at the position of the dicing street 110, and the original molded body 300 is separated from each other to form a separate wafer 200; after the dicing film 400 is removed That is, the wafer 200 package as shown in Fig. 1 is formed. It can be seen that at the bottom surface of each wafer 200, it is not encapsulated by the plastic body 300, and there is no protection.
As shown in FIG. 3, it is a schematic view of a plastic sealing structure of another conventional semiconductor wafer 200. The bottom and periphery of the wafer 200 are encapsulated by a molding body 300. The packaging method of the wafer 200, as shown in FIG. 4: steps B1, B2, firstly cutting the cymbal sheet 100 to form separate individual wafers 200, and then fixing each wafer 200 face down, respectively, on the dicing film 400. The spacing between each wafer 200 and the other wafers 200 is such that the spacing is greater than the spacing of the wafers 200 on the cymbal 100; in step B3, injection molding is performed to fill the molding compound with adjacent wafers. 200 is spaced apart and completely covers the back surface of the cymbal sheet 100 to form the molding body 300; in steps B4 and B5, after removing the dicing film 400, the lining sheet 100 is connected by the molding body 300 as a whole. The plurality of wafers 200 are turned over so that the cymbal sheet 100 faces upward; steps B6 and B7, in turn, fan-out type metal wiring redistribution (Fan-Out RDL) processing and passivation processing are performed on the front side of the cymbal sheet 100; steps B8, B9, A solder ball 230 is implanted at a corresponding position on the front side of the cymbal sheet 100 to form a top electrode of the wafer 200. After testing the wafer 200, the wafer 100 is diced from the front surface of the cymbal sheet 100 to separate a plurality of individual wafers 200 as shown in FIG. The bottom and periphery of the wafer 200 are protected by a molding body 300, but the manufacturing process is very complicated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a wafer level packaging method that results in a wafer package structure that is protected by a package encapsulation at the bottom and periphery of the wafer.
In order to achieve the above object, the technical solution of the present invention provides a wafer level packaging method for encapsulating a bottom and a periphery of a wafer, which forms a protective molding body at the bottom and the periphery of each wafer; the packaging method includes the following steps :
Step 1. preparing the slab; preparing a surface pattern of a plurality of wafers on the front side of the slab, and placing the front side of the cymbal facing upward;
Step 2, performing back thinning on the back side of the cymbal;
Step 3, the back surface of the cymbal sheet is fixedly bonded to the dicing film;
Step 4: cutting from the front side of the cymbal sheet, correspondingly separating the respective wafers; the wafers are connected by the dicing film of the bottom surface, and maintain the relative positions and intervals on the cymbals on each other;
Step 5, flipping the ruthenium film with the dicing film, so that the entire ruthenium after cutting is fixedly bonded to the top surface of a double-sided tape, and then the dicing film is removed; The bottom surface of the tape is bonded and fixed on a support liner or other fixing device;
Step 6, the bake sheet is plastically sealed, so that the molding material fills the space between the adjacent wafers from the back side of the bake piece, and covers the back surface of all the wafers to form a plastic package;
Step 7, inverting the cymbal, and peeling off the cymbal from the supporting lining and the double-sided tape;
Step 8. On the front side of the upward facing cymbal, the ball is placed corresponding to the position of the top electrode of each wafer;
Step 9. Through a reflow process, a plurality of solder balls corresponding to the top electrodes are formed;
Step 10: Forming individual wafers by dicing: separating the plastic bodies that are connected together between adjacent wafers, so that a certain of the plastic body protection is left at the bottom and the periphery of each wafer.
When the wafer is a MOSFET wafer, in step 1, the front surface of the wafer substrate of the wafer includes a germanium dioxide starting layer, a metal wiring layer made of aluminum, and a passivation layer; the front side of the wafer faces upward.
In the step 2, after the back surface of the ruthenium sheet is thinned, a metal layer having a certain thickness is formed on the back surface of the ruthenium sheet by a back surface etching and a back metallization process.
When the wafer is a power device wafer, in step 1, the metal wiring redistribution process is performed on the front side of the ruthenium; the front surface of the ruthenium substrate of the wafer includes a ruthenium dioxide starting layer and a metal wiring made of aluminum. a redistribution layer, and a passivation layer; the front side of the wafer faces upward.
In one embodiment, the double-sided tape has a certain stretch property, and after the entire cut piece in the step 5 is flipped and fixedly bonded to the top surface of the double-sided tape, one of the tapes is stretched. a step of increasing the spacing between the wafers to facilitate the spacing of the subsequent molding compound into the wafer; the stretched double-sided tape is bonded to the support liner or other fixing device to maintain the stretching. The rear wafers are spaced from each other.
In step 3, the dicing film is an ultraviolet tape;
In step 5, the double-sided tape is a thermal release tape or an ultraviolet tape.
In step 5, the support liner bonded to the bottom surface of the double-sided tape is a glass substrate or other slab.
Compared with the prior art, the wafer level packaging method of the present invention obtains a wafer package structure protected by a plastic package at the bottom and the periphery of the wafer in a simple and feasible fabrication process.

Several embodiments of the invention are described below in conjunction with the drawings.
Example 1
The wafer level packaging method described in this embodiment is particularly suitable for a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or other similar semiconductor device wafer package, so that the bottom and periphery of each wafer 20 can be encapsulated by the molding body 30. Protect (Figure 14).
Referring to Figures 5 through 14, the packaging method comprises the following steps:
Step 1, as shown in Fig. 5, the front side process of the cymbal 10 is completed; a surface pattern of a plurality of wafers 20 is formed on the front side of a cymbal 10, and the side of the cymbal 10 is faced upward; On the wafer 10 of each wafer 20, a ruthenium oxide starting layer 11, a metal wiring layer 21 made of aluminum, and a surface of the passivation layer 22 are faced upward.
Step 2: As shown in Fig. 6, the back surface thinning treatment is performed on the back surface of the cymbal sheet 10, and a metal layer 24 having a certain thickness is formed on the back surface of the cymbal sheet 10 by back etching and back metallization.
Step 3. As shown in Fig. 7, an ultraviolet tape is attached as a dicing film 40 from below, and the cymbal 10 is fixed to the dicing film 40 through the metal layer 24 on the back surface.
Step 4, as shown in Fig. 8, dicing and cutting the front surface of the cymbal 10 from above, correspondingly separating the respective wafers 20; the wafers 20 are connected by the dicing film 40 of the bottom surface, and are kept on the cymbal 10 at the same time. Relative position and spacing.
Step 5, as shown in FIG. 9, the entire cut piece 10 with the dicing film 40 is inverted and fixedly bonded to the top surface of a tape 50, and then the dicing film 40 is removed; The tape 50 is disposed around the surface and periphery of the metal wiring layer 21, the passivation layer 22 on the front surface of the wafer 20, and is in contact with the front surface of the starting layer 11.
In one embodiment, the adhesive tape 50 is a double-sided tape bonded to a support liner 60 by a bottom surface, and the support liner 60 may be a glass substrate or other gusset. The double-sided tape 50 may be a thermal release tape or an ultraviolet tape. The individual wafers that are cut to form a separate bond are fixedly bonded to the top surface of the double-sided tape 50 and held in relative positions and spaces on the crotch panel 10 with respect to each other.
In another embodiment, the tape 50 has better ductility. After the entire cymbal 10 after cutting in step 5 is flip-chip mounted and fixedly bonded to the top surface of the tape 50, the tape 50 is further stretched. One step is to increase the spacing of the wafers 20 from each other so that the molding compound in the subsequent step is easily injected into the interval of the wafer 20. The stretched tape can be adhesively attached to the support backing 60 or other fixture to maintain the spacing of the wafers 20 from each other after stretching.
Step 6. As shown in Fig. 10, the cymbal sheet 10 is plastically sealed: a molding compound injected from above, covering the top surface of the double-sided tape 50 with a sufficient thickness so that the molding compound is filled from the back surface of the cymbal sheet 10 The spaced locations between the adjacent wafers 20 and cover the metal layers 24 on the back of all of the wafers 20. Thereby, the molded body 30 enclosing the back surface of each wafer 20 (i.e., the bottom of the finished product) and the periphery is obtained.
Step 7. As shown in Fig. 11, the cymbal sheet 10 is turned over, and the cymbal sheet 10 is peeled off from the bonded support lining 60 and the double-sided tape 50. At this time, the wafers 20 are integrally joined by the molding body 30 at a position where the bottom of the wafer 20 and the adjacent wafers 20 are spaced apart.
Step 8. As shown in Fig. 12, on the front side of the upwardly facing cymbal 10, the ball is placed on the metal wiring layer 21 at a position corresponding to the top electrode of each wafer 20.
Step 9. As shown in Fig. 13, a plurality of solder balls 23 corresponding to the top electrodes are formed by a reflow process.
Step 10, as shown in FIG. 14, each of the individual wafers 20 is formed by dicing: the integrally formed molding bodies 30 are separated from each other, so that a certain of the plastic seals are left in the periphery of each of the wafers 20. Body 30 protection.
To this end, the encapsulation of the wafer 20 is completed, and the bottom and periphery of each wafer 20 are protected by a molding body 30.
Example 2
This embodiment is particularly suitable for a wafer package of a power device (Power IC) such that the bottom and periphery of each wafer 20 can be encapsulated for protection by a molding body 30 (Fig. 24).
Referring to FIGS. 15 to 24, the encapsulation method includes the following steps, wherein steps 1 and 2 are different from the above embodiments, and other steps are similar:
Step 1, as shown in Fig. 15, completes the front side process of the cymbal 10, including its metal wiring redistribution process (RDL); correspondingly, a plurality of surface patterns of the wafer 20 are formed on one cymbal 10, and the cymbal is made The front side of the wafer 10 is upwardly facing; that is, the wafer 10 of each wafer 20 is provided with a ruthenium oxide starting layer 11, a metal wiring redistribution layer 25 made of aluminum, and a surface of the passivation layer 22 facing upward. .
Step 2. As shown in Fig. 16, the back surface thinning treatment is performed on the back surface of the cymbal 10.
Step 3 As shown in Fig. 17, an ultraviolet tape is attached as a dicing film 40 from below, and the back surface of the cymbal 10 is fixedly bonded to the dicing film 40.
Step 4, as shown in Fig. 18, the front side of the cymbal sheet 10 is diced from above, and the respective wafers 20 are separated correspondingly; the wafers 20 are connected by the dicing film 40 of the bottom surface.
Step 5. As shown in Fig. 19, the cymbal sheet 10 with the dicing film 40 is inverted and fixedly attached to the top surface of a tape 50, and then the dicing film 40 is removed; The metal wiring redistribution layer 25, the surface and the periphery of the passivation layer 22 are disposed around the front surface of the wafer 20, and are in contact with the front surface of the starting layer 11.
In one embodiment, the adhesive tape 50 is a double-sided tape bonded to a support liner 60 by a bottom surface, and the support liner 60 may be a glass substrate or other gusset. The double-sided tape 50 may be a thermal release tape or an ultraviolet tape. The individual wafers that are cut to form a separate bond are fixedly bonded to the top surface of the double-sided tape 50 and held in relative positions and spaces on the crotch panel 10 with respect to each other.
In another embodiment, the tape 50 has better ductility. After the entire cymbal 10 after cutting in step 5 is flip-chip mounted and fixedly bonded to the top surface of the tape 50, the tape 50 is further stretched. One step is to increase the spacing of the wafers 20 from each other so that the molding compound in the subsequent step is easily injected into the interval of the wafer 20. The stretched tape can be adhesively attached to the support backing 60 or other fixture to maintain the spacing of the wafers 20 from each other after stretching.
Step 6. As shown in Fig. 20, the cymbal sheet 10 is plastically sealed: a molding compound injected from above, covering the top surface of the double-sided tape 50 with a sufficient thickness so that the molding compound is filled from the back surface of the cymbal sheet 10 The spaced locations between the adjacent wafers 20 and cover the backside of all of the wafers 20. Thereby, the molded body 30 enclosing the back surface of each wafer 20 (i.e., the bottom of the finished product) and the periphery is obtained.
Step 7. As shown in Fig. 21, the cymbal sheet 10 is turned over, and the cymbal sheet 10 is peeled off from the supporting lining plate 60 and the double-sided tape 50 bonded thereto. At this time, the wafers 20 are integrally joined by the molding body 30 at a position where the bottom of the wafer 20 and the adjacent wafers 20 are spaced apart.
Step 8. As shown in Fig. 22, on the front side of the upward facing cymbal 10, a ball is placed on the metal wiring redistribution layer 25 corresponding to the position of the top electrode of each wafer 20.
Step 9. As shown in Fig. 23, a plurality of tin balls 23 corresponding to the top electrodes are formed by a reflow process.
Step 10, as shown in Fig. 24, each of the individual wafers 20 is formed by dicing: the integrally formed molding bodies 30 between the adjacent wafers 20 are separated, so that a certain of the plastic seals are left in the periphery of each of the wafers 20. Body 30 protection.
To this end, the encapsulation of the wafer 20 is completed, and the bottom and periphery of each wafer 20 are protected by a molding body 30.
Although the present invention has been described in detail by the preferred embodiments thereof, it should be understood that the foregoing description should not be construed as limiting. Various modifications and alterations of the present invention will be apparent to those skilled in the art. Therefore, the scope of the invention should be limited by the scope of the appended claims.

10,100. . . Bract

11. . . Starting layer

20, 200. . . Wafer

twenty one. . . Metal wiring layer

22,220. . . Passivation layer

23, 230. . . Solder balls

twenty four. . . Metal layer

30, 300. . . Plastic body

40, 400. . . Draw film

50. . . tape

60. . . Support liner

110. . . Scribing road

210. . . Metal wiring

1 is a schematic view showing a conventional semiconductor wafer structure in which a molding body is disposed at a periphery;
Figure 2 is a schematic view showing the flow of the wafer shown in Figure 1;
Figure 3 is a schematic view showing another conventional semiconductor wafer structure in which a molded body is provided at the bottom and the periphery;
Figure 4 is a schematic view showing the manufacturing process of the wafer shown in Figure 3;
5 to 14 are schematic views showing the flow of the wafer-level packaging method of the bottom and periphery of the wafer of the present invention in Embodiment 1;
15 to 24 are schematic views showing the flow of the wafer-level packaging method for the bottom and periphery of the wafer of the present invention in Embodiment 2.

10. . . Bract

11. . . Starting layer

20. . . Wafer

twenty one. . . Metal wiring layer

twenty two. . . Passivation layer

twenty three. . . Solder balls

twenty four. . . Metal layer

30. . . Plastic body

Claims (7)

A wafer level packaging method for encapsulating a bottom and a periphery of a wafer, characterized in that a protective molding body (30) is formed on the bottom and periphery of each wafer (20); the packaging method comprises the following steps:
Step 1. Preparing the cymbal sheet (10); forming a surface pattern of a plurality of wafers (20) on the front side of a cymbal sheet (10), and placing the front surface of the cymbal sheet (10) upward;
Step 2, performing back surface thinning treatment on the back surface of the cymbal sheet (10);
Step 3, the back surface of the cymbal sheet (10) is fixedly bonded to the dicing film (40);
Step 4: dicing and cutting from the front side of the cymbal sheet (10), correspondingly separating the respective wafers (20); the wafers (20) are connected by the dicing film (40) of the bottom surface, and are kept in the cymbal (10) Relative position and spacing;
Step 5, flipping the cymbal sheet (10) with the dicing film (40), so that the entire cymbal sheet (10) after cutting is fixedly attached to the top surface of a double-sided tape (50). Removing the dicing film (40); the bottom surface of the double-sided tape (50) is adhesively fixed on a supporting lining (60) or other fixing device;
Step 6. Plastically seal the cymbal sheet (10) so that the molding material fills the space between the adjacent wafers (20) from the back surface of the cymbal sheet (10), and covers the back surface of all the wafers (20) to form a plastic body (30). );
Step 7, inverting the cymbal sheet (10), and peeling off the cymbal sheet (10) from the supporting lining plate (60) and the double-sided tape (50);
Step 8. On the front side of the upward facing cymbal (10), the ball is placed corresponding to the position of the top electrode of each wafer (20);
Step 9, through the reflow process, formed a number of tin balls (23) corresponding to the top electrode;
Step (10), forming individual wafers (20) by dicing: separating the plastic bodies (30) integrally connected between the adjacent wafers (20), leaving the bottom and the periphery of each wafer (20) A certain of the plastic body (30) is protected. A wafer level packaging method for encapsulating a wafer bottom and a periphery as described in claim 1 of the patent application, characterized in that
When the wafer (20) is a MOSFET wafer, in step 1, the wafer (10) of the wafer (20) has a front side of the substrate, a germanium dioxide starting layer (11), and a metal wiring layer made of aluminum (21). And a passivation layer (22); the face of the wafer (20) facing up. A wafer level packaging method for encapsulating a wafer bottom and a periphery as described in claim 2, characterized in that
In step 2, after the back surface of the enamel sheet (10) is thinned, a metal layer (24) having a certain thickness is formed on the back surface of the cymbal sheet (10) by back etching and back metallization. A wafer level packaging method for encapsulating a wafer bottom and a periphery as described in claim 1 of the patent application, characterized in that
When the wafer (20) is a power device wafer, in step 1, the metal wiring redistribution process on the front side of the cymbal (10) is further included; the wafer (10) of the wafer (20) is provided on the front side of the substrate A cerium oxide starting layer (11), a metal wiring redistribution layer (25) made of aluminum, and a passivation layer (22); the front side of the wafer (20) faces upward. A wafer level packaging method for encapsulating a wafer bottom and a periphery as described in claim 3 or 4, wherein
The double-sided tape (50) has a certain stretch property, and the entire crepe (10) after cutting in step 5 is flip-chip mounted and fixedly bonded to the top surface of the double-sided tape (50), and is further stretched. a step of the double-sided tape (50) to increase the spacing of the wafers (20) from each other to facilitate the injection of the subsequent molding compound into the wafer (20);
The bottom surface of the stretched double-sided tape (50) is adhesively attached to the support liner (60) or other fixture to maintain the spacing of the wafers (20) from each other after stretching. A wafer level packaging method for encapsulating a wafer bottom and a periphery as described in claim 5, characterized in that
In step 3, the dicing film (40) is an ultraviolet light tape;
In step 5, the double-sided tape (50) is a thermal release tape or an ultraviolet tape. A wafer level packaging method for encapsulating a wafer bottom and a periphery as described in claim 5, characterized in that
In step 5, the support liner (60) bonded to the bottom surface of the double-sided tape (50) is a glass substrate or other crepe.