TW201639206A - Memory device and manufacturing method of the same - Google Patents

Abstract

A 3D array of memory cells with one or more blocks is described. The blocks include a plurality of layers. The layers in the plurality include semiconductor strips which extend from a semiconductor pad. The layers are disposed so that the semiconductor strips in the plurality of layers form a plurality of stacks of semiconductor strips and a stack of semiconductor pads. Also, a plurality of select gate structures are disposed over stacks of semiconductor strips in the plurality of stacks between the semiconductor pad and memory cells on the semiconductor strips. In addition, different ones of the plurality of select gate structures couple the semiconductor strips in different ones of the stacks of semiconductor strips to the semiconductor pads in the plurality of layers. Further, an assist gate structure is disposed over the plurality of stacks between the select gate structures and the stack of semiconductor pads.

Description

Memory device and method of manufacturing same 【0001】

The present technology relates to a stacked transistor structure, such as a high-density three-dimensional memory device, and to a memory device using such a structure.

【0002】

A three-dimensional (3D) memory device is characterized by having a multi-layered structure, and each layer can include a planar array of a plurality of memory cells. For a particular three-dimensional stacked memory device, the plurality of active layers may include a plurality of active strips, and the material of the active strips may be configured as bit lines or word lines of the memory cells, and stacked in a ridge shape spaced apart from each other (ridge-like) structure. Such active layers may be made of doped (p-type or n-type) or undoped semiconductor materials. In such a three-dimensional memory device, a plurality of memory cells may be disposed on a stacked bit line or word line and a plurality of cross-points of the word line or bit line intersecting therewith to form a three-dimensional Memory array.

[0003]

The memory device as described above is described in US Patent Publication No. 2012/0182806, and the filing date is April 1, 2011, and the invention is entitled "3D Memory Array Structure with Interleaved Memory String Configuration and String Selection Structure" Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures), the inventors are Chen Shihong and Lu Xinting; and the US Patent No. 8,363,476, the application date is January 19, 2011, the invention name is "memory device, its manufacture" Memory Device, Manufacturing Method And Operating Method Of The Same, the inventors are Chen Shihong and Lu Yiting. The above two U.S. patents are commonly owned by the assignee of the present application and are hereby incorporated by reference. In the above example, active strips are coupled to the pads of the layers. The contact pads are configured in a stepped step configuration to provide a plurality of landing areas to a plurality of interlayer conductors. Especially for large arrays, the resistance of the contact pads may be relatively high, thus slowing down the operation of the device. Also, the plurality of current paths across the array to the respective active strips may be different from one another such that control circuitry and sensing circuitry are more complex.

[0004]

1 is a perspective view of a three-dimensional anti-gate flash memory device 100, which is described in U.S. Patent No. 8,503,213 B2, which is incorporated herein by reference in its entirety. The apparatus 100 as shown in Fig. 1 includes a plurality of stacked semiconductor strips and insulating strips arranged in a staggered manner. The insulating material is removed from the pattern to expose more structure, for example, the insulating strips between the semiconductor strips and between the semiconductor strip stacks in the stack are removed.

[0005]

Four semiconductor contact pads 102B, 103B, 104B, and 105B are located on the proximal end of the stack formed by a plurality of active layers, and four semiconductor contact pads 112A, 113A, 114A, and 115A are located at the distal end of the stack ( Distal end). However, the number of active layers and corresponding semiconductor contact pads can extend to any N layer, where N is an integer greater than one. As shown, the three-dimensional semiconductor device includes a plurality of stacks of a plurality of active strips (e.g., 102, 103, 104, 105) spaced apart by an insulating material. The semiconductor contact pads (eg, 102B, 103B, 104B, and 105B) terminate a plurality of active strips in the corresponding plurality of active layers. As described above, semiconductor contact pads 102B, 103B, 104B, and 105B are electrically coupled to a plurality of active layers for connection to a decoding circuit to select layers in the array. The semiconductor contact pads 102B, 103B, 104B, and 105B may be patterned together as the active layer is patterned, with the possible exception being a via used as an interlayer connector. In the illustrated example, each active strip includes a semiconductor material to be suitable as a channel region. The strips are ridge-like and extend along the Y-axis such that the active strips 102, 103, 104, 105 can serve as a plurality of bodies, the bodies comprising a plurality of channels of a plurality of flash memory cell strings The zone, for example, is in a plurality of horizontal and gate train configurations. In the illustrated example, the memory material layer 152 is coated with a plurality of stacks of a plurality of active strips, while in other embodiments, the memory material layer 152 is coated on at least one side wall of the plurality of active strips. In other embodiments, the active strip can be used as a word line for the vertical and gate train configuration.

[0006]

In the illustrated example, one end of each stack of active strips terminates in a semiconductor contact pad and the other end terminates in a source line. Thus, the active strips 102, 103, 104, 105 terminate at the proximal end of the semiconductor contact pads 102B, 103B, 104B, and 105B, and terminate at the source line end (119) at the distal end through the gate select line 127. The active strips 112, 113, 114, 115 terminate at the distal end of the semiconductor contact pads 112A, 113A, 114A, and 115A, and terminate near the source line end (eg, the source) through the gate select line 126 and near the proximal end of the active strip. Line 128).

【0007】

In the example shown in Fig. 1, a plurality of conductors 125-1 to 125-N are orthogonally arranged on a plurality of stacks composed of a plurality of active strips. The plurality of conductors 125-N have a plurality of surfaces conformal to the stack of the plurality of active strips in a plurality of trenches defined by the plurality of stacks, and the active strips 102, 103, 104 on the stack The sides of 105, and the intersections of conductors 125-1 through 125-N (e.g., word line or source select line) define a multi-layer array of interface regions. As shown, a germanide layer (e.g., tungsten telluride, cobalt telluride, titanium telluride or nickel telluride) 154 may be formed on the top surface of a conductor, such as a word line or source select line.

[0008]

In one embodiment of apparatus 100, a multilayer array is formed on an insulating layer and includes a plurality of word lines (conductors 125-1, ..., 125-N) conformal to a plurality of stacks. Such stacks include a plurality of semiconductor strips 112, 113, 114, 115 located in a multi-layer plane. As shown in Fig. 1, the character line applied to the number of memory pages of the number is increased from the conductor 121-1 to the front of the entire structure from the conductor 121-1 to 125-N, and for the singular number of memory pages, the word line is from the overall structure. The label to the front is then reduced from conductor 125-N to 121-1.

【0009】

A memory material layer is disposed on the surface of the semiconductor strips 112-115 and 102-105 and the interface area of the intersection of the word lines (conductors 125-1~125-N). Similar to the word line, the ground select lines (GSL) 126 and 127 are conformal to a plurality of stacks.

[0010]

A bit line and a string selection line are formed at the metal layers ML1, ML2, and ML3. The bit lines are coupled to a planar decoder (not shown). The string selection line is coupled to a string of select line decoders (not shown).

[0011]

The patterning of the gate structures of the ground select lines 126, 127 can be performed in the same step of defining the word lines (conductors 125-1~125-N). A ground selection device is formed at the intersection between the plurality of stacked planes and the gate structure of the ground select lines 126, 127. The patterning of string select line (SSL) gate structures 119 and 109 can be performed in the same step of defining word lines 125-1~125-N. A string selection device is formed at an intersection between a plurality of stacked planes and string selection line gate structures 119 and 109. Such devices are coupled to a decoding circuit for selecting strings in a particular stack in the array.

[0012]

Depending on the manner of implementation, the memory material layer 152 may comprise a multi-layered dielectric charge storage structure, such as described in commonly-owned U.S. Patent Application Serial No. 14/309,622, the disclosure of which is incorporated herein in its entirety. For example, a multi-layer charge storage structure includes a tunneling layer, a charge trapping layer, and a blocking layer. The tunneling layer includes niobium oxide, the charge trapping layer includes tantalum nitride, and the barrier layer includes an oxidation layer. Hey. In some embodiments, the tunneling layer in the dielectric charge storage layer may include a first tantalum oxide layer having a thickness of less than 2 nanometers, a tantalum nitride layer having a thickness of less than 3 nanometers, and a thickness of less than 3 nanometers. a second layer of cerium oxide. In other embodiments, the memory material layer 152 may include only one charge trapping layer, and does not include any tunneling layers or barrier layers.

[0013]

In another embodiment, an anti-fuse material such as hafnium oxide, hafnium oxynitride or other antimony oxide may be employed, the thickness of which is, for example, 1 to 5 nm. Other types of antifuse materials, such as tantalum nitride, may also be used. In embodiments employing an antifuse material, the active strips 102, 103, 104, 105 may be semiconductor materials having a first conductivity type (eg, p-type). The conductor (eg, a word line or source select line) 125-N may be a semiconductor material having a second conductivity type (eg, an n-type). For example, the active strips 102, 103, 104, 105 can be made of p-type polysilicon, while the conductors 125-N can be made of relatively heavily doped n+ polysilicon or relatively heavily doped p+ polysilicon. In embodiments where an antifuse material is employed, the width of the active strip must be sufficient to provide space to create a depletion region for operation of the diode. Therefore, the intersection between the polycrystalline beam and the conductor line in the three-dimensional array forms a plurality of memory cells, and the memory unit includes a rectifier having a pn connection between the cathode and the anode and having a stylized antifuse layer Formed by the face.

[0014]

In other embodiments, the memory material can employ different programmable resistive memory materials, including metal oxides, such as tungsten oxide formed on tungsten, or doped with metal oxides, or other materials. Some of the materials formed by such devices may be programmable and may be erased at multiple voltages or multiple currents and may perform multi-bit storage operations within the unit.

[0015]

As shown in FIG. 1, semiconductor contact pads 102B, 103B, 104B, and 105B are coupled to one side of a plurality of active strips in a corresponding layer of the device, for example, by forming a continuous patterned semiconductor layer. In some implementations, the contact pads can be coupled to both sides of a plurality of active strips in a corresponding layer. In other embodiments, the contact pads can be connected to the active strip via other materials and structures to achieve electrical communication of voltage and current required for device operation. Also, among the semiconductor contact pads 102B, 103B, 104B, and 105B, except for the bottommost layer, a plurality of openings 102C1, 102C2, 103C1, 103C2, 104C or contacts are exposed, the openings or contacts exposing the landing zone on the bottom contact pads, and Form a stepped structure. The opening defines a plurality of inner circumferences on the contact pad.

[0016]

The interleaved pattern shown in FIG. 1 is only an example, and may not necessarily be applied to other embodiments of the present technology. An example of such an embodiment is, for example, that the semiconductor contact pads and the string selection structures in the three-dimensional anti-gate flash memory array structure are disposed on the same side of the block.

[0017]

This document describes a three-dimensional array of a plurality of memory cells having one or more blocks. The block includes a plurality of layers including a plurality of semiconductor strips extending from a semiconductor contact pad. The layers are arranged such that the semiconductor strips form a plurality of semiconductor strip stacks and one of a plurality of semiconductor contact pads. Also, a plurality of select gate structures are disposed over the stack of semiconductor stripes and between the semiconductor contact pads on the semiconductor strips and the memory cells. The different ones of the selected gate structures couple different semiconductor strips in the semiconductor strip stack to the semiconductor contact pads in the layers. Still further, at least one auxiliary gate structure is disposed over the semiconductor strip stack and between the select gate structure and the semiconductor contact pad stack. In some embodiments, the auxiliary gate structure includes a horizontal portion that overlaps at least one side of the semiconductor contact pad.

[0018]

A bias circuit can be connected to the auxiliary gate structure. The bias circuit applies a gate voltage to select a memory cell in a block in response to the address and when the select gate structure is turned on. Applying a gate voltage to the auxiliary gate structure can result in a local inversion channel (eg, increasing the concentration of charge carriers) formed in a plurality of semiconductor strips adjacent to the auxiliary gate structure, and reducing the semiconductor strip The resistance of the upper semiconductor contact pad to the current path of the memory cell. The semiconductor contact pad can include a plurality of landing regions for the plurality of interlayer conductors, and can include a plurality of openings in a stack formed by the plurality of semiconductor contact pads, the openings providing a plurality of interconnecting pillars to connect the landing regions thereto Overlying conductors are overlying the semiconductor contact pads. Still further, the doping concentration of the plurality of regions located in the landing regions is higher than the doping concentration of the plurality of other regions in the semiconductor contact pads.

[0019]

The semiconductor strip can include a plurality of anti-gate channels. A plurality of word lines may overlie the stack of semiconductor strips, and the word lines may include a plurality of vertical gate structures between the stacks. In some embodiments, a dielectric charge storage layer is disposed on at least a plurality of stacked sidewalls between the vertical gate structure and the semiconductor strip. Similarly, the auxiliary gate structure may include a conductor, the conductor is covered with a plurality of semiconductor strip stacks, and the vertical gate structure is located between the semiconductor strip stacks, and the dielectric charge storage layer may be disposed as a gate dielectric layer and Located between the vertical gate structure and the semiconductor strip.

[0020]

In some other embodiments, the auxiliary gate structure includes a conductor overlying the plurality of semiconductor strip stacks, and the vertical gate structure is between the stacks of semiconductor strips, and a gate dielectric layer is located in the vertical gate structure and Between the semiconductor strips.

[0021]

In still other embodiments, at least one side of the auxiliary gate structure is separated by a gate dielectric layer and a plurality of semiconductor contact pads, and an inversion channel is induced by the semiconductor contacts under bias. One side of the pad.

[0022]

In still other embodiments, the array includes one or more lateral auxiliary gate structures, the lateral auxiliary gate structures being coupled to the select gate structures.

[0023]

In order to provide a better understanding of the above and other aspects of the present invention, the preferred embodiments of the present invention are described in detail below.

[0024]

Similar reference numerals in the drawings are used to designate similar parts in different drawings. Moreover, the dimensional ratios in the drawings are not drawn in proportion to actual products, but are used to emphasize the technical features of the disclosure. Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

【0117】

100‧‧‧ device
102, 103, 104, 105, 112, 113, 114, 115‧‧ ‧ active strips
102B, 103B, 104B, 105B, 112A, 113A, 114A, 115A, 245, 246, 247, 248‧‧ ‧ semiconductor contact pads
102C1, 102C2, 103C1, 103C2, 104C‧‧‧ openings
109, 119‧‧‧ string selection line gate structure
125-1~125-N‧‧‧ conductor
126, 127‧‧ ‧ gate selection line
128‧‧‧ source line
152‧‧‧ memory material layer
154‧‧‧ Telluride layer
191‧‧‧Interlayer conductor
200, 300, 400A, 400B, 500A, 500B, 500C, 600A, 600B, 600C, 600D, 600E, 600F, 700A, 700B, 800A, 800B, 800C, 800D, 900A, 900B, 900C‧‧
202, 203, 204, 205, 317, 318‧‧‧
212‧‧‧Auxiliary gate structure
213‧‧‧ vertical part
214‧‧‧ horizontal extension
220, 222, 224, 226, 310, 312, 314, 320, 322, 324, 326 ‧ ‧ insulation strip
221, 223, 225, 227, 229, 309, 310, 311, 312, 313, 314, 315, 316, 319, 321, 323, 325 ‧ ‧ semiconductor strip
228‧‧‧Conductor
232‧‧‧ dielectric charge storage layer
233, 234, 235, 236 ‧ ‧ landing zone
237, 238, 239, 240, 241, 242, 243, 244, 410‧‧‧ areas
270‧‧‧ trench
302, 402, 406‧‧‧ Grounding selection line gate structure
305‧‧‧Source contact points
306‧‧‧Contact plug
308a, 308b, 408‧‧‧ string selection line gate structure
327, 328‧‧‧ lateral auxiliary gate structure
404, 1062‧‧‧ character line
1058‧‧‧Planar decoder
1059‧‧‧ bit line
1060‧‧‧ memory array
1061‧‧‧ column decoder
1063‧‧‧ line decoder
1064‧‧‧string selection line
1065, 1067‧‧ ‧ busbar
1066, 1068‧‧‧ blocks
1069‧‧‧ bias setting state machine
1070‧‧‧Auxiliary Gate Structure Decoder
1071‧‧‧ data input line
1072‧‧‧ data output line
1074‧‧‧Other circuits
1075‧‧‧Integrated circuit line
A, B, C, D‧‧‧ curves
Loffset‧‧‧ offset distance
ML1, ML2, ML3‧‧‧ metal layer

[0025]

1 is a perspective view of a three-dimensional inverse gate flash memory array structure, wherein the three-dimensional inverse gate flash memory array structure includes a plurality of semiconductor contact pads for a plurality of interlayer contact conductors.
Figure 2 illustrates a perspective view of an auxiliary gate structure (AG) disposed over the stack between the select gate structure and the semiconductor contact pad stack.
Figure 3 illustrates a side view of a lateral auxiliary gate structure (LAG) disposed over the stack and between the selected gate structures.
FIG. 4A is a schematic diagram showing the three-dimensional anti-gate flash memory array as shown in FIG. 2.
FIG. 4B is an enlarged view of the schematic diagram shown in FIG. 4A, and is used to describe the pitch and cell size of the three-dimensional inverse NAND flash memory array as shown in FIG. 2.
Figure 5A is a current-voltage (Id-Vg) characteristic diagram for describing the electrical characteristics of a three-dimensional inverse gate flash memory array including at least one auxiliary gate structure.
Figure 5B is a current-voltage (Id-Vg) characteristic diagram for describing the electrical characteristics of a three-dimensional inverse gate flash memory array including at least one auxiliary gate structure.
Figure 5C is a plot of saturation current (Id _sat ) versus memory page for different crystalline yttrium forms.
Figure 6A is a schematic diagram of a three-dimensional inverse gate flash memory array in which the semiconductor contact pads of the three-dimensional inverse gate flash memory array are completely and uniformly doped.
6B~6D are diagrams illustrating the effect of a semiconductor contact pad doped with a three-dimensional inverse gate flash memory array, wherein the three-dimensional inverse gate flash memory array includes at least one auxiliary gate structure.
Figure 6E is a plot of saturation current (Id _sat ) versus memory page for different crystalline germanium forms with different doping concentrations.
FIG. 6F based on a graph of the ratio described in relation to the doping concentration of the saturated current of the memory page 0 (Id _sat) / memory page saturation current (Id _sat) 14 of the.
Figure 7A is a current-voltage (Id-Vg) characteristic diagram for describing the electrical characteristics of a three-dimensional anti-gate flash memory array including at least one auxiliary gate structure and 64 word lines.
Figure 7B is a graph of the saturation current (Id _sat ) of the three-dimensional inverse gate flash memory array at different interface trap densitys relative to the memory page, wherein the three-dimensional inverse gate flash memory The array includes at least one auxiliary gate structure and 64 word lines.
8A-8D are diagrams illustrating the effect of changing the offset distance between the auxiliary gate structure and the landing zone of a three-dimensional inverse gate flash memory array.
Figure 8E is a graph of saturation current (Id _sat ) versus offset distance of a three-dimensional inverse gate flash memory array on different memory pages, wherein the three-dimensional inverse gate flash memory array includes at least one auxiliary Gate structure.
The 9A~9B diagram is a current-voltage (Id-Vg) characteristic curve for describing a different auxiliary gate structure of a three-dimensional anti-gate flash memory array including at least one auxiliary gate structure on different memory pages. The electrical characteristics of the pressure.
Figure 9C is a graph of the saturation current (Id _sat ) of the three-dimensional inverse gate flash memory array on different memory pages relative to the auxiliary gate structure bias (AG bias), wherein the three-dimensional inverse gate flash memory array includes At least one auxiliary gate structure.
Figure 10 is a simplified block diagram of an integrated circuit of one embodiment of the present disclosure.

[0026]

The following is a detailed description of various embodiments in conjunction with the drawings. The detailed structure and process steps set forth in the following examples are for illustrative purposes only and are not intended to limit the scope of the invention. The scope of the invention is defined by the scope of the appended claims. Modifications or variations of the steps and structural details may be made by those of ordinary skill in the art. Similar elements in different embodiments are labeled with like reference numerals.

[0027]

2 is a perspective view 200 of a three-dimensional inverse gate flash memory array including an auxiliary gate structure 212 disposed on a plurality of stacks 202, 203, 204 Above 205, and between a plurality of select gate structures (eg, 406, 408) and one of a plurality of semiconductor contact pads 245, 246, 247, 248. As in the embodiment shown in Fig. 2, a string selection line/ground selection line can be used in combination with oxygen/oxygen oxide (SSL/GSL ONO).

[0028]

As shown in FIG. 2, the array includes a plurality of semiconductor stripes (e.g., 221, 223, 225, and 227) at a plurality of levels to form a plurality of stacks 202, 203, 204, 205. The semiconductor strip includes a film strip made of a semiconductor material for use as a channel for the anti-gate string. The semiconductor strip can be lightly doped n-type or p-type or fully doped, thus acting as a channel for the memory cell. For example, the semiconductor strips 221, 223, 225, 227 may be lightly doped with relatively low concentrations of impurities, for example having a doping concentration of about 10 ¹⁵ cm ^-3 , or may also be an internally undoped semiconductor material.

[0029]

The semiconductor strip stacks 202, 203, 204, 205 include a plurality of semiconductor strips and a plurality of insulating strips arranged in a staggered manner. In one embodiment, stack 202 includes a plurality of semiconductor strips 221, 223, 225, 227 and a plurality of insulating strips 220, 222, 224, 226 arranged in a staggered manner, while stack 205 includes semiconductor strips 229 and insulating strips 228 that are staggered. In one embodiment, the sides of the insulating strip are recessed relative to the sides of the semiconductor strip such that at least one side of the stack includes a plurality of recesses between the plurality of semiconductor strips.

[0030]

One end of each of the semiconductor strip stacks 202, 203, 204, 205 terminates in a stack of a plurality of semiconductor contact pads, and the other end terminates in a source line. For example, the semiconductor strips 221, 223, 225, 227 terminate in a stack of semiconductor contact pads 245, 246, 247, 248 at a proximal end and a gate structure (eg, 406) through a ground select line. The end of the semiconductor strip terminates at the source line end (not shown).

[0031]

The stack of semiconductor contact pads 245, 246, 247, 248 terminates the semiconductor strips, such as semiconductor strips 221, 223, 225, 227. Semiconductor contact pads 245, 246, 247, 248 are electrically coupled to different bit lines to connect the decoding circuitry to selected planes in the array. Patterning of such semiconductor contact pads 245, 246, 247, 248 can occur simultaneously when defining a plurality of ridge-shaped stacks.

[0032]

The semiconductor contact pads 245, 246, 247, 248 of the various blocks in the array may be arranged in a stepped configuration, similar to that shown in Figure 1, and having landing zones 233, 234, 235, 236 for placement in a stepped Successive individual bit lines for each step of the structure. The stack of semiconductor contact pads 245, 246, 247, 248 can be configured in a simple step pattern or other suitable pattern. The interlayer conductor (e.g., 191) is coupled to a plurality of bit lines in the semiconductor contact pads 245, 246, 247, 248 and over the patterned conductor layer (e.g., ML3 as shown in Fig. 1). The overlying bit line is connected to a peripheral circuit used to support a three-dimensional vertical gate memory array. For example, a plurality of interlayer conductors can be coupled to the plurality of patterned conductor layers of the semiconductor contact pads 245, 246, 247, 248 overlying the page buffer. The page buffer can store data written to or read from a selected memory cell in the three-dimensional vertical gate memory array.

[0033]

The landing zones 233, 234, 235, 236 are exposed from a plurality of openings in the stack of semiconductor contact pads 245, 246, 247, 248, and the stack of semiconductor contact pads 245, 246, 247, 248 provides a plurality of connection posts to A semiconductor contact pad and an overlying conductor are connected. Conductor contact pads 245, 246, 247, 248 may be formed via one or more patterning and etching processes, wherein a decreasing height of a masking layer is used to form each exposed landing zone. The details of the various fabrication methods of the stepped structure are described, for example, in U.S. Patent No. 8383512, which is commonly owned by the assignee of the present application, and whose filing date is May 14, 2011, the name of which is "manufacture of a multilayer connection structure". Method for Making Multilayer Connection Structure, the inventors are Chen Shihong, Lu Yiting, Li Hongzhi, and Yang Jincheng. This patent is hereby incorporated by reference and referenced in its entirety.

[0034]

In one embodiment, regions 237, 238, 239, 240 in landing regions 233, 234, 235, 236 have higher regions 241, 242, 243, 244 than semiconductor contact pads 245, 246, 247, 248. Doping concentration. According to some embodiments, it may be accomplished by implanting impurity implantation impurities with impurities on landing zones 233, 234, 235, 236. In one embodiment, the impurities may have the same conductivity type (n-type or p-type) as the semiconductor strips 221, 223, 225, 227 or the semiconductor contact pads 245, 246, 247, 248. In another embodiment, the impurities may have a different conductivity type than the semiconductor strips 221, 223, 225, 227 or the semiconductor contact pads 245, 246, 247, 248. The four semiconductor contact pads 245, 246, 247, 248 of the four active layers and the stacks 202, 203, 204, 205 of the corresponding active strip layers are shown in the figure, wherein the semiconductor contact pads 245, 246, 247, The stack of 248 is front-facing. The insulating strips between the semiconductor contact pads are not shown in the drawings to present structural features more clearly.

[0035]

In one embodiment, the impurity component is introduced into the outer peripheral region of the contact pad at one or more oblique incident angles for implantation, wherein the tilt angle is, for example, 0 relative to the normal substrate surface. 45 or 89 degrees, commonly referred to as the tilt angle. At the time of implantation, the substrate at the bottom of the stacks 202, 203, 204, 205 can also be rotated in the XY plane such that the impurity ions can pass through one or more incident angles relative to the crystal plane of the substrate (rotation angle (twist) Angle)) Incident. In various embodiments, the tilt angle, the rotation angle, the ionic strength, and other causes may be appropriately selected such that the regions 237, 238, 239, 240 in the landing regions 233, 234, 235, 236 are formed to have a lower resistance. Value, so in some embodiments, the semiconductor contact pads 245, 246, 247, 248 may not be fabricated in a layer-by-layer doping manner.

[0036]

Also, impurities can be implanted while covering the stacks 202, 203, 204, 205 with a mask layer, such that the implant process does not substantially alter the resistance of the active strip material in the active layer.

[0037]

The dielectric charge storage layer 232 can be a multilayer dielectric layer, such as an oxynitride (ONO) dielectric material, that can be used for charge storage of memory cells. A small sidewall recess can be obtained via an optimized process. According to an embodiment, a conformal oxygen-oxygen oxide structure is deposited on the sidewalls of the semiconductor stripes 221 to 227. In another embodiment, the dielectric charge storage layer 232 is deposited on at least a plurality of stacked sidewalls prior to word line formation.

[0038]

The three-dimensional anti-gate flash memory array as shown in FIG. 200 may also include an auxiliary gate structure 212 disposed adjacent to the semiconductor contact pads 245, 246, 247, 248. The distance between the auxiliary gate structure 212 and the semiconductor contact pads is very small, separated only by the dielectric charge storage layer 232. In one embodiment, the auxiliary gate structures 212 are orthogonally disposed on the semiconductor strip stacks 202, 203, 204, 205. In another embodiment, the auxiliary gate structure 212 has a surface conformal to the semiconductor strip stacks 202, 203, 204, 205 and fills a plurality of trenches (eg, 270) defined by the stacks 202, 203, 204, 205, And a multilayer array of interface regions at the intersections of the side surfaces of the strips of semiconductor material on the stacks 202, 203, 204, 205 is defined.

[0039]

In some embodiments, the auxiliary gate structure 212 includes a vertical portion 213 that is adjacent to at least one side of the stack 202, 203, 204, 205, and the auxiliary gate structure 212 includes a horizontally extending portion 214 at the vertical portion 213. One side. In some embodiments, the horizontally extending portion 214 is overlaid on at least one side of the semiconductor contact pads 245, 246, 247, 248. In still other embodiments, the auxiliary gate structure 212 includes a conductor 228 overlying the semiconductor strip stacks 202, 203, 204, 205, and a plurality of vertical gate structures (eg, 213) are positioned between the stacks. In some embodiments, the dielectric charge storage layer (e.g., 232) is disposed as a gate dielectric layer and between the vertical gate structure and the semiconductor strip.

[0040]

Applying a gate voltage to the auxiliary gate structure 212 may result in a partial inversion channel (eg, increasing the concentration of charge carriers) formed in the plurality of semiconductor stripes 221, 223, 225, 227 and lowering the semiconductor stripes 221, 223 The resistance of the semiconductor contact pads 245, 246, 247, 248 on 225, 227 to the current path of the memory cell.

[0041]

Moreover, applying a gate voltage to the auxiliary gate structure 212 can immediately result in a partial inversion channel and reduce the resistance in the region between the auxiliary gate structure 212 and the stack of semiconductor contact pads 245, 246, 247, 248. .

[0042]

Moreover, applying a gate voltage to the auxiliary gate structure 212 can immediately cause a partial inversion channel and reduce the area in the stack of semiconductor contact pads 245, 246, 247, 248 adjacent to the auxiliary gate structure 212. Resistance value.

[0043]

Due to the stepped structure of the stacked semiconductor contact pads 245, 246, 247, 248, the semiconductor contact pads 245, 246, 247, 248 are stacked to the semiconductor strips 221, 223, on various horizontal planes of the three-dimensional anti-gate flash memory array. The current path of 225, 227 can be a non-uniform load. The auxiliary gate structure 212 passes immediately between the region between the auxiliary gate structure 212 and the stack of semiconductor contact pads 245, 246, 247, 248 and immediately adjacent to the semiconductor contact pads 245, 246, 247 of the auxiliary gate structure 212, The region in the stack of 248 creates an inversion channel to solve this technical problem. This inversion channel reduces the resistance in the semiconductor strips 221, 223, 225, 227 and thus improves the current path of the stack of semiconductor contact pads 245, 246, 247, 248 to the semiconductor strips 221, 223, 225, 227.

[0044]

3 is a side view 300 of a three-dimensional inverse gate flash memory array in which lateral auxiliary gate structures 327, 328 are disposed over a stack (eg, 317 and 318) and are located at ground select line gate structure 302 and The string selects between the line gate structures 308a-308b.

[0045]

In a three-dimensional memory device, such as shown in FIG. 1, there may be a relatively high resistance channel (eg, semiconductor strips 112-115 and 102-05) through a string select line gate structure (eg, 119 and 109) and The gate structure of the ground selection line (eg, 126 and 127) reduces the performance of the three-dimensional memory device.

[0046]

Any one of the semiconductor strip stacks is coupled to one of the opposite sides of the stack of semiconductor contact pads of the three-dimensional anti-gate flash memory array, but is not coupled to both sides at the same time. In the array as shown in FIG. 1, one semiconductor strip stack has two opposite orientations, and the opposite orientation is from the semiconductor contact pad end to the source line end bit or source line end to the semiconductor contact pad end. Position. For example, stack 317 of semiconductor strips 310, 312, 314, 316 has a semiconductor contact pad end to source line end orientation, and stack 318 of semiconductor strips 319, 321, 323, 325 has source line end to semiconductor contacts The end of the pad is oriented. In other embodiments, the interleaved pattern as described above may not be employed, and the semiconductor contact pads and the string selection structure may both be disposed on one side of the block.

[0047]

A semiconductor strip is stacked on the semiconductor strip to form a vertical word line (not shown) and a vertical ground select line gate structure 302. The string select line gate structures 308a-308b are also overlaid with a stack of semiconductor stripes. The string select line gate structures 308a-308b overlie the top ends of the semiconductor strips of each of the spaced apart semiconductor strip stacks and overlie the bottom ends of the other set of semiconductor strips stacked one at a time. In either of these two examples, string select line gate structures 308a-308b control the electrical connection between any of the semiconductor strip stacks and their corresponding semiconductor contact pad stacks.

[0048]

In one embodiment, the ground select line gate structure 302 and the string select line gate structures 308a-308b may be formed via an anisotropic etch. Isotropic etching produces a well-controlled profile such that the outer surface of the horizontally extending portion of the gate structure can be flat or perpendicular to the ground compared to the overhanging semiconductor strips 309, 311, 313, 315. Chemical.

[0049]

3 shows that one side of the string select line gate structure 308b is spaced apart from the ground select line gate structure 302 along the stack. The ground select line gate structure 302 can be used as a ground select line, and the string select line gate structures 308a-308b can be used as a string select line. When a voltage is applied to the string select line gate structures 308a-308b to turn on the SSL switch (not including the transistor), the channel region in the semiconductor strip is turned on to induce an inversion layer in the semiconductor strip. Similarly, when a voltage is applied to the ground select line gate structure 302 to turn on the ground select line switch (GSL switch) (the transistor is not included), the channel region in the semiconductor strip is turned on, inducing the inversion layer in the semiconductor strip.

[0050]

A contact plug 306 couples the semiconductor strip to a source contact 305. Contact plug 306 may include doped polysilicon, tungsten, or other vertical interconnect techniques. Although not shown in the figures, the contact plug 306 contacts each layer in the stack, including a plurality of semiconductor strips (eg, 309, 311, 313, 315, 319, 321, 323, 325). In one embodiment, the difference in height between the contact plug 306 and the bottom of the stack provides a better insulation and process window between the source contact 305, the ground select line gate structure 302, and the string select line gate structures 308a-308b ( Process window). In one embodiment, source contact 305 is approximately 0.12 microns in length and is coupled to contact plug 306 having a length of 0.07 microns.

[0051]

In one embodiment, the three-dimensional inverse NAND flash memory array as shown in FIG. 3 utilizes lateral auxiliary gate structures 327 and 328 to reduce the resistance of the stack of semiconductor stripes in the stack, such stacks comprising staggered semiconductor strips (eg, 309, 311, 313, 315, 319, 321, 323, 325) and insulating strips (eg, 310, 312, 314, 320, 322, 324, 326). This effect can be achieved by providing lateral auxiliary gate structures 327 and 328 between ground select line gate structure 302 and string select line gate structure 308b, respectively. When a voltage is applied to the lateral auxiliary gate structures 327 and 328, an inversion layer having a lower resistance is formed in the semiconductor strip and under the gate structures 302 and 308b.

[0052]

Lateral auxiliary gate structures 327 and 328 are coupled to ground select line gate structure 302 and string select line gate structure 308b and may be extensions of ground select line gate structure 302 and string select line gate structure 308b. Unlike the ground select line gate structure 302 and the string select line gate structure 308b, the lateral auxiliary gate structures 327 and 328 do not overlap the semiconductor strips 309, 311, 313, 315, 319, 321, 323, 325, and thus may Prevent contact.

[0053]

In other embodiments, applying a gate voltage to the lateral auxiliary gate structures 327 and 328 may cause a partial inversion channel to be formed in the stack 318 of the semiconductor stripes 319, 321, 323, 325, and adjacent to the stack 317. The source line ends to the semiconductor contact pad end.

[0054]

Such stacks are coated with a dielectric material, such as an oxygen oxynitride (ONO) material, to provide a gate dielectric layer and to prevent shorting of the semiconductor strips and lateral auxiliary gate structures 327 and 328 in the stack.

[0055]

FIG. 4A is a schematic diagram 400A of the three-dimensional anti-gate flash memory array as shown in FIG. 2. This device can be made to have a 43 nm half-pitch. In this simulation result, the character line in the center is selected to be read. The schematic of Fig. 4A is used to simulate and fabricate a four-layer vertical gate, thin film transistor, and band gap engineered yttria oxide enthalpy oxide (BE-SONOS) charge trapping anti-gate device. This device was made to have a half pitch of 75 nm. The thickness of the channel is approximately 43 nm.

[0056]

In the schematic diagram as shown in FIG. 4A, the stack 202 of semiconductor strips 221, 223, 225, 227 is horizontal. In diagram 400A, adjacent semiconductor strip stacks are staggered to have opposite orientations, that is, semiconductor contact pad end to source line end orientation and source line end to semiconductor contact pad end. For example, the stack 202 terminates in a stack of semiconductor contact pads 245, 246, 247, 248; wherein a stack of semiconductors adjacent to the stack 202 (not shown) has semiconductor strips that do not terminate at the semiconductor contact pads 245, 246 The stack of 247, 248 terminates at the source line (not shown in the figure). Also, a stack of semiconductor strips each stacked one semiconductor strip runs from the top semiconductor contact pad structure to the bottom source line. Another set of semiconductor strips each stacked one semiconductor strip stack runs from the top source line to the bottom semiconductor contact pad structure.

[0057]

One end of the stack 202 of semiconductor strips 221, 223, 225, 227 terminates in a stack of semiconductor contact pads 245, 246, 247, 248, through a string select line gate structure 408, a ground select line gate structure 406, a word line 404 The ground selects the gate gate structure 402 and terminates at the other end on a source line (not shown). The stack 202 of semiconductor strips 221, 223, 225, 227 does not reach the stack of semiconductor contact pads at the opposite ends of the three-dimensional anti-gate flash memory array.

[0058]

A layer of memory material separates word lines 404 from semiconductor strips 221, 223, 225, 227. Similar to the word lines, the ground select line gate structures 406 and 402 are conformal to a plurality of ridge stacks.

[0059]

In one embodiment, the auxiliary gate structure 212 is disposed adjacent to the semiconductor contact pads 245, 246, 247, 248. The distance between the auxiliary gate structure 212 and the semiconductor contact pads is very small, separated only by the dielectric charge storage layer 232. In one embodiment, the auxiliary gate structures 212 are orthogonally disposed on the semiconductor strip stack 202. In another embodiment, the auxiliary gate structure 212 has a surface conformal to the semiconductor strip stack 202.

[0060]

Applying a gate voltage to the auxiliary gate structure 212 may result in a local inversion channel (eg, increasing the concentration of charge carriers) formed in the plurality of semiconductor stripes 221, 223, 225, 227 and reduced The resistance of the semiconductor contact pads 245, 246, 247, 248 on the semiconductor strips 221, 223, 225, 227 to the current path of the memory cell. The semiconductor strips 221, 223, 225, 227 have a semiconductor contact pad end to source line end orientation.

[0061]

In the illustrated embodiment, applying a gate voltage to the auxiliary gate structure 212 can immediately result in a partial inversion channel in region 410 (as indicated by the dashed line) that is adjacent to the auxiliary gate structure 212. The semiconductor contacts are stacked in a stack of pads 245, 246, 247, 248.

[0062]

Moreover, applying a gate voltage to the auxiliary gate structure 212 can immediately cause a partial inversion channel and reduce the area in the stack of semiconductor contact pads 245, 246, 247, 248 adjacent to the auxiliary gate structure 212. Resistance value.

[0063]

In the illustrated embodiment, applying a gate voltage to the auxiliary gate structure 212 may result in a partial inversion channel being formed in a plurality of semiconductor strip stacks adjacent to the stack 202 (not shown), the stacks having The source line ends to the semiconductor contact pad end and does not terminate in the stack of semiconductor contact pads 245, 246, 247, 248, but terminates in the source line (not shown).

[0064]

FIG. 4B is an enlarged schematic diagram 400B of the schematic diagram shown in FIG. 4A, and is used to describe the pitch and cell size of the three-dimensional anti-gate flash memory array as shown in FIG. Similar component numbers are used in the drawings, and the related description will not be repeated here. The simulations of Figures 400A and 400B were performed in Computer Aided Design (TCAD), a simulation tool provided by Synopsys, Inc., which supports the simulation of random grain boundaries and trap locations of memory cells.

[0065]

In order to simplify the structure of the simulation and improve the efficiency of the simulation, a two-dimensional junction-free vertical gate reversal with p-channel doping and a half pitch of 43 nm as shown in Fig. 4A is used. The gate flash structure is used for simulation. In the simulation, the p-type channel has a doping concentration of 1e15 cm ^-3 . The channel thickness (BL CD) is 30 nm. The number of simulated word lines is six and has one string select line (SSL) / ground select line (GSL). The width of the word line is 30 nm, and the channel width of the string select line (SSL)/ground select line (GSL) is 0.25 micron. The oxygen-oxygen (ONO) structure has a thickness of 5/7/10 nm or 22 nm and has a 20 nm thick p+ polysilicon gate. The p-type doping concentration of this polysilicon gate is 5e19 cm ^-3 . A semiconductor contact pad having a length of 0.5 microns is relatively lightly doped or undoped compared to a landing zone having a length of 0.3 microns. In other embodiments, different parameters than those described above may be employed.

[0066]

Regarding the junction type, the p+ junction is used for the string selection line (SSL)/ground selection line (GSL), wherein the device inside the gate array is a junctionless surface. In order to extract the features of the memory unit, it is selected to read the central word line. When the transfer characteristics of the selected cell are read, 6V is applied as the pass gate voltage, and 3V is set to the string select line (SSL)/ground select line (GSL). The drain voltage is 1V. When the drain current is 100 nA, V _t is defined as the gate voltage. The position and shape of the grain boundaries are set to be randomly generated in the simulation. To further simplify the analysis of the grain boundary effect, at least one artificial limitation is set such that the grain size is 50 nm. In other embodiments, other different artificial constraints may be employed, such as a grain angle of between ±45°.

[0067]

Regarding the interface trap density (Dit), the interface capture concentration (Dit) is defined as the density of electrical traps located at the interface of the two layers of the memory array 200. It should be noted that the terms "interface capture concentration" and "Dit" in this article mean the same meaning. Dit is an important parameter because its parameter has an effect on the mobility of electrical carriers in multiple layers of a multilayer wafer.

[0068]

According to an embodiment, the auxiliary gate structure 212 may have a length of 0.13 microns and a width of 22 nanometers. A plurality of landing zones are adjacent to the auxiliary gate structure 212 and are located within the perimeter of the stack of semiconductor contact pads 245, 246, 247, 248, such as landing zone 233. In one embodiment, the distance between the auxiliary gate structure 212 and the landing zone 233 is 0.05 microns.

[0069]

In the following description, different device parameters are evaluated in terms of the performance of the memory unit. Please refer to Figures 5A-5B for two graphs 500A, 500B. All geometric conditions are fixed, so the variation of the current-voltage (Id-Vg) characteristic curve comes from different interface capture concentrations and randomly distributed grain boundaries.

[0070]

An electrical feature of a three-dimensional inverse gate flash memory array including at least one auxiliary gate structure is described in Figure 5A, which presents the gate current (Id) of the memory array as a function of the drain voltage (Vg). In particular, Figure 500A presents the effect of using a polycrystalline germanium having a grain size of 50 nm and an interface capture concentration of 5e12 cm ^-2 ev ^-1 on memory cell performance. In other embodiments, other device characteristics may also be employed, such as channel length, channel width, bit line voltage, programming time, erase time, program-erase cycling, and conduction band. ).

[0071]

In FIG. 500A, three current-voltage (Id-Vg) characteristic curves are shown: a solid line indicates a characteristic curve of the memory array having a memory page number of 0, and a first broken line indicates a memory page having a memory page number of 6. The curve and the second broken line indicate the characteristic curve of the memory array having a memory page number of 14. Comparing these three characteristic curves, it can be seen that the turn-on current of the memory page 0 flowing into the memory array is greater than 1.5 to 2.3 times of the memory page 6 and the memory page 14, respectively. When the memory array is turned on by applying a threshold voltage higher than a threshold voltage, for example, +10V to +15V, the turn-on current represents a drain current.

[0072]

An electrical characteristic of a three-dimensional inverse gate flash memory array including at least one auxiliary gate structure can also be referred to FIG. 5B, which shows the relationship between the gate current (Id) of the memory array and the gate voltage (Vg). . In particular, graph 500B presents the effect on the performance of memory cells using polycrystalline germanium having a grain size of 50 nm and an interface capture concentration of 1e13 cm ^-2 ev ^-1 . In other embodiments, other device characteristics may also be employed, such as channel length, channel width, bit line voltage, programming time, erase time, program erase cycle, and conduction band.

[0073]

In FIG. 500B, five current-voltage (Id-Vg) characteristic curves are shown: a solid line indicates a characteristic curve of the memory array having a memory page number of 0, and a first broken line indicates that the number of memory pages of the memory array is 2. The characteristic curve, the second broken line indicates a characteristic curve of the memory array having a memory page number of 6, the third broken line indicates a characteristic curve of the memory array having a memory page number of 10, and the fourth broken line indicates that the number of memory pages of the memory array is 14. Characteristic curve. Comparing these five characteristic curves, it can be seen that the turn-on current of the memory page 0 flowing into the memory array is 1 to 2 times larger than that of the memory pages 2, 6, 10, 14, respectively.

[0074]

Three typical examples are used to evaluate the effects of varying interface capture concentrations and random grain boundary effects. Figure 5C is a graph 500C depicting the relationship of saturation current (Id _sat ) versus memory page for different crystalline yttrium forms. In graph 500C, a solid curve A with a circle represents the saturation current (Id _sat ) discrepancy between memory pages 0 and 14 of a single crystal germanium implant of a three-dimensional inverse gate flash memory array. In this embodiment, curve A is the relationship of the simulated saturation current with respect to the number of pages in which there are no grain boundaries in the channel. As shown in FIG. 5C, the saturation current of the memory page 0 is greater than 1.9 times the saturation current of the memory page 14.

[0075]

Curves B and C are modeled according to the same geometric state parameters, with the difference being the state of the grain boundary and interface capture concentration. However, the unique memory unit characteristics of the two are as follows.

[0076]

The dashed curve B with an inverted triangle represents the saturation current (Id _sat ) discrepancy between the memory pages 0 and 14 of the polysilicon stack of the three-dimensional inverse gate flash memory array. In this embodiment, the interface capture concentration of the polysilicon is

5e12 cm ^-2 ev ^-1 . It should be noted that the saturation current of the memory page 0 is 2.3 times the saturation current of the memory page 14. Furthermore, the dashed curve C with squares represents the saturation current (Id _sat ) discrepancy between the memory pages 0 and 14 of the polysilicon stack of the three-dimensional inverse gate flash memory array. In this embodiment, the interface capture concentration of the polysilicon is 1e13 cm ^-2 ev ^-1 . It should be noted that the saturation current of the memory page 0 is 2.0 times the saturation current of the memory page 14.

[0077]

Therefore, the saturation current (Id _sat ) discrepancy between the memory pages 0 and 14 becomes higher as the grain size effect is considered. Nonetheless, according to other embodiments, this variation is reduced as the interface capture concentration increases. 6A-6F depict the effect of implanting impurities into a semiconductor contact pad of a three-dimensional anti-gate flash memory array, wherein the three-dimensional inverse gate flash memory array includes at least one auxiliary gate structure. In particular, Figure 6A is a schematic 600A of a memory array in which a semiconductor contact pad of the memory array is completely and uniformly doped via a tilt-angle array implantation. In particular, the schematic of Figure 6A is used to simulate the fabrication and use of a four-layer vertical gate, thin film transistor, and band gap engineered yttria oxide (BE-SONOS) charge trapping anti-gate device. This device was made to have a half pitch of 75 nm. About 4F ² channel thickness of 43 nm.

[0078]

Also, in FIG. 6A, the doping of the semiconductor contact pads is described by visual hashing of the semiconductor contact pads 245. In this embodiment, it is selected to read the word line in the center. Grain boundaries with a limited range of grain sizes and angles are randomly generated. Similar component numbers are used in the drawings, and the related description will not be repeated here. The Model 600A was performed using Computer Aided Design (TCAD).

[0079]

Please refer to FIG. 6B to FIG. 6D, which illustrate three current-voltage (Id-Vg) characteristic graphs 600B, 600C, and 600D. All geometric conditions are fixed, so the variation of the current-voltage (Id-Vg) characteristic curve comes from different doping concentrations.

[0080]

An electrical feature of a three-dimensional inverse gate flash memory array including at least one auxiliary gate structure is described in Figure 6B, which presents the gate current (Id) of the memory array as a function of the drain voltage (Vg). In particular, graph 600B presents the effect of doping the semiconductor contact pads at an ion concentration of 1e17 cm ^-3 . The crystalline ruthenium has a grain size of 50 nm and an interface capture concentration of 1e13 cm ^-2 ev ^-1 . In other embodiments, other device characteristics may also be employed, such as channel length, channel width, bit line voltage, programming time, erase time, program erase cycle, and conduction band.

[0081]

In FIG. 600B, three current-voltage (Id-Vg) characteristic curves are shown: a solid line indicates a characteristic curve of the memory array having a memory page number of 0, and a first broken line indicates a memory page having a memory page number of 6. The curve and the second broken line indicate the characteristic curve of the memory array having a memory page number of 14. Comparing these three characteristic curves, it can be seen that the turn-on current of the memory page 0 flowing into the memory array is greater than 0.1 to 0.7 times of the memory page 6 and the memory page 14, respectively.

[0082]

An electrical characteristic of a three-dimensional inverse gate flash memory array including at least one auxiliary gate structure can also be referred to FIG. 6C, which shows the relationship between the gate current (Id) of the memory array and the gate voltage (Vg). . Figure 600C presents the effect of doping the semiconductor contact pads at an ion concentration of 5e17 cm ^-3 . The crystalline ruthenium has a grain size of 50 nm and an interface capture concentration of 1e13 cm ^-2 ev ^-1 . In other embodiments, other device characteristics may also be employed, such as channel length, channel width, bit line voltage, programming time, erase time, program erase cycle, and conduction band.

[0083]

In FIG. 600C, three current-voltage (Id-Vg) characteristic curves are shown: a solid line indicates a characteristic curve of the memory array having a memory page number of 0, and a first broken line indicates a memory page having a memory page number of 6. The curve and the second broken line indicate the characteristic curve of the memory array having a memory page number of 14. Comparing these three characteristic curves, it can be seen that the turn-on current of the memory page 0 flowing into the memory array is greater than 0.1 to 0.2 times of the memory page 6 and the memory page 14, respectively.

[0084]

An electrical characteristic of a three-dimensional anti-gate flash memory array including at least one auxiliary gate structure can be further referred to FIG. 6C, which shows the relationship between the gate current (Id) of the memory array and the gate voltage (Vg). . In particular, graph 600D presents the effect of doping the semiconductor contact pads at an ion concentration of 1e18 cm ^-3 . The crystalline ruthenium has a grain size of 50 nm and an interface capture concentration of 1e13 cm ^-2 ev ^-1 . In other embodiments, other device characteristics may also be employed, such as channel length, channel width, bit line voltage, programming time, erase time, program erase cycle, and conduction band.

[0085]

In FIG. 600D, three current-voltage (Id-Vg) characteristic curves are shown: a solid line indicates a characteristic curve of the memory array having a memory page number of 0, and a first broken line indicates a memory page having a memory page number of 6. The curve and the second broken line indicate the characteristic curve of the memory array having a memory page number of 14. Comparing these three characteristic curves, it can be seen that the turn-on current of the memory page 0 flowing into the memory array is greater than 0.1 to 0.4 times of the memory page 6 and the memory page 14, respectively.

[0086]

Four typical examples are used to evaluate the effect of changing the doping concentration. Figure 6E is a graph 600E depicting the relationship of saturation current (Id _sat ) versus memory page for different crystalline germanium forms having different doping concentrations. In Figure 600E, a solid curve A with a circle represents the saturation current (Id _sat ) discrepancy between memory pages 0 and 14 of a three-dimensional inverse gate flash memory array, where the semiconductor contacts The mat is undoped.

[0087]

Curves B, C, and D are modeled according to the same geometric state parameters, with the difference being the state of the doping concentration. However, the unique memory unit characteristics of these three are as follows.

[0088]

The dashed curve B with an inverted triangle represents the saturation current (Id _sat ) discrepancy between memory pages 0 and 14 of the three-dimensional inverse gate flash memory array. In this embodiment, the semiconductor contact pads were doped at an ion concentration of 1e17 cm ^-3 .

[0089]

Furthermore, the dashed curve C with squares indicates the saturation current (Id _sat ) discrepancy between the memory pages 0 and 14 of the three-dimensional inverse gate flash memory array. In this embodiment, the semiconductor contact pads were doped at an ion concentration of 5e17 cm ^-3 .

[0090]

Further, a dashed curve D having a diamond shape indicates a saturation current (Id _sat ) discrepancy between memory pages 0 and 14 of a three-dimensional inverse gate flash memory array. In this embodiment, the semiconductor contact pads were doped at an ion concentration of 1e18 cm ^-3 .

[0091]

6F line graph of FIG. 600F, for the relationship between the ratio described with respect to dopant concentration and memory page 0 of the saturation current (Id _sat) / page memory 14 of the saturation current (Id _sat) of. When the doping concentration is 0, the saturation current of the memory page 0 is 2.0 times the saturation current of the memory page 14. When the doping concentration is 1e17 cm ^-3 , the saturation current of the memory page 0 is 1.3 times the saturation current of the memory page 14. Furthermore, when the doping concentration is 5e17 cm ^-3 , the saturation current of the memory page 0 is 1.65 times the saturation current of the memory page 14. Furthermore, when the doping concentration is 1e18 cm ^-3 , the saturation current of the memory page 0 is 1.59 times the saturation current of the memory page 14.

[0092]

Therefore, the saturation current (Id _sat ) discrepancy between the memory pages 0 and 14 decreases as the implantation causes the resistance value of the semiconductor contact pad to decrease.

[0093]

Due to the stepped structure of the stacked semiconductor contact pads 245, 246, 247, 248, the semiconductor contact pads 245, 246, 247, 248 are stacked to the semiconductor strips 221, 223, on various horizontal planes of the three-dimensional anti-gate flash memory array. The current path of 225, 227 can be a non-uniform load. As the number of memory pages increases from 16 to 32, different current lines increase. The auxiliary gate structure 212 passes immediately between the region between the auxiliary gate structure 212 and the stack of semiconductor contact pads 245, 246, 247, 248 and immediately adjacent to the semiconductor contact pads 245, 246, 247 of the auxiliary gate structure 212, The region in the stack of 248 creates an inversion channel to solve this technical problem. This inversion channel reduces the resistance in the semiconductor strips 221, 223, 225, 227 and thus improves the current path of the stack of semiconductor contact pads 245, 246, 247, 248 to the semiconductor strips 221, 223, 225, 227.

[0094]

Figure 7A is a current-voltage (Id-Vg) characteristic diagram for describing the electrical characteristics of a three-dimensional anti-gate flash memory array including at least one auxiliary gate structure and 64 word lines. In FIG. 700A, two current-voltage (Id-Vg) characteristic curves are shown: a solid line indicates a characteristic curve in which the number of memory pages of the memory array is 0, and a broken line indicates a characteristic curve in which the number of memory pages of the memory array is 14. Comparing the two characteristic curves, it can be seen that the turn-on current of the memory page 0 flowing into the memory array is larger than 0.1 to 0.2 times of the memory page 14. When the memory array is turned on by applying a threshold voltage higher than a threshold voltage, for example, +10V to +15V, the turn-on current represents a drain current.

[0095]

Figure 7B is a graph of the saturation current (Id _sat ) of the three-dimensional inverse gate flash memory array at different interface trap densitys relative to the memory page, wherein the three-dimensional inverse gate flash memory The array includes at least one auxiliary gate structure and 64 word lines. Diagram 700B, as shown in Figure 7B, depicts the relationship of saturation current (Id _sat ) for different interface trap densities relative to memory pages. In FIG. 700B, a solid curve A with a circle represents a saturation current (Id _sat ) discrepancy between memory pages 0 and 14 of a three-dimensional inverse gate flash memory array, wherein the interface captures At a concentration of 5e12 cm ^-2 ev ^-1 , the saturation current of memory page 0 is greater than 1.40 times the saturation current of memory page 14.

[0096]

The dashed curve B with an inverted triangle represents the saturation current (Id _sat ) discrepancy between memory pages 0 and 14 of the three-dimensional inverse gate flash memory array, wherein the interface capture concentration is 5e12 cm ^{- 2} ev ^-1 . It should be noted that the saturation current of the memory page 0 is 1.37 times the saturation current of the memory page 14.

[0097]

Therefore, for a three-dimensional inverse gate flash memory array having 64 word lines, the saturation current (Id _sat ) discrepancy is relatively unrelated to the interface capture concentration.

[0098]

Please refer to FIGS. 8A-8D for four current-voltage (Id-Vg) graphs 800A, 800B, 800C, and 800D. All geometric conditions are fixed, so the variation of the current-voltage (Id-Vg) characteristic curve is derived from the offset distance between the different auxiliary gate structures 212 and the landing zone 233.

[0099]

An electrical feature of a three-dimensional inverse gate flash memory array including at least one auxiliary gate structure is described with reference to FIG. 8A, which presents the relationship of the gate current (Id) of the memory array with respect to the drain voltage (Vg). In particular, diagram 800A presents the effect of the offset distance between the auxiliary gate structure 212 and the landing zone 233. In the embodiment as shown in Fig. 8A, the offset distance is 50 nm. In other embodiments, other device characteristics may also be employed, such as channel length, channel width, bit line voltage, programming time, erase time, program erase cycle, and conduction band.

【0100】

In FIG. 800A, two current-voltage (Id-Vg) characteristic curves are shown: a solid line indicates a characteristic curve in which the number of memory pages of the memory array is 0, and a broken line indicates a characteristic curve in which the number of memory pages of the memory array is 14. Comparing the two characteristic curves, it can be seen that the turn-on current of the memory page 0 flowing into the memory array is larger than 0.1 to 0.8 times of the memory page 14. When the memory array is turned on by applying a threshold voltage higher than a threshold voltage, for example, +10V to +15V, the turn-on current represents a drain current.

【0101】

An electrical characteristic of a three-dimensional anti-gate flash memory array including at least one auxiliary gate structure can also be referred to FIG. 8B, which shows the relationship between the gate current (Id) of the memory array and the gate voltage (Vg). . In particular, diagram 800B presents the effect of the offset distance between the auxiliary gate structure 212 and the landing zone 233. In the embodiment as shown in Fig. 8B, the offset distance is 100 nm. In other embodiments, other device characteristics may also be employed, such as channel length, channel width, bit line voltage, programming time, erase time, program erase cycle, and conduction band.

【0102】

In FIG. 800B, two current-voltage (Id-Vg) characteristic curves are shown: a solid line indicates a characteristic curve in which the number of memory pages of the memory array is 0, and a broken line indicates a characteristic curve in which the number of memory pages of the memory array is 14. Comparing the two characteristic curves, it can be seen that the turn-on current of the memory page 0 flowing into the memory array is larger than 0.1 to 0.6 times of the memory page 14. When the memory array is turned on by applying a gate voltage higher than 0 to 6 V as shown in FIG. 8B, the turn-on current represents the drain current.

【0103】

An electrical characteristic of a three-dimensional inverse gate flash memory array including at least one auxiliary gate structure can be referred to FIG. 8C, which presents the relationship between the gate current (Id) of the memory array and the gate voltage (Vg). In particular, diagram 800C presents the effect of the offset distance between the auxiliary gate structure 212 and the landing zone 233. In the embodiment as shown in Fig. 8C, the offset distance is 150 nm. In other embodiments, other device characteristics may also be employed, such as channel length, channel width, bit line voltage, programming time, erase time, program erase cycle, and conduction band.

[0104]

In FIG. 800C, two current-voltage (Id-Vg) characteristic curves are shown: a solid line indicates a characteristic curve in which the number of memory pages of the memory array is 0, and a broken line indicates a characteristic curve in which the number of memory pages of the memory array is 14. Comparing the two characteristic curves, it can be seen that the turn-on current of the memory page 0 flowing into the memory array is larger than 0.1 to 0.4 times of the memory page 14. When the memory array is turned on by applying a gate voltage higher than 0 to 6 V as shown in Fig. 8C, the turn-on current indicates the drain current.

【0105】

An electrical feature of a three-dimensional inverse gate flash memory array including at least one auxiliary gate structure can be referenced to FIG. 8D, which presents the relationship of the gate current (Id) of the memory array with respect to the drain voltage (Vg). In particular, diagram 800D presents the effect of the offset distance between the auxiliary gate structure 212 and the landing zone 233. In the embodiment as shown in Fig. 8D, the offset distance is 2000 nm. In other embodiments, other device characteristics may also be employed, such as channel length, channel width, bit line voltage, programming time, erase time, program erase cycle, and conduction band.

【0106】

In FIG. 800D, two current-voltage (Id-Vg) characteristic curves are shown: a solid line indicates a characteristic curve in which the number of memory pages of the memory array is 0, and a broken line indicates a characteristic curve in which the number of memory pages of the memory array is 14. Comparing the two characteristic curves, it can be seen that the turn-on current of the memory page 0 flowing into the memory array is larger than 0.1 to 0.2 times of the memory page 14. When the memory array is turned on by applying a gate voltage higher than 0 to 6 V as shown in Fig. 8C, the turn-on current indicates the drain current.

【0107】

Curves A and B are simulated according to the same geometric state parameters, the difference being the number of pages of the memory page. However, the unique memory unit characteristics of the two are as follows.

【0108】

Figure 8E is a graph 800E of the saturation current (Id _sat ) versus the offset distance of the memory array on different memory pages. In Fig. 800E, a solid curve A having a circle indicates a saturation current (Id _sat ) of the memory page 0 along a unit interval of 50 unit ranges of an offset distance of 50 to 200 nm. The dashed curve B with an inverted triangle represents the saturation current (Id _sat ) of the memory page 14 along the same offset distance range as the solid curve A.

【0109】

Therefore, extending the offset distance Loffset can more effectively reduce the saturation current of the memory page 0 because this causes the memory page 0 to have a larger string length than the memory page 14. As such, according to an embodiment, the saturation current (Id _sat ) discrepancy between the memory pages can be scaled down as the offset distance increases.

[0110]

The 9A~9B diagram is a current-voltage (Id-Vg) characteristic graph 900A-900B for describing a different auxiliary gate of a three-dimensional anti-gate flash memory array including at least one auxiliary gate structure on different memory pages. Electrical characteristics of the pole structure bias. As shown in FIG. 900A, for page 0 of the three-dimensional inverse gate flash memory array, the current-voltage (Id-Vg) characteristic curve is determined by the auxiliary gate structure bias voltage of 6V, 8V to 10V. As shown in FIG. 900B, for page 14 of the three-dimensional inverse gate flash memory array, the current-voltage (Id-Vg) characteristic curve is determined by the auxiliary gate structure bias voltages of 6V, 8V to 10V.

[0111]

Figure 9C is a plot 900C of the saturation current (Id _sat ) of the memory array on different memory pages relative to the auxiliary gate structure bias (AG bias). In FIG. 900C, a solid line curve A having a circle indicates a saturation current (Id _sat ) of the memory page 0 of two unit intervals along the range of the auxiliary gate structure bias voltage of 6V to 10V, which is higher. The saturation current deviation between the auxiliary gate structure bias and the lower auxiliary gate structure bias is in the range of 70 nA. The dashed curve B with an inverted triangle indicates the saturation current (Id _sat ) of the memory page 14 along the unit interval of the auxiliary gate structure bias voltage of 6V~10V, and the higher auxiliary gate structure is biased. The saturation current deviation between the voltage and the lower auxiliary gate structure bias is in the range of 130 nA.

[0112]

Therefore, applying a larger auxiliary gate structure bias (AG bias) can be used to reduce the resistance of the junctionless region of the semiconductor contact pad of the memory page 14, and only reverse the gate region for memory page 0. The resistance is reduced by this mechanism. As a result, the saturation current of the memory page 14 is greatly improved.

[0113]

Figure 10 is a simplified block diagram of an integrated circuit of one embodiment of the present disclosure. The integrated circuit line 1075 includes a three-dimensional inverse gate flash memory (memory array 1060) having, for example, a structure as shown in FIG. 2, such as on a semiconductor substrate, wherein each active layer has a lower resistance contact. pad. Column decoder 1061 is coupled to a plurality of word lines 1062 and is arranged along the columns in memory array 1060. Row decoder 1063 couples a plurality of string select lines 1064 along a row that correspond to a stack in memory array 1060 for reading and programming data from memory cells in array 1060. Planar decoder 1058 couples a plurality of planes in memory array 1060 via bit line 1059. The access system is applied to bus bar 1065 to row decoder 1063, column decoder 1061, and plane decoder 1058. In the present embodiment, the sense amplifier and data input structure is coupled to row decoder 1063 via data bus 1067 in block 1066. Data is provided via data input line 1071 from input/output ports on integrated circuit 1075 or from other data sources internal or external to integrated circuit 1075 data to block 1066. In the embodiment, the other circuit 1074 is included in the integrated circuit, such as a general purpose processor or a special application circuit system, or a system single chip is supported by the anti-gate flash memory cell array. A combination of modules of the (system-on-a-chip) function. The data is passed from the sense amplifier in block 1066 via data output line 1072 to the input/output port on integrated circuit 1075, or to other data endpoints internal or external to integrated circuit 1075.

【0114】

In one embodiment, the implementation of the controller uses a bias arrangement state machine 1069 to control the bias setting to provide a voltage application, which is generated or provided via a voltage supply or provider in block 1068. For example, read, erase, program, erase confirm or program verify voltage. The controller can be implemented using special logic circuitry known to those of ordinary skill in the art. In other embodiments, the controller includes a general purpose processor that can be implemented on the same integrated circuit that performs computer programming to control or operate the device. In still other embodiments, a combination of special purpose logic circuitry and a general purpose processor may be utilized in the implementation of the controller.

[0115]

The auxiliary gate structure decoder 1070 is a side voltage circuit and can be connected to a three-dimensional inverse NAND flash memory array 1060 that includes an auxiliary gate structure. In one embodiment, the auxiliary gate structure decoder 1070 applies a gate voltage in response to the address to select a memory cell in a block when the select gate structure is turned on. Applying a gate voltage to the auxiliary gate structure can result in a partial inversion channel (eg, increasing the concentration of charge carriers) formed in the plurality of semiconductor stripes adjacent to the auxiliary gate structure and reducing the semiconductor contact pads on the semiconductor strip The resistance of the current path to the memory cell.

[0116]

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

200‧‧‧ Figure

202, 203, 204, 205‧‧‧ stacking

212‧‧‧Auxiliary gate structure

213‧‧‧ vertical part

214‧‧‧ horizontal extension

220, 222, 224, 226‧‧ ‧ insulation strip

221, 223, 225, 227, 229‧‧ ‧ semiconductor strips

228‧‧‧Conductor

232‧‧‧ dielectric charge storage layer

233, 234, 235, 236 ‧ ‧ landing zone

237, 238, 239, 240, 241, 242, 243, 244 ‧ ‧ areas

245, 246, 247, 248‧‧ ‧ semiconductor contact pads

270‧‧‧ trench

Claims (21)

[Item 1] A memory device comprising:
A three-dimensional array of a plurality of memory cells having one or more blocks, the blocks comprising:
a plurality of layers comprising a plurality of semiconductor strips extending from a semiconductor contact pad, the layers being disposed such that the plurality of semiconductor stripes form a plurality of semiconductor strip stacks and one of the plurality of semiconductor contact pads Semiconductor contact pad stacking;
a plurality of select gate structures disposed on the plurality of semiconductor strip stacks between the semiconductor contact pads on the semiconductor strips and the memory cells, and the different ones of the select gate structures The plurality of semiconductor strips in the stack of semiconductor strips are coupled to the plurality of semiconductor contact pads in the layers; and an auxiliary gate structure disposed over the stack of semiconductor strips and located in the select gate structures and The semiconductor contacts the pads between the stacks.
[Item 2] The memory device of claim 1, wherein the semiconductor contact pads comprise a plurality of landing zones for a plurality of interlayer conductors, and wherein the memory device further comprises a plurality of openings in the semiconductor contact pad stack, The openings provide a plurality of vias connecting the landing regions overlying the interlayer contact conductors over the semiconductor contact pads.
[Item 3] The memory device of claim 2, further comprising a plurality of regions located in the landing regions, the doping concentration of the regions being higher than a doping concentration of the plurality of other regions of the plurality of semiconductor contact pads.
[Item 4] The memory device of claim 1, wherein the semiconductor strips comprise a plurality of anti-gate channels, and the memory device further comprises a plurality of word lines, the plurality of word lines being stacked on the word lines The word lines include a plurality of vertical gate structures between the plurality of semiconductor strip stacks.
[Item 5] The memory device of claim 1, wherein the auxiliary gate structure comprises a conductor overlying the plurality of semiconductor strip stacks, a plurality of vertical gate structures are disposed between the plurality of semiconductor strip stacks, and the memory device The method further includes a dielectric charge storage layer disposed as a gate dielectric layer between the vertical gate structures and the semiconductor stripes.
[Item 6] The memory device of claim 1, wherein the auxiliary gate structure comprises a conductor overlying the plurality of semiconductor strip stacks, a plurality of vertical gate structures are disposed between the plurality of semiconductor strip stacks, and the memory device Further comprising a gate dielectric layer, the gate dielectric layer being between the vertical gate structures and the semiconductor strips.
[Item 7] The memory device of claim 1, wherein at least one side of the auxiliary gate structure is separated by a gate dielectric layer and the semiconductor contact pads, and a reverse is induced under a bias voltage. The transfer channel is on one side of the semiconductor contact pads.
[Item 8] The memory device of claim 1, wherein the auxiliary gate structure is disposed over the plurality of semiconductor strip stacks and between the selected gate structures.
[Item 9] The memory device of claim 1, further comprising one or more lateral auxiliary gate structures connected to the selection gate structures.
[Item 10] A method of manufacturing a memory device, comprising:
Forming a plurality of layers of a plurality of memory cells, the layers comprising a plurality of semiconductor stripes extending from a semiconductor contact pad, the layers being disposed such that the plurality of semiconductor stripes form a plurality of semiconductor strip stacks and a plurality of a semiconductor contact pad stack of the semiconductor contact pad;
Forming a plurality of select gate structures, the select gate structures are disposed on the plurality of semiconductor strip stacks, and between the semiconductor contact pads on the semiconductor strips and the memory cells, the select gate structures A different one of the plurality of semiconductor strips is coupled to the plurality of semiconductor contact pads of the plurality of semiconductor strips; and an auxiliary gate structure is formed, the auxiliary gate structure being located on the plurality of semiconductor strips Above and between the select gate structures and the semiconductor contact pad stack.
[Item 11] The manufacturing method of claim 10, wherein the semiconductor contact pads comprise a plurality of landing zones for a plurality of interlayer conductors, and the manufacturing method further comprises forming a plurality of openings in the semiconductor contact pad stack, The openings provide a plurality of interconnecting pillars for connecting the landing zones to the plurality of interlayer conductors over the plurality of semiconductor contact pads.
[Item 12] The manufacturing method of claim 11, wherein the doping concentration of the plurality of regions in the landing zones is higher than the doping concentration of the plurality of other regions in the plurality of semiconductor contact pads.
[Item 13] The manufacturing method of claim 12, wherein the implanting impurities are used to form the regions having higher doping concentrations in the landing regions to reduce the resistance of the regions. The value is below the resistance of the other regions in the semiconductor contact pads.
[Item 14] The manufacturing method of claim 13, wherein the implanting impurity process comprises introducing an impurity component into the landing zones at a substantially normal angle of incidence.
[Item 15] The manufacturing method of claim 10, wherein the semiconductor strips comprise a plurality of anti-gate channels, and the manufacturing method further comprises forming a plurality of word lines, the plurality of word lines being overlying the semiconductor strips Stacking, the word lines include a plurality of vertical gate structures between the plurality of semiconductor strip stacks.
[Item 16] The manufacturing method described in claim 10 of the patent application further includes:
Before forming a plurality of word lines, a dielectric charge storage layer is formed on at least a plurality of sidewalls of the plurality of semiconductor strip stacks.
[Item 17] The manufacturing method of claim 16, wherein the auxiliary gate structure comprises a conductor overlying the plurality of semiconductor strip stacks, a plurality of vertical gate structures being disposed between the plurality of semiconductor strip stacks, and the dielectric charge The storage layer is disposed as a gate dielectric layer and is located between the vertical gate structures and the semiconductor stripes.
[Item 18] The manufacturing method of claim 10, wherein at least one side of the auxiliary gate structure is separated by a gate dielectric layer and the semiconductor contact pads, and a reverse is induced under a bias voltage. The transfer channel is on one side of the semiconductor contact pads.
[Item 19] The manufacturing method of claim 10, wherein the auxiliary gate structure comprises a horizontal portion that overlaps at least one side of the plurality of semiconductor contact pads.
[Item 20] The manufacturing method of claim 10, further comprising forming the auxiliary gate structure over the plurality of semiconductor strip stacks and between the selected gate structures.
[Item 21] The manufacturing method of claim 10, further comprising forming one or more lateral auxiliary gate structures connected to the selection gate structures.