TWI515876B - Contact structure and forming method - Google Patents

Description

Contact window structure and forming method

The present invention is directed to high density devices, and in particular, in embodiments of the present invention, a method of forming a three dimensional high density semiconductor device that is electrically connected to an active layer of a semiconductor device (e.g., a memory device).

The three-dimensional semiconductor device is formed by a stack in which a plurality of active layers and a plurality of insulating layers are alternately arranged. In a memory device, each layer can include a planar array of memory cells. In today's three-dimensional stacked memory devices, the active layer includes word lines and bits formed by active strips. Lines are used for memory cells that are alternately stacked to form a spaced-apart ridge-like structure. The active layers may be made of a doped (p-type or n-type doped) semiconductor material or an undoped semiconductor material. In the three-dimensional memory device of this type, the memory cells can be placed on the intersection of the stacked bit lines or the stacked word lines and the intersecting word lines or the intersecting bit lines to form a three-dimensional memory. Array.

One such method of connecting the interlayer conductor to the active layer is a multi-pass micro-developing etch process, which is disclosed in U.S. Patent No. 8,383,512, entitled For Making Connection Structure, the disclosure of which is hereby incorporated by reference. A further method is described in U.S. Patent Application Serial No. 13/735,922, filed on Dec.

In an example, a method of forming a stepped contact window structure is presented. A stack of alternating active layers and a plurality of insulating layers is formed as described below. Forming a first sub-stack comprising N active layers separated by the insulating layers, the N active layers including an upper boundary active layer. Forming a second sub-stack on the first sub-stack, the second sub-stack comprising M active layers, the M active layers being separated by the insulating layers, the M active layers comprising an upper boundary active layer. Forming a first sub-stack insulation layer between the first sub-stack layer and the second sub-stack layer, the first sub-stack insulation layer having a different one from the second sub-stack in a known etching step Etching time of the plurality of etching times of the insulating layers. Turn on the upper boundary active layers. And following the step of turning on the upper boundary active layer, turning on the remaining active layers of the first sub-stack and the second sub-stack, and stacking the active layers in the first sub-stack and the second sub-stack A landing area is created on a stepped structure. A plurality of interlayer conductors extending to the landing zones are formed, the interlayer conductors being separated by an insulating material.

In an example, a method of forming a stepped contact window structure is presented. A stack of alternating active layers and a plurality of insulating layers is formed as described below. The stack includes a plurality of sub-stacks having an active layer of an upper boundary, and the sub-stacks Having an insulating layer and a plurality of active layer pairs under the upper boundary active layer, the insulating layer and the active layer pairs forming a plurality of first layer pairs, the first layer pairs There are a plurality of consistent first sub-stack etch times in the known etch process. The stack also includes a plurality of second layer pairs, the second layer pairs including a plurality of sub-stack insulation layers, the sub-stack insulation layers being located between the sub-stacks, the second layer pair being The known etching process has a plurality of second sub-stack etch times that are different from the first sub-stack etch times; in one or more etch steps, the etch is performed to cause the stack to generate a plurality of openings, The etch depth of the opening stops at the upper boundary active layers. The openings are selected to be deeply etched to form a plurality of vias that expose a plurality of active layers within each of the sub-stacks. Forming a plurality of interlayer conductors in (1) the via holes to extend to the active layers, and (2) forming the interlayer conductors to extend to the openings when the openings are not deeply etched The active layer of the boundary.

In one example, a stepped contact window structure includes a stack of alternating active and insulating layers, the stack being non-simple, such that at least one of the following conditions is for the same etch process (1) active layer The etching time is different, or (2) the etching time between the insulating layers is different. A landing structure of a stepped structure is above the active layers, the interlayer conductors extending to a landing zone of the stepped structure, the interlayer conductors being separated by an insulating material.

For a better understanding of the above, the advantages and other aspects of the present invention, the preferred embodiments are described below, and in the accompanying drawings,

ML1, ML2, ML3‧‧‧ metal layer

100‧‧‧Semiconductor device

102~105, 112~115‧‧‧ active layer belt

102B, 103B, 104B, 105B, 112B, 113B, 114B, 115B‧‧‧ semiconductor pads

102C1, 102C2, 102C3, 103C1, 103C2, 104C1‧‧‧ semiconductor board opening

119‧‧‧Source line terminal

125-1~125-N‧‧‧Interlayer conductor

126‧‧‧ Grounding selection gate

127‧‧‧ gate selection line

128, 252‧‧‧ source line

152‧‧‧ memory material layer

154‧‧‧Deuterated metal layer

200, 330‧‧‧ Stacking

202, 202.2, 202.3, 202.4‧‧‧ alternating active layers

202.1‧‧‧Upper boundary active layer

204, 204.1, 204.2, 312‧‧ insulation

204.3‧‧‧The third insulation layer

206, 278, 328‧‧‧ first etch shield

212, 284, 336 ‧ ‧ second etch shield

220, 290, 352‧‧‧ third etching shield

298, 364‧‧‧ fourth etch shield

304, 332‧‧‧ fifth etching shield

208, 280‧‧‧ first etched shield opening

214, 286‧‧‧ second etched shield opening

222, 292.1, 292.2‧‧‧ third etched shield opening

299‧‧‧4th etched shield opening

306‧‧‧ fifth etched shield opening

224‧‧‧The upper active layer reveals the area

228, 234, 334‧‧‧ active layer 202.1 exposed area

226, 230‧‧‧ active layer 202.2 revealed area

230, 232‧‧‧ active layer 202.3 exposed area

236‧‧‧ stepped structure

238, 310, 358‧‧‧ landing zone

250, 370‧‧‧Contact window structure

252‧‧‧Sub-stacking

252.1‧‧‧First sub-stacking

252.2‧‧‧Second sub-stacking

252.3‧‧‧ Third sub-stacking

252.4‧‧‧ Fourth sub-stacking

254‧‧‧ layer pairs

262‧‧‧Second layer

264‧‧‧ third layer pair

266‧‧‧Fourth pair

256, 258, 260‧ ‧ sub-stack insulation

268‧‧‧Upper insulation

270‧‧‧lower insulation

272, 372‧‧ ‧ interlayer conductor

274‧‧‧ Sidewall insulation

282‧‧‧First etching opening

288‧‧‧Second etching opening

294‧‧‧ Third etching opening

296‧‧‧fourth etching opening

300‧‧‧ partially etched structure

302‧‧‧ openings

308, 368‧‧‧through holes

314‧‧‧Side wall insulation

318‧‧‧Upper opening

331‧‧‧Shielding section

338, 340, 342, 344‧‧‧ surface

348, 349, 350, 351‧‧ ‧ exposed surface area

354, 356‧ ‧ shear etching shield

360‧‧‧Barrier

362‧‧‧Insulation materials

370‧‧‧Contact window structure

975‧‧‧ integrated circuit

958‧‧‧ Planar Decoder

959‧‧‧ bit line

960‧‧‧Three-dimensional flash memory array

961‧‧‧ column decoder

962‧‧‧ character line

963‧‧‧ row decoder

964‧‧‧SSL line

965‧‧‧ address input line

966‧‧‧Sense amplifier/data input structure

968‧‧‧ bias voltage supply voltage

969‧‧‧ state machine

971‧‧‧ data input line

972‧‧‧ data output line

974‧‧‧Integrated circuit

1 is a schematic diagram of a semiconductor device including a semiconductor pad as an interlayer conductor.

2A, 2B, 2C, 2D, 2E and 2F are a simple side view showing an example of a multi-pass lithography process when the stack is simply arranged.

3A, 3B, 3C, 3D, and 3E are a simplified side view showing an example of an etch depth problem in a lithography process when the stack is not simply arranged.

4A, 4B, 4C, 4D, 4E, 4F and 4G are a simple side view, which is an embodiment of a shear etching process step when the stack is simply arranged.

5A, 5B, 5C, and 5D are a simple side view, which is an embodiment in which the etching etching process steps and the etching depth are generated in a process when the stack is a non-simple arrangement.

Fig. 6 is an example of a contact window structure in which an alternating stack of active layers and insulating layers is a non-simple arrangement.

Figures 7-25 are examples of the formation steps of the contact window structure of Figure 6, which is a multi-pass lithography process.

Figure 7 illustrates a stack of alternating active and insulating layers.

Figure 8 shows the structure of Figure 7 plus the etched shield.

Figure 9 is a diagram showing the structure of Figure 8 after the etching step.

Figure 10 is a diagram showing the structure of Figure 9 after the etch mask is removed.

Figure 11 shows the structure of Figure 10 plus the second layer of etched shield.

Fig. 12 is a view showing the state after the etching step of the structure of Fig. 11.

Figure 13 is a diagram showing the structure of Figure 12 after the second layer of etch mask is removed.

Figure 14 shows the structure of Figure 13 plus the third layer of etched shield.

Figure 15 is a diagram showing the structure of Figure 14 after the etching step.

Figure 16 is a diagram showing the structure of Figure 15 after the third layer of etch mask is removed.

Figure 17 shows the structure of Figure 16 plus the fourth layer of etched shield.

Figure 18 is a diagram showing the structure of Figure 17 after the etching step.

Figure 19 is a diagram showing the structure of Figure 18 after the fourth layer of etch mask is removed.

Figure 20 illustrates the structure of Figure 19 plus a fifth layer of etched shield.

Figure 21 is a diagram showing the structure of Figure 20 after the etching step.

Fig. 22 is a view showing the formation of the through holes in the stack after the fifth layer etching shield is removed from the structure of Fig. 21.

Figure 23 shows the structure of Figure 22 incorporating an insulating layer.

Figure 24 illustrates that the structure of Figure 23 removes a portion of the insulating layer and leaves a sidewall insulating layer in the via.

Figure 25 is a diagram showing the contact window structure as shown in Fig. 6 after the structure of Fig. 24 is added to the interlayer conductor.

Figures 26-43 show an example of a contact window structure formed by a shear etching step.

Figure 26 illustrates a stack of alternating active and insulating layers with a first etch shield disposed thereon.

Figure 27 is a diagram showing the structure of Figure 26 after the etching step.

Figure 28 illustrates the structure of Figure 27 with the first etch mask removed and replaced with a second etch shield.

Figure 29 is a diagram showing the structure of Figure 28 after the etching step.

Figure 30 illustrates the structure of Figure 29 with the second etch shield removed.

Figure 31 shows the structure of Figure 30 plus a third etch shield.

Figure 32 is a diagram showing the structure of Fig. 31 after the etching step.

Figure 33 shows the first trimming of the third etch mask in Figure 32.

Figure 34 is a diagram showing the structure of Fig. 33 after the etching step.

Figure 35 shows the second trimming of the third etch mask in Figure 34.

Figure 36 shows the structure of Figure 35 after the etching step.

Figure 37 illustrates the third etching shield after trimming is removed in Figure 36.

Figure 38 illustrates the structure of Figure 37 after the addition of an insulating/extinction layer.

Fig. 39 is a view showing the structure of Fig. 38 after the addition of an insulating material.

Figure 40 illustrates the structure of Figure 39 plus a fourth etch shield.

Fig. 41 is a view showing the structure of Fig. 40 after the etching step.

Figure 42 is a view showing the structure formed by the through hole after the second etching mask is removed.

Fig. 43 is a view showing the structure in which the interlayer conductor is added to the through hole in Fig. 42.

Figure 44 is a simplified flow diagram showing the steps of forming the contact window structure described in Figures 7-25.

Figure 45 is a simplified flow diagram showing the formation of the contact window structure of Figures 26-43.

Figure 46 is a simplified flow diagram showing the steps of forming the contact window structure of Figures 26-43.

Figure 47 is a simplified block diagram of an integrated circuit.

The following is a detailed description of various embodiments with reference to the accompanying drawings. The following description is intended to be illustrative of specific embodiments and methods, and is not intended to All of the following examples are intended to illustrate the invention and not to limit its scope, which is defined by the scope of the application of this patent. Those skilled in the art having ordinary knowledge will be able to understand various equivalent changes in the following description. Unless otherwise stated, the relationships specified in this application, for example, parallel, aligned, have uniform characteristics, or on the same plane, as a specified relationship, are indicative of limitations in the manufacturing process and variations in production. When the elements are described as being connected, connected, contacted or in contact with one another, they are not necessarily in physical contact with each other unless specifically described. The same elements in the various embodiments are generally given the same reference numerals.

1 is a schematic diagram of a three-dimensional semiconductor device 100 (eg, a memory device), which is described in US Patent Publication No. 2012/0182806, filed on April 1, 2011, entitled Memory Architecture of 3D Array With Alternating Memory String Orientation and String Select Structures. In order to make the active layer behave significantly, many of the insulating materials in the figure are not explicitly depicted, including semiconductor layers and semiconductor pads and other components connected to the interlayer conductors. The three-dimensional semiconductor device 100 is formed on a substrate (not shown) having an insulating layer (not shown). The substrate includes at least one integrated circuit or other structure. Four semiconductor pads 102B, 103B, 104B, and 105B are located at the proximal end of the active layer of the stack, while the other four semiconductor pads 112B, 113B, 114B, and 115B are located at the ends of the active layer of the stack. As shown, the number of corresponding active layers and the number of semiconductor pads can be extended to any number of layers N, N being a number greater than one. As shown, the three-dimensional semiconductor device includes a stack of active layers (eg, 102, 103, 104, and 105) separated by an insulating material between the active layers, such as 102B, 103B, 104B. The active layer strip in the corresponding active layer is separated from 105B). As shown, the semiconductor pads 102B, 103B, 104B, and 105B are electrically coupled to the active layers, and the decoding circuit is coupled to the selected layer within the array. The semiconductor pads 102B, 103B, 104B, and 105B and the active layer can be simultaneously patterned, as long as the vias for the interlayer conductors are exceptional. In the above embodiments, each active layer strip includes a channel section adapted to be fabricated from a semiconductor material. As shown, the active layer strips are ridged along the Y-axis, so the active layer strips 102, 103, 104, and 105 can be configured as the body of the flash memory cell string, and also include the channel sections in the body. In the following example, in a horizontal NAND string configuration, as shown, a layer of memory material 152 is plated with a plurality of layers of active layer strips, and in other examples at least over the sidewalls of the active layer strip. In other embodiments, the active layer strips can be configured as word lines in a vertical NAND string configuration. See U.S. Patent No. 8,363,476, the disclosure of which is incorporated herein by reference.

One end of each active layer stack is a semiconductor pad, and the other end is It is the source line. Therefore, the terminals of the active layer strips 102, 103, 104, 105 are the proximal semiconductor pads 102B, 103B, 104B and 105B and the other end is the source line terminal 119. The source line terminal 119 passes through a gate select line 127, and the active layer strip 112 The terminals of 113, 114 and 115 are remote semiconductor pads 112B, 113B, 114B and 115B and the other proximal end is a source line terminal (for example, source line 128), and the source line terminal passes through a gate selection line. 126.

In the embodiment of FIG. 1, a plurality of conductors 125-1 to 125-N are orthogonally arranged on a stack of a plurality of active layer strips, and the conductors 125-1 to 125-N are formed with the active layer strips. The stack has a conformal surface, a plurality of stacks of conductors are defined between the trenches, and an interface between the plurality of layers is defined between the intersections of the active layer strips 102, 103, 104, 105 side surfaces (interface Region), the arrays are above the stack and conductors 125-1 through 125-N (eg, word line or source select line). Thus, a germanium layer (eg, tungsten telluride, cobalt telluride, titanium telluride or nickel germanide) 154 may be formed on the upper surface of the conductors (eg, word line or source select line).

Depending on the ion implantation procedure, layer 152 made of memory material can include a plurality of dielectric charge storage structures. For example, a plurality of layers of dielectric energy storage structures include a tunneling layer comprising a tantalum oxide material, a charge storage layer made of tantalum nitride, and a barrier layer made of tantalum oxide. In some examples, the tunneling layer in the dielectric energy storage layer can include a first tantalum oxide layer having a thickness of less than 2 nanometers, a tantalum nitride layer having a thickness of less than 3 nanometers, and a thickness of less than 3 nanometers. The second layer of ruthenium oxide. In other ion implantation procedures, layer 152 made of memory material includes only the charge storage layer, and does not include the tunneling layer and the barrier layer.

In other alternatives, anti-fuse materials such as dioxins Plutonium, bismuth oxynitride or other types of cerium oxide, these materials have a thickness rating of between about 1 and 5 nanometers, which is a grade that can be utilized. Other antifuse materials, such as tantalum nitride, are also available materials. In an anti-fuse embodiment, the active layer strips 102, 103, 104, and 105 can be a first conductivity type (eg, p-type) semiconductor material, conductor (eg, word line or source select line) 125-N It can be a second conductivity type (eg, n-type) semiconductor material. When the conductors 125-N are made of a higher doping ratio of n+-type polysilicon, the active layer strips 102, 103, 104, and 105 may be formed using p-type polysilicon. In the anti-fuse embodiment, the width of the active layer must have sufficient space to provide a depletion region to support diode operation. Therefore, the internal memory cell includes a pn junction formed by a programmable antifuse layer. A rectifying circuit between the anode and the cathode, that is, in a three-dimensional array intersection between the polysilicon layer strip and the conductor line.

In other embodiments, different programmable resistive memory materials can also be used as memory materials, including metal oxides such as tungsten oxide or ion doped metal oxides, or other materials, some such materials. A device that is programmed or erased by a variety of voltages or currents can be fabricated, and the operation of storing multiple bytes per memory cell can be achieved.

As can be seen from FIG. 1, the semiconductor pads 102B, 103B, 104B and 105B are disposed in corresponding layers of the device and are connected to the active layer strips on one side, and the semiconductor pads are formed in a continuous patterning manner. In some embodiments, the semiconductor pads in the corresponding layers are connected to the active layer strips on both sides. In other embodiments, the semiconductor pads may be connected to the active layer strips by other materials or structures, which may result in electrical connections to pass voltages or currents required for operation of the device. Moreover, an overlying insulating layer (not shown) and semiconductor pads 102B, 103B, 104B and 105B, except for the lowermost semiconductor pad, include openings 102C1, 102C2, 102C3, 103C1, 103C2 and 104C1, Exposed on the underlying semiconductor pad A plurality of landing zones form a stepped structure.

One way of connecting the interlayer conductors to the active layers in the stack is a multi-pass development etch process, which is disclosed in U.S. Patent No. 8,383,512, the entire disclosure of which is incorporated herein by reference. A similar application method, called a trim-etch process, is disclosed in the inventor's U.S. Patent Application Serial No. 13/735,922, filed on Jan. 7, 2013, entitled Method for Forming Interlayer Conductors To a Stack of Conductor Layers, the disclosure of which is incorporated herein by reference.

2A-2F illustrates a multi-pass development etching process for forming a contact window structure, and FIG. 2A illustrates a stack 200 having alternating active layers 202 and a plurality of insulating layers 204 therein. The uppermost active layer 202.1 is covered with a first etched shield 206. The first etch mask 206 has a plurality of first etch shield openings 208. FIG. 2B illustrates a second etching process of the structure of FIG. 2A, that is, an active layer 202 and an insulating layer 204. The first etching creates a first etching opening 210 in the etch shielding opening 208. After the first etch mask 206 is removed, see FIG. 2C, a second etch mask 212 is formed overlying the stack 200. Referring to FIG. 2D, the second etch mask has a plurality of second etched shield openings 214, one of the etched shield openings 214 being aligned with the first etched opening 208, and the rest is not. Next, as shown in FIG. 2E, the second stage performs a second etching to form a plurality of via holes and extend to the second, third, and fourth active layers 202.2, 202.3 and 204.4 and the first active layer 202.1. The second layer of etch mask is removed after removal, as shown in Figure 2F.

The stack 200 is made of an active layer 202 and an insulating layer 204, each of which has the same etching properties as the insulating layer 204. In this example, the active layer 202 is the same guide Made of electrical materials and of the same thickness. Likewise, the insulating layer 204 is made of the same insulating material and has the same thickness. Therefore, each pair of active layers and the insulating layer have the same etching time in a known etching process, and the configuration in which the active layer and the insulating layer are paired can be regarded as a stacked layer having a simple arrangement.

Figures 3A-3D illustrate a stacked layer that is similar to the 2A-2F diagram without a simple arrangement of stacked layers. In this example, the thickness of the third insulating layer 204.3 is thicker than the insulating layers 204.2 and 204.1 above, and therefore, the etching time of the third insulating layer 204.3 is more than that of the insulating layer 204.1. The first upper boundary active layer 202.1, the first insulating layer 204.1, the second active layer 202.4, and the second insulating layer 204.2 are etched in the second etched shield opening 214.1, and the second etched shield opening 214.2 is opposite to the third insulating layer 204.3. It can be completed completely when etching.

As described herein, the structures provide a non-simple arrangement in which the active layer and/or the insulating layer have different etching times, the active layer and/or the insulating layer are formed of different materials and different etching properties, or even Different thicknesses, or a combination of different materials and different thicknesses between the active layer and/or the insulating layer.

4A-4G illustrate a simplified example of a shear etch process. An etch mask 220 is formed over the uppermost boundary active layer 202.1. The etch mask 220 has an etched shield opening 222 that exposes a portion 224 of the uppermost active layer. As shown in FIG. 4B, the first etching step is: etching through the active layer 202.1 and the insulating layer 204.1 to expose the active layer 202.2 to a portion 226. After a first shearing step, a portion of the etch mask 220 is removed and reveals another portion 228 of the uppermost active layer 202.1. The next etching step, as shown in FIG. 4D, etches through the active layer 202 and an insulating layer 204 to form a portion 230 of the active layer 202.2, and the active layer Part 232 of 202.3 is revealed. After the second shearing step, see Figure 4E, a portion of the etch mask 220 is removed and reveals a portion 234 of the uppermost active layer 202.1. Following another etching step, see FIG. 4F, after a portion of the openings 234, 230, and 232 traverses an active layer and an insulating layer, a structure as shown in FIG. 4F is produced. After the etching shield 220 is removed, the 4G is removed. The figure illustrates a stepped structure 236 having a number of landing zones 238 corresponding to the active layers 202.1-202.4, respectively, thereby connecting the active layer to the interlayer conductor.

An example is shown in Figures 5A-5D, which is similar to that illustrated in Figures 4A-4G. The stacking of the two cases is a non-simple arrangement. In this example, the second insulating layer 204.2 is thicker than the insulating layer above or below. After the etching step as in FIG. 5D, the step may correspond to the 4D drawing, which is sufficient to etch the active layer 202.1. Portion 228 is portion of insulating layer 204.1 located below to expose portion 230 of active layer 232.2. Nonetheless, as seen in Fig. 5D, the etching step can only complete etching of a portion of the insulating layer 204.2 because the thickness of the insulating layer 204.2 is large and a longer etching time is required. Therefore, unlike FIG. 4D, the third active layer 202.3 is not exposed at the second etching step. Nonetheless, the second etching step is continued through the second insulating layer 204.2 until the third active layer 202.3 is exposed, possibly exposing or destroying the exposed portion 230 of the active layer 202.2.

Against the background of the above, FIG. 6 illustrates that a contact window structure 250 is also a non-simple arrangement of alternating stacks of active layers and insulating layers. Contact window structure 250 includes a stack 200 of alternating active layer 202 and insulating layer 204, stacking 200 packages A plurality of sub-stacks 252 are included, the sub-stacks 252 having an upper boundary active layer 202.1. The sub-stacks 252 also have a first layer pair 254 which is formed by alternating the active layer 202 and the insulating layer 204 under each of the upper boundary active layers 202.1. In the embodiment of Figure 6, there are four sub-stacks labeled 252.1 to 252.4, respectively. The first layer pair 254 is alternated between the active layer 202 and the insulating layer 204 and has the same first etch time in a known etch process. Stack 200 also includes sub-stack insulating layers 256, 258, and 260 between sub-stacks 252. In this embodiment, the sub-stack insulating layers 256 and 260 have the same composition, and are also made of cerium oxide SiO2, and the sub-stack insulating layer 258 is made of tantalum nitride SiN. Sub-stack insulation layers 256 and 260 are substantially identical in thickness and composition and thus have substantially the same etch properties. Nonetheless, the thickness of the sub-stack insulating layers 256 and 260 is much greater than the insulating layer 204, so the time required to penetrate the sub-stack insulating layers 256 and 260 is greater than the time required to penetrate the insulating layer 204 in a known etching process. .

The sub-stack insulating layer 256 and the adjacent active layer 202.1 located thereunder form a second layer pair 262 having a second etch time in a known etching process. The sub-stack insulation layer 260 and the adjacent active layer 202.1 located thereunder form a third layer pair 264 having the same second etch time in a known etch process. The sub-stack insulating layer 258 and the adjacent active layer 202.1 located thereunder form a fourth layer pair 266 having a fourth different from the first to third etching times in a known etching process. Etching time. The etching time for the different layer pairs 254, 262, 264 and 266 can be varied from a wide range of the same or different material properties, etching rates or the same/different active and insulating layers. The thickness is determined.

Contact window structure 250 includes an upper insulating layer 268 that is over active layer 202.1 of sub-stack 252.1. The lower insulating layer 270 is located below the active layer 202.4 in the sub-stack 252.4. Both the upper insulating layer 268 and the lower insulating layer 270 are made of hafnium oxide. A set of interlayer conductors 272 extend through upper insulating layer 268 in a stepped manner with each active layer 202 in each sub-stack 252. Each interlayer conductor 272 is surrounded by a sidewall insulation 274 made of tantalum nitride.

Figures 7-25 illustrate an embodiment of a multi-pass lithography process step of the contact window structure 250 of Figure 6, which is discussed in conjunction with Figures 2A-2F.

FIG. 7 illustrates that the stack 200 includes sub-stacks 252.1-252.4 between the upper insulating layer 268 and the lower insulating layer 270, which are separated by sub-stack insulating layers 256, 258, 260. FIG. 8 illustrates that the stack 200 (shown in FIG. 7) is overlaid with a first etch mask 278 having a first etch shield opening 280. FIG. 9 illustrates that the first etched shield opening 280 passes through the insulating layer 268 after etching, and is etched down to the lower boundary active layer 202.1 to form a first etched opening 282. FIG. 10 illustrates the structure after the first etch mask 278 is removed.

11 illustrates that the stack is overlaid with a second etch mask 284 covering half of the first etch opening 282, and the second etch mask 284 has a second etch shield opening 286 and the remaining half of the An etched opening 282 is aligned. In FIG. 12, the second etched shield opening 286 is etched down to the lower boundary active layer 202.1 to form an etch opening 288. Figure 13 shows the first The second etch mask 284 is removed to reveal the first etched opening 282.

14 shows that the stack 200 of FIG. 13 is overlaid with a third etch mask 290 having a third etch shield opening 292.1 exposing half of the second etch opening 282, the third etch mask 290 The third etch shield opening 292.2 covers half of the second etch opening 288. 15 illustrates that in FIG. 14, the stack 200 is etched through the first sub-stack 252.1 and the sub-stack insulating layer 256 via the third etch opening 292.1, and FIG. 15 simultaneously illustrates etching through the third etch opening 292.2. As a result of the third sub-stack 252.3 and the sub-stacked insulating layer 260, the above process forms a third etch opening 294 and a fourth etch opening 296. Figure 16 illustrates the removal of the third etched shield 290.

FIG. 17 illustrates a fourth etch mask 298 having a fourth etch shield opening 299 that exposes all of the first through fourth etch openings 282, 288, 294, and 296. Figure 18 illustrates an etch step in each of the sub-stacks 252.1, 252.2, 252.3, and 252.4, traversing the upper boundary active layer 202.1 and the underlying insulating layer 204.1. This step forms a portion of the etched structure 300 that removes the fourth etched mask 298 as depicted in FIG. The partially etched structure 300 has openings 302 that extend to different levels within the stack 200. Figure 20 illustrates a fifth etch mask 304 covering and exposing the two openings 302. The fifth etch shield has an etch shield opening 306 over the exposed etch opening 302 shown in FIG. Figure 21 illustrates the etched shield opening 306 traversing the two active layers 202 and the two insulating layers 204.

Figure 22 is a schematic view of the second etching shield 304 removed from Figure 21 The through hole 308 extends downward to the landing zone 310 of the active layer 302. The structure of Fig. 22 has a landing zone 310 arranged in a stepped manner. FIG. 23 illustrates an insulating layer 312, such as tantalum nitride, disposed in each via 308 in the structure to form a sidewall insulating 314. In FIG. 24, the insulating layer 312 is over the insulating layer 268, and the insulating layer 312 at the bottom of the vias 308 is removed, so that the landing zone 310 can be exposed. In FIG. 25, the vias 308 are filled with a conductor, such as tungsten W, to produce interlayer conductors 272 extending from the upper insulating layer 268 to the landing zone 310 of each active layer 202. This produces a contact window structure as shown in FIG.

Figures 26-43 illustrate an embodiment of a shear etch process step, and the shear etch process discussed in Figures 4A-4G above is a simplified embodiment herein.

Figure 26 depicts the same stack 330 as stack 200 (Fig. 7), except that the upper insulating layer 268 is missing. A first etch mask 332 is formed over the stack 330, the first etch mask 332 overlying the portion 331 of the active layer 202.1 of the sub-stack 252.1 and revealing approximately half of the active layer. After the first etching step, the result is shown in Fig. 27, via the exposed portion, the sub-stack 252.1, the sub-stack insulation 256, the second sub-stack 252.2, and the sub-stack insulating layer 258 are all partially etched. A portion 334 of the boundary active layer 202.1 above the third sub-stack 252.3 is exposed.

Figure 28 is a diagram showing the structure of Figure 27, which covers a second etch mask 336 which covers and reveals a half of the portion 334 and about half of the portion 331 at the exposed portion 331, etching through Sub-stacking 252.1 and sub-sub The insulating layer 256 is stacked. In the exposed portion 334, the penetration sub-stack 252.3 and the sub-stack insulating layer 260 are etched. This step produces a structure as shown in Fig. 29 having surface areas 338, 340, 342 and 344. In Fig. 30, the second etch mask is removed from the structure shown in Fig. 29.

FIG. 31 illustrates that the third etch mask 346 covers the surface 338-344 and exposes a portion of the surfaces 338-344, and then etches through an active layer 202 and an insulating layer 204 to produce a 32. The structure shown in the figure. The structure has exposed surface areas 348-351. Thereafter, FIG. 33 illustrates that a third etch mask 352 is trimmed to produce a shear etch mask 354 that reveals excess portions of the active layer 202.1 of each sub-stack 252.1-252.4. All of them are another etching step, which penetrates an active layer 202 and an insulating layer 204. The result is shown in Fig. 34. Figure 35 illustrates the shear etch mask 356 produced by the trim etch mask 354 after being trimmed, again exposing an active layer 202 and the underlying insulating layer 204 to an etch process, as shown in Figure 36.

Figure 37 illustrates the result of the removal of the shear etch mask 356 in Figure 36, which shows the landing zone 358 in a stepped arrangement. As shown in Fig. 38, the stepped structure is covered with an insulating layer 360, or a barrier layer 360, which may be made of, for example, tantalum nitride SiN. Next, as shown in Fig. 39, the entire structure is covered by an insulating material 362, which can be made of, for example, cerium oxide. Next, a fourth etch mask 364 has an opening 366 aligned with the landing zone 358 formed over the insulating material 362. After etching, the vias 368 pass through the insulating material 362 and the insulating layer 360 to reach the landing zone 358. This result is shown in Figure 41. Figure 42 illustrates the structure of Figure 41 with the fourth etch mask 364 removed. The 43rd diagram shows the interlayer conductor 272, which may be fabricated from tungsten W, formed in the via 368 and creates a contact structure 370.

Figure 44 is a simplified flow chart showing the steps of the method of forming the contact window structure shown in Figures 7-25. A stack 200 of alternating active layer 202 and insulating layer 204 is formed in step 380. In step 382, a plurality of openings 294, 288 and 296 are etched into the stack, the openings deep into the boundary active layer 202.1. At step 384, the particular openings 294, 288 and 296 are etched deeper to create vias 308. In steps 366 and 388, an insulating layer 314 is formed in vias 308 and openings 294, 288, and 296 that have not been etched. Following the formation of the interlayer conductor 272 in step 390, the interlayer conductor 272 is connected to the landing zone 310 of the active region 202.

Figure 45 is a simplified flow chart showing the basic steps of the method of forming the contact window structure shown in Figures 26-43. At step 392, a stack 330 of alternating active layer 202 and insulating layer 204 is formed. In step 394, stack 330 is etched to expose regions 338, 342, and 344 that are located above boundary active layer 202.1 of sub-stack 252. Regions 338, 342, and 344 may also be referred to as surface regions 338, 342, and 344 at the same time. In step 396, the regions are etched to reveal active layers 202.2, 202.3, and 202.4, the active layers being under the upper boundary active layer 202.1, thereby forming a stepped structure. In step 398, an insulating layer 360 is formed in the stepped structure. In step 400, the insulating layer 360 is covered with an insulating material 362. In step 402, a via hole 368 is formed to penetrate the insulating material 362. And insulating layer 400. In step 404, the interlayer conductor 372 is placed within the via 368 to create a contact structure 370.

Figure 46 is a simplified flow chart showing the basic steps of the method of forming the contact window structure shown in Figures 7-25 and 26-43. In step 410, a stack 220, 380 of alternating active layer 202 and insulating layer 204 is formed, consisting of first, second, third, and fourth sub-stacks 252, each having multiple layers of active layers 202 The active layers are separated by an insulating layer 204. The active layers 202 in each sub-stack include an upper boundary active layer 202.1. In step 412, the first, second, and third sub-stack insulating layers 256, 258, 260 are formed and disposed between the sub-stacks 252. In the first, second, and third sub-stack insulation layers, at least two sub-stack insulation layers and sub-stack insulation layers 204 have different etching times in known etching processes. In step 414, the upper boundary active layer 202.1 is turned "on", and then the other active layers 202.2-202.4 are turned "on" in step 416 to form a stepped structure as shown in Figures 22 and 42. At step 418, the interlayer conductors 272 are formed and extend to the landing zones 310, 318. The interlayer conductors are separated by an insulating material.

Figure 47 is a simplified block diagram of an integrated circuit 975 comprising a three-dimensional NAND flash memory array 960 having the structure shown in Figure 1, for example, on a semiconductor substrate. A high density, narrow linewidth global word line, a row decoder 961 is coupled to a plurality of word lines and arranged in the course direction of the memory array 960. A row decoder 963 is connected to a plurality of SSL lines 964 and arranged in a straight direction for reading and programming. The data is derived from the memory cells within the memory array 960 within the stack. A plane decoder 958 is coupled to a plurality of planes within memory array 960 by word line 959. The address is supplied by bus 965 and coupled to row decoder 965, column decoder 961 and plane decoder 958. A sense amplifier and data input structure located in block 966 is coupled to row decoder 963. In this example, through the bus 967, the data is supplied through a data-in line 971 which is supplied from the input/output port on the integrated circuit 971 or through other internals located on the integrated circuit 975. / External data source to supply, to the data entry structure located in block 966. In the above embodiment, another line 974 is included in the integrated circuit 975 for use as a general purpose processor or a special purpose application processing circuit, or a collection of modules to provide a NAND flash memory. System single chip supported by the array. The data is transmitted to the input/output port through a data-out line 972 on the sense amplifier, or other data destinations located inside/outside of the integrated circuit 975.

Implemented by a control unit, in this example, a bias arrangement state machine 969 is used to generate or supply a voltage through a voltage supply or power supply located in region 968 to control the bias voltage setting. Application, such as reading, erasing, stylizing or clearing the voltage required for verification and stylization verification. With known prior art techniques, the control unit can be implemented by a special purpose logic loop. In other embodiments, the control unit includes a general purpose processor that may be implemented in the same integrated circuit for executing a controlled computer program. In another embodiment, a special purpose logic loop is combined with a general purpose processor Used for the implementation of the control unit.

In many embodiments, a three-dimensional array device, such as a memory device, includes a plurality of patterned semiconductor materials, each patterned layer including a plurality of parallel lines formed of a semiconductor material, the parallel One end of the wire is connected to the first side of a semiconductor pad, and the semiconductor pads are connected to a plurality of patterned layers disposed in a stack, each of the semiconductor pads including a landing zone connecting the interlayer conductors, the interlayer conductors are connected The overlying inter-connect conductors are arranged to be aligned along the parallel lines of the semiconductor material. Viewed from above, the interlayer conductors are arranged in the course direction and are located in a via structure covered by an insulating layer, each column being aligned along the X direction and parallel to the first side. In other embodiments, the interlayer conductor may be partially offset in the Y direction, which is perpendicular to the X direction. In other embodiments, the landing zones may be formed in a plurality of stepped arrangements, as depicted in Figures 6 and 43.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

200‧‧‧Stacking

202.1‧‧‧ active layer

204.1‧‧‧Insulation

202.4‧‧‧Second active layer

204.3‧‧‧The third insulation layer

252.1‧‧‧First sub-stacking

252.2‧‧‧Second sub-stacking

252.3‧‧‧ Third sub-stacking

252.4‧‧‧ Fourth sub-stacking

254‧‧‧ layer pairs

262‧‧‧Second layer

264‧‧‧ third layer pair

266‧‧‧Fourth pair

256, 258, 260‧ ‧ sub-stack insulation

268‧‧‧Upper insulation

270‧‧‧lower insulation

272‧‧‧Interlayer conductor

314‧‧‧ sidewall insulation

Claims (20)

A method for forming a stepped contact window structure includes: forming a stack consisting of a plurality of active layers and a plurality of insulating layers, comprising: forming a first sub-stack comprising N active layers, wherein the N active layers are Separating the insulating layers, the N active layers include an upper boundary active layer; forming a second sub-stack on the first sub-stack, the second sub-stack comprising M active layers, the M active layers being Separating the insulating layers, the M active layers include an upper boundary active layer; and forming a first sub-stack insulating layer between the first sub-stack layer and the second sub-stack layer, in a known etching step The first sub-stack insulation layer has an etching time different from a plurality of etching times of the insulating layers in the second sub-stack; turning on the upper boundary active layers; and connecting the upper boundary active layers Step: turning on the first sub-stack and the remaining active layers of the second sub-stack, and generating a plurality of landing areas of the stepped structure on the active layers of the first sub-stack and the second sub-stack (landing area); and forming an extension A plurality of conductor layers between the plurality of landing zone, between the plurality of conductive layers are each separated by an insulating material. The method of forming the method of claim 1, wherein the stacking step comprises: forming a stack comprising a first sub-stack, a second sub-stack, a third sub-stack, and a fourth sub-stack; forming a second sub- Stacking an insulating layer on the second sub-stack and the third sub-stack And forming a third sub-stack insulation layer between the third sub-stack and the fourth sub-stack. The method of forming of claim 2, wherein each of the first, second, third, and fourth sub-stacks comprises the same number of active layers. The method of forming the third aspect of the invention, wherein the insulating layers of the first, second, third, and fourth sub-stacks have substantially the same thickness and are made of a first insulating material. The first, second, and third sub-stack insulation layers are respectively made of a second insulating material, a third insulating material, and a fourth insulating material; and the second, third, and fourth insulating materials are formed At least two of them are different insulating materials and have different etching properties. The forming method of claim 3, wherein the insulating layers in each of the first, second, third, and fourth sub-stacks are substantially the same in a known etching process. Etching time; and in the known etching process, in each of the first, second, and third sub-stack insulating layers, different from the first, second, third, and fourth sub-stacks Etching time of some insulating layers. The method of forming of claim 5, wherein the first and third sub-stack insulating layers have substantially the same etching time in the known etching process. The method of forming the method of claim 1, wherein the step of turning on the upper boundary active layer comprises: selecting one of the upper boundary active layers of one of the sub-stack layers in one or more etching steps An area and revealing the area; and the remaining steps of the active layers include: Performing an etching step on the exposed regions of the upper boundary active layer to expose a plurality of active layers under the active layer of the upper boundary layer of the selected sub-stack layer; using a material to cover the exposed portions An active layer, comprising: covering the upper boundary active layers; and etching the material into holes such that the active layers of the selected sub-stack layer are exposed. The method of forming the method of claim 7, wherein: in the one or more etching steps, the exposed regions of the upper boundary active layer generate the regions of a stepped structure; and the execution is revealed The etching steps of the regions are performed to create a stepped structure of interlayer conductor contact window regions on the active layers. A method for forming a contact window structure includes: forming a stack consisting of a plurality of active layers and a plurality of insulating layers, the stack comprising a plurality of sub-stacks having an active layer of an upper boundary, the sub-stack having an insulating layer and a plurality of active layers The pair of layers below the active layer of the upper boundary, the insulating layer and the pair of active layers form a plurality of first layer pairs, the first layer pairs having a plurality of uniformities in the known etching process a first sub-stack etch time, the stack also includes a plurality of second layer pairs, the second layer pairs including a plurality of sub-stack insulating layers, the sub-stack insulating layers being located between the sub-stacks, the second layer There are a plurality of second sub-stack etch times in the known etch process, which are different from the first sub-stack etch times; in one or more etch steps, the etch is performed to cause the stack to generate a plurality of openings, Etching depths of the openings terminate at the upper boundary active layers; the openings are selected to form a plurality of vias, the vias exposing a plurality of active layers in each of the sub-stacks; Forming a plurality of interlayer conductors, wherein the interlayer conductors extend to the active layers; and the interlayer conductors extend to the upper boundary active layers during the deep etching of the openings . The forming method of claim 9, wherein the stack forming step comprises forming a stack comprising the first sub-stack, the second sub-stack, and the third sub-stack. The method of forming of claim 10, wherein each of the first, second, and third sub-stacks comprises the same number of the plurality of first layer pairs. The forming method of claim 10, wherein the insulating layers in the first, second and third sub-stacks are made of a first insulating material; in the first and second sub- The sub-stack insulation layer between the stacks is made of a second insulating material; and the sub-stack insulation layer between the second and third sub-stacks is made of a third insulating material; At least two of the first, second and third insulating materials are different materials and have different etching properties. The method of forming of claim 9, wherein each sub-stack comprises at least three sets of first layer pairs. The method of forming the method of claim 9, further comprising: forming a sidewall insulating layer in the via holes; and forming sidewall insulating layers in the openings during the deep etching of the openings . The method of forming the method of claim 14, wherein the vias are formed in the vias and the openings that are not deeply etched. The steps of the body are performed substantially simultaneously. A stepped contact window structure comprising: a stack of alternating active layers and a plurality of insulating layers, the stack being a non-simple arrangement; a plurality of landing zones of a stepped structure on the active layers; a plurality of interlayer conductors extending to the landing areas, the interlayer conductors being separated by an insulating material, wherein the stack of the active layers and the insulating layers comprises: a first sub-stack comprising N active layers The active layers are separated by a plurality of insulating layers, the N active layers including an upper boundary active layer; a second sub-stack being located above the first sub-stack, the second sub-stack comprising M active layers, the M The active layers are separated by a plurality of insulating layers, the M active layers including an upper boundary active layer; and a first sub-stack insulating layer between the first and second sub-stacks, the first sub-stack insulating layer is In a known etching step, there is an etching time different from the plurality of etching times of the insulating layers in the second sub-stack. The stepped contact window structure of claim 16, wherein the stack comprises: a third and fourth sub-stack; a second sub-stack insulating layer is located between the second and third sub-stacks; a third sub-stack insulating layer is positioned between the third and fourth sub-stacks; and the insulating layers in the first, second, third, and fourth sub-stacks have substantially the same thickness and a first insulating material; the first, second and third sub-stack insulating layers are made of a second insulating material, a third insulating material and a fourth insulating material; At least two of the first, second, third, and fourth insulating materials are different materials and have different etching properties. The stepped contact window structure of claim 17, wherein the insulating layers in the first, second, third and fourth sub-stacks are substantially identical in a known etching process Etching time; and in the known etching process, each of the first, second, and third sub-stack insulating layers is different from the insulating layers in the first, second, third, and fourth sub-stacks The etching time of the layer. The stepped contact window structure of claim 18, wherein the etching time of the first and third sub-stack insulating layers in the known etching process is substantially the same. The stepped contact window structure according to claim 16, wherein (1) the etching time between the active layers is different, or (2) the etching time between the insulating layers is different, at least one of After the same etching process.