TWI490862B - Memory architecture of 3d array with improved uniformity of bit line capacitances - Google Patents

Description

Improved bit line capacitance singleness 3D array memory structure

The present invention is a high density memory device, and more particularly a memory device in which multiple planes of a plurality of memory cells are used to provide a 3D array.

As device critical dimensions in integrated circuits shrink to the limits of general memory cell technology, designers have been looking for techniques to stack multiple memory cell planes to achieve greater storage capacity and lower bit unit cost. For example, Lai et al., "Multi-Layer Stackable Thin Film NAND Flash Memory", "A Multi-Layer Stackable Thin", December 11-13, 2006, at the International Electron Devices Conference of the Electrical and Electronics Engineering Society. -Film Transistor (TFT) NAND-Type Flash Memory, "IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006); and Jung et al., December 11-13, 2006, at the Electrical and Electronics Engineering Society International "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal", "Electrical Devices Conference, "3D Stacked NAND Flash Memory Technology for Stacking Single Crystal Layers on ILD and TANOS Structures at Nodes Beyond 30 nm" Si Layers on ILD and TANOS Structure for Beyond 30 nm Node", IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006), applying thin film transistor technology to charge trapping memory technology.

And, in November 2003, Johnson et al., 512-3D with a 3D diode/anti-fuse memory cell array, published in the No. 11 of the Journal of the Solid State Circuits, Electrical and Electronic Engineering Society, November. Mb PROM" ("512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory Cells" IEEE J. of Solid-State Circuits, vol. 38, no. 11, Nov. 2003), has been the intersection Array technology is applied to anti-fuse memory. In the design described by Johnson et al., a plurality of layers of word lines and bit lines are provided that have memory elements at the intersections. The memory component includes a P+ type polycrystalline germanium anode connected to the word line and an N-type polycrystalline germanium cathode connected to the bit line, wherein the anode and the cathode are separated by an antifuse material.

In the process described by Lai et al, Jung et al. and Johnson et al., there are several critical lithography steps for each memory layer. Therefore, the number of critical lithographic steps required to fabricate the device is directly proportional to the number of layers implemented. Therefore, although the use of 3D arrays can achieve higher density benefits, higher manufacturing costs limit the use of the technology.

Another structure for providing vertical NAND cells in charge trapping memory technology is described in Tanaka et al., June 12-14, 2007, on the 14th-15th of the 2007 VLSI Technical Digest Symposium Technical Paper. "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory", 2007 Symposium on VLSI Technology Digest of Technical Papers; 12- 14 June 2007, pages: 14-15). The structure described by Tanaka et al. includes a multi-gate field-effect transistor structure with a vertical channel that operates like a NAND gate, using a silicon-oxide-nitride-oxide-silicon (SONOS) charge design. Technology is used to create storage locations in each gate/vertical channel interface. The memory structure is a semiconductor material disposed on a column, such as a vertical channel, for multiple gate cells, wherein the lower select gate is adjacent to the substrate and the upper select gate is on the top. A plurality of horizontal control gates are formed using a planar electrode layer that intersects the pillars. The planar electrode layer used as a control gate does not require critical lithography, thus saving costs. However, many critical lithographic steps are still required for each vertical unit. Moreover, the number of control gates stacked in layers can be limited by such methods, depending, for example, on the conductivity of the vertical channels and the programming and erase procedures used.

3D Finger VG (vertical gate) NAND is a high density 3D stackable NAND flash architecture. However, the structure is asymmetrical for different locations of the array, such as different planar locations of the array. Bit lines respectively coupled to the same planar position of different blocks in the array have different bit line capacitances (CBL). The different bit line capacitances of these different bit lines create difficulties in sensing the values stored in the memory cells.

Therefore, the provided 3D integrated circuit memory structure preferably has a low manufacturing cost, and includes reliable and very small memory components, and an improved process window, wherein the process window refers to and has A process window in which adjacent stacks of memory cell strings of a gate structure are combined.

Various embodiments provide a 3D memory array such as 3D Finger VG (vertical gate NAND).

Various embodiments convert the bit lines to sequences of different layers in the 3D memory array for transformation. For example, in a configuration in which a bit line runs through a plurality of distinct memory blocks, the bit lines have different sequences in different memory blocks that couple the bit lines to the 3D memory array. The different layers (of coupling to the different layers of the 3D memory array are modified?). Because different plane positions in the array have different capacitances, and in the configuration of bit lines running through multiple different memory blocks, the difference in capacitance between different layers in a single block will traverse different regions. The blocks are summed up in turn, so the bit lines of the same planar position of different blocks in each coupled array will have bit line capacitances (CBL) that are different from the other bit lines. Different sequences couple different plane positions of different blocks to bit lines, and the different sequences traverse different blocks to average the difference between capacitances that vary with different planar positions. Such an average ensures that the bit line capacitances of the different bit lines are uniform, facilitating the sensing of the values from the bit lines for storage in the memory cells. In contrast, in an embodiment, each bit line (eg, like a metal bit line located in metal layer 3) has an average capacitance (CBL) that is consistent with other bit lines.

According to a first aspect of the invention, a memory device includes a substrate, a plurality of semiconductor material strip stacks, a plurality of word lines, a plurality of memory elements, and a plurality of bit line structures.

The strips of semiconductor material are stacked on top of the substrate. The strips of semiconductor material are ridged and comprise at least two strips of semiconductor material separated by an insulating material in a plurality of planar locations.

The word lines are disposed across the stacks and have a conformal surface with the stacks.

The memory device located in the interface region establishes a 3D array of memory cells through the strips of semiconductor material and the word lines.

The bit line structures are located at the ends of the stacks, and the bit line structures are coupled to the plurality of bit lines.

Each of the bit lines of the bit lines is coupled to at least two different planar positions of the planar positions.

In one embodiment, each of the bit lines is coupled to at least two different planar positions of the different stacks of the semiconductor material strip stacks. The at least two-phase different planar position includes a first planar position of a first semiconductor strip stack and a second planar position of a second semiconductor strip stack such that the first semiconductor strip stack and the second semiconductor strip stack It is a block of different memory.

In one embodiment, each of the bit lines is coupled to at least two different planar positions of the different stacks of the semiconductor material strip stacks. The at least two-phase different planar position includes a first planar position of a first semiconductor strip stack and a second planar position of a second semiconductor strip stack such that the first semiconductor strip stack and the second semiconductor strip stack are Accessed by distinct group of character lines of the word lines.

In one embodiment, the memory cells are disposed along the strips of semiconductor material in the NAND string.

In one embodiment, the memory cells are disposed along the bit line structures and the plurality of semiconductor material strips between the plurality of source line structures.

In one embodiment, the distinct capacitances characterize the different planar positions of the planar locations.

In one embodiment, the stacks are separated into a plurality of memory blocks by the bit line structures.

In one embodiment, the semiconductor material strips are stacked with a particular semiconductor strip and a combination of a particular word line of the word lines to identify a particular memory cell of the memory cell 3D array.

In one embodiment, the memory devices comprise charge-trapping structures, the charge trapping structures comprising a tunneling layer, a charge trapping layer, and a barrier layer ( Blocking layer).

In another aspect of the invention, a memory device includes a substrate, a plurality of semiconductor material strip stacks, a plurality of word lines, a plurality of memory elements, and a plurality of bit line structures.

The strips of semiconductor material are stacked on top of the substrate. The stacks are ridged and include at least two strips of semiconductor material separated by an insulating material in a plurality of planar locations.

The word lines are disposed across the stacks and have planes that are conformal to the stacks.

The memory device located in the interface areas establishes a 3D array of memory cells through the strips of semiconductor material and the word lines.

The bit line structures are located at the ends of the stacks. The bit line structures couple the planar locations to a plurality of bit lines. The bit line structures have at least two distinct sequences of the plurality of sequences of the planar positions. Each of the sequences depicts sequential features of the bit line structures of the bit line structures coupled to the planar locations of the bit lines.

In one embodiment, the memory cells are disposed along the strips of semiconductor material in the NAND string.

In one embodiment, the memory cells are disposed along the strips of semiconductor material between the bit line structures and the plurality of source lines.

In one embodiment, the distinct capacitances characterize the different planar positions of the planar locations.

In an embodiment, the different sequences of the sequences of the bit line structures average the phases of the dissimilar planar position features of the planar positions coupled to the bit lines. Different capacitance.

In one embodiment, the order in which the bit line structure is coupled to the planar positions of the bit lines is from one of the first ends of the bit line structure to one of the bit line structures. The second end.

In an embodiment, the stacks are separated into a plurality of memory blocks by the bit structures.

In one embodiment, the semiconductor material strips are stacked with a particular semiconductor strip and a combination of a particular word line of the word lines to identify a particular memory cell of the memory cell 3D array.

In one embodiment, the memory devices include a charge trapping structure, the charge trapping structures including a tunneling layer, a charge trapping layer, and a barrier layer.

According to an aspect of the invention, a memory device includes: a 3D integrated circuit memory array having a plurality of memory cells at a plurality of planar positions; and a plurality of bit line structures having a plurality of planes a plurality of sequences of positions, the sequences comprising at least two distinct sequences, each of the sequences depicting a bit line structure of the bit line structures coupled to the planar positions of the plurality of bit lines Sequential features.

In one embodiment, the memory cells of the array are disposed along the strips of semiconductor material in a NAND string.

In one embodiment, the memory cells of the array are disposed along the plurality of semiconductor material strips between the bit line structures and the plurality of source lines.

In one embodiment, the distinct capacitances characterize the distinct planar locations of the planar locations.

In an embodiment, the different sequences of the sequences of the bit line structures average the different capacitances depicting the different planar position features of the planar positions.

In one embodiment, the order in which the bit line structure is coupled to the planar positions of the bit lines is from one of the first ends of the bit line structure to one of the bit line structures. The second end.

In one embodiment, the array is separated into a plurality of memory blocks by the bit structures.

In one embodiment, a combination of one of the plurality of semiconductor material strips in the array and a particular one of the plurality of word lines in the array is selected to identify a particular one of the arrays. Memory unit.

In one embodiment, the memory elements of the array comprise a charge trapping structure, the charge trapping structures comprising a tunneling layer, a charge trapping layer, and a barrier layer.

According to an aspect of the invention, a memory device includes: a 3D integrated circuit memory array having a plurality of memory cells in a plurality of planar positions; a plurality of bit lines, each of the bits The line system is coupled to at least two different planar positions of the different planar positions, and the memory units are accessed at the at least two different planar positions.

In one embodiment, the memory cells of the array are disposed along the strips of semiconductor material in a NAND string.

In one embodiment, the memory cells of the array are disposed along the plurality of semiconductor material strips between the bit line structures and the plurality of source lines.

In one embodiment, the distinct capacitances characterize the distinct planar locations of the planar locations.

In one embodiment, the array is separated into a plurality of memory blocks by a plurality of bit line structures.

In one embodiment, a combination of one of the plurality of semiconductor material strips in the array and a particular one of the plurality of word lines in the array is selected to identify a particular one of the arrays. Memory unit.

In one embodiment, the memory elements of the array comprise a charge trapping structure, the charge trapping structures comprising a tunneling layer, a charge trapping layer, and a barrier layer.

Various embodiments have multiple stacked layer numbers. For example, for an eight-layer vertical gate, the sequence of bit lines (BL) coupled to different layers of the memory block is sequenced BL(1), BL(2), BL(3), BL. (4), BL(5), BL(6), BL(7), BL(8) can be transformed in different blocks such that the bit line capacitance of each bit line is averaged. This minimizes the difference in capacitance of each metal bit line to achieve a stable sensing margin.

With regard to other aspects of the invention and its advantages, reference is made to the following figures, embodiments, and patent applications.

A detailed description of embodiments with reference to the accompanying drawings will be provided below.

1 is a perspective view of a portion of a 3D programmable resistive memory array 2x2 in which fill material is removed from the pattern to display a stack of semiconductor strips and vertical word lines that make up the 3D array. In this illustration, only two planes are shown. However, the number of planes can be extended to very large. As shown in FIG. 1, a memory array is fabricated on an integrated circuit substrate having an insulating layer 10, which is based on a semiconductor or other structure (not shown). The memory array includes a plurality of stacks separating the semiconductor strips 11, 12, 13, and 14 with insulating materials 21, 22, 23, and 24. The stacks are ridges extending from the Y-axis, as shown, such that the semiconductor strips 11-14 can be configured as a series of memory cells. The semiconductor strips 11 and 13 can be used as a memory cell string in the first memory plane. Semiconductor strips 12 and 14 can be used as a string of memory cells in the second memory plane. The memory material layer 15, for example, is an anti-fuse material, in this case the anti-fuse material is applied to a plurality of semiconductor strip stacks, and in other examples at least to the sidewalls of the semiconductor strip. A plurality of word line lines 16 and 17 are vertically disposed across a plurality of semiconductor strip stacks. The word lines 16 and 17 have a surface conformal to the plurality of semiconductor strip stacks, filling the trenches formed by the edges of the plurality of stacks (ie, 20 in the figure), and placing the semiconductor strips 11-14 on the stack A multilayer array of side regions and interface regions of intersections between the sides of word lines 16 and 17 are formed. Layers of Tellurides 18 and 19 (i.e., tungsten telluride, cobalt telluride, titanium telluride) may be formed on the top surfaces of word lines 16 and 17.

The memory material layer 15 may be comprised of an antifuse material, such as cerium oxide, cerium oxynitride or other cerium oxide; for example, the memory material layer 15 has a thickness of about 1 to 5 nanometers. Other antifuse materials, such as tantalum nitride, may also be used for the memory material layer 15. The semiconductor strips 11-14 may be semiconductor materials of a first conductivity type (ie, P-type). Word lines 16 and 17 can be semiconductor materials of the second conductivity type (i.e., N-type). For example, the semiconductor strips 11-14 can be fabricated using P-type polysilicon, whereas the word lines 16 and 17 can be fabricated using the corresponding heavily doped n+-type polysilicon. The width of the semiconductor strip should provide sufficient space in the depletion region to support diode operation. Thus, a memory cell comprising a rectifier formed with a programmable anti-fuse layer P-N junction is formed in a 3D array of intersections between polysilicon ribbons and lines. The programmable anti-fuse layer is between the anode and the cathode. (This is an English sentence structure, which is not suitable for Chinese writing.) In other embodiments, different programmable resistive memory materials can be used, including tungsten oxide on tungsten or doped metal oxide semiconductor strips. Transition metal oxide. These materials can be programmed and erased and can be implemented in jobs that store multiple bits per cell.

2 shows a cross-sectional view taken from the X-Z plane of the memory cell formed in the intersection of the word line 16 and the semiconductor strip 14. Active regions 25 and 26 are formed on two sides between word line 16 and strip 14. In the natural state, the antifuse material layer 15 has a high electrical resistance. After programming, the antifuse material decomposes, causing either or both of the active regions 25 and 26 in the antifuse material to exhibit a low resistance state. In the embodiment described herein, each memory cell has two active layers 25 and 26, each located at each edge of the semiconductor strip 14. 3 shows a cross-sectional view of the memory cell formed in the intersection of the word line 16 and the semiconductor strip 14 in an X-Y plane. 3 also illustrates the current path from the word line labeled as word line 16 through the antifuse material layer 15 to the semiconductor strip 14.

The electron flow, as shown by the solid arrow in FIG. 3, flows from the N+ type word line 16 into the P-type semiconductor strip, and then flows along the semiconductor strip (--arrow) to a sense amplifier, where the electron current can It is measured to indicate the state of the selected memory unit. In a typical embodiment where a layer of about 1 nm thick ruthenium dioxide is used as an antifuse material (the adjective is too long, so that it is very hard to be alone; try to treat the complement of the subject as a sentence), The programming pulse is applied under the control of a control circuit on a wafer. Wherein the programming pulse can include a 5 to 7 volt pulse having a pulse width of about 1 millisecond, and the on-wafer control circuit is described below with reference to the portion of FIG. The read pulse is applied under the control of a control circuit on a wafer. Wherein the read pulse can comprise a pulse of 1 to 2 volts, as the pulse width depends on its configuration. The on-wafer control circuit is described below with reference to the portion of Fig. 18. The read pulse may be much shorter than the programming pulse.

Fig. 4 is a schematic diagram showing a 2-plane of a memory unit, each having 6 cells. The memory cell is represented by a diode symbol with a dashed line representing the layer of antifuse material between the anode and the cathode. The intersection of the word lines 60 and 61 with the first stack of semiconductor strips 51 and 52, the second stack of semiconductor strips 53, 54 and the third stack of semiconductor strips 55 and 56 shape the two planar memory cells, The word lines 60 and 61 are used as the first word line (WL) WLn and the second word line WLn+1, and the first to third stacks are in the first layer and the second layer array. The memory cells are serially n, n+1, and n+2. The first plane of the memory cell includes memory cells 30 and 31 on semiconductor strip 52, memory cells 32 and 33 on semiconductor strip 54, and memory cells 34 and 35 on semiconductor strip 56. The second plane of the memory cell includes memory cells 40 and 41 on the semiconductor strip 51, memory cells 42 and 43 on the semiconductor strip 53, and memory cells 44 and 45 on the semiconductor strip 55. As shown, the word line 60, which is the word line WLn, includes vertical extensions 60-1, 60-2, and 60-3, which are located between the stacks and are located in the trench 20 as shown in FIG. The extensions are for coupling the word lines 60 along the three strips of material in the illustrated plane to the memory unit. Arrays with many layers can be implemented as described herein, making very high density memory methods possible, or reaching terabits per chip.

Figure 5 is a perspective view of a portion of a 3D charge trap memory array 2x2 in which the fill material is removed from the pattern to enable display of the semiconductor strip stack and vertical word lines that make up the 3D array. In this illustration, only two layers are shown. However, the number of layers can be extended to very large. As shown in FIG. 5, the memory array is fabricated on an integrated circuit substrate having an insulating layer 110 based on a semiconductor or other structure (not shown). The memory array includes a plurality of stacks separating the semiconductor strips 111, 112, 113, and 114 with insulating materials 121, 122, 123, and 124. The stacks are ridges extending over the Y-axis, as shown, such that the semiconductor strips 111-114 can be configured as a series of memory cells. The semiconductor strips 111 and 113 can be used as a memory cell string in the first memory plane. Semiconductor strips 112 and 114 can be used as a string of memory cells in a second memory plane.

The insulating layer 121 interposed between the semiconductor strips 111 and 112 in the first stack and the insulating layer 123 interposed between the semiconductor strips 113 and 114 in the second stack have an effective oxide thickness of about 40 nm or more (effective oxide Thickness, EOT), wherein the effective oxide thickness is the thickness of the insulating material normalized according to the ratio of the dielectric constant of the cerium oxide and the dielectric constant of the selected insulating material. The term "about 40 nm" used in this case is intended to estimate a possible change of about 10%, as is conventionally produced for this type of structure. The thickness of the insulating material can play a key role in reducing interference between adjacent layer units of the structure. In some embodiments, the effective oxide thickness of the insulating material can be as small as 30 nanometers while allowing sufficient isolation between the layers.

The memory material layer 115, such as a dielectric charge trapping structure, is coated on a plurality of semiconductor strip stacks in this embodiment. A plurality of word line lines 116 and 117 are vertically disposed across a plurality of semiconductor strip stacks. The word lines 116 and 117 have surfaces conformal to the plurality of semiconductor strip stacks, filling the trenches formed by the plurality of stacks (i.e., 120 in the figure) and causing the sides of the semiconductor strips 111-114 on the stack And a multilayer array of interface regions at the intersections between the sides of word lines 116 and 117. Layers of Tellurides 118 and 119 (i.e., tungsten telluride, cobalt telluride, titanium telluride) may be formed on the top surfaces of word lines 116 and 117.

The metal-oxide-semiconductor field effect transistor (MOSFET) unit can also be arranged in such a manner that the nanowire is provided in the channel region on the word line 111-114. Or the structure of the nanotubes, as Paul and others published in September 2007 in the Journal of Electrical and Electronic Engineering, Electronic Devices, Vol.54, No. 9, "Impact of Process Variations on the Performance of Nanowires and Nanotubes" ("Impact of a Process Variation on Nanowire and Nanotube Device Performance", IEEE Transactions on Electron Devices, Vol. 54, No. 9, September 2007), which is incorporated herein by reference. (which article is incorporated by reference as if fully set forth herein). (This is an incorporated by reference, an American manual that describes how to write a pre-case content. It is recommended to translate the Chinese translation of google "incorporate by reference" and then use the original by reference. Mark it out, it will be very clear.)

Thus, a 3D array of silicon-oxide-nitride-oxide-silicon (SONOS) type memory cells arranged in a NAND flash array can be fabricated. A source, a drain, and a channel are formed in the germanium semiconductor strips 111-114. The memory material layer 115 includes a tunneling dielectric layer 97 formed of hafnium oxide, which may be formed of tantalum nitride. The charge storage layer 98, the blocking dielectric layer 99 formed of cerium oxide, and the gate of the polysilicon including the word lines 116 and 117.

The semiconductor strips 111-114 can be P-type semiconductor materials. The word lines 116 and 117 can be semiconductor materials having the same or different conductivity types (i.e., P+ type). For example, the semiconductor strips 111-114 can be fabricated using P-type polycrystalline germanium or P-type epitaxial single crystal germanium, whereas the word lines 116 and 117 can be fabricated using corresponding heavily doped P+-type polycrystalline germanium.

Additionally, the semiconductor strips 111-114 can be N-type semiconductor materials. The word lines 116 and 117 can be semiconductor materials having the same or different conductivity types (i.e., P+ type). Such an N-type band arrangement can achieve a buried-channel and depletion mode charge trap memory unit. For example, the semiconductor strips 111-114 can be fabricated using N-type polycrystalline or N-type epitaxial single crystal silicon, whereas the word lines 116 and 117 can be used with corresponding heavily doped P+. Polycrystalline germanium is manufactured. A typical N-type semiconductor strip doping concentration may be in the vicinity of 10 ¹⁸ /cm ³ , and in the range of about 10 ¹⁷ /cm ³ to 10 ¹⁹ /cm ³ in the available embodiment. The use of N-type semiconductor strips is particularly advantageous in junction-free embodiments to promote conductivity along the NAND string and to allow for higher read currents.

Thus, a memory cell including a field effect transistor having a charge storage structure is formed in a 3D array of intersections. A semiconductor strip and word line of about 25 nm width are used, and the gap between the ridges is about 25 nm, and a device having tens of layers (ie, 32 layers) can reach 10,000 in a single wafer. The capacity of billions of dollars.

The memory material layer 115 can include other charge storage structures. For example, a band gap engineered SONOS (BE-SONOS) charge storage structure can be used, which includes a dielectric tunneling layer 97 that includes an inverted "U" under zero bias. A composite of materials of a valence band. In an embodiment, the synthetic tunneling dielectric layer includes a first layer called a hole tunneling layer, a second layer called a band offset layer, and an isolation layer ( The third layer of the isolation layer). The hole tunneling layer of layer 115 in this embodiment includes ruthenium dioxide on the side of the semiconductor strip, which is formed, for example, by using an in-situ steam generation (ISSG) with a selective nitride. It can also be used in the surrounding environment to deposit post-deposited NO anneal or increase the use of nitric oxide. The thickness of the first layer of cerium oxide is less than 20 And more preferably less than or equal to 15 . A representative embodiment may have a thickness of 10 Or 12 .

The tape offset layer in this embodiment includes tantalum nitride which is laid flat on the tunnel tunneling layer, and is formed by, for example, low-pressure chemical vapor deposition (LPCVD), for example, The dichlorosilane (DCS) and the ammonia (NH ₃ ) precursor were used at a temperature of 680 °C. In an alternative process, the belt offset layer comprises niobium oxynitride produced using a similar process with a nitrous oxide precursor. The thickness of the tantalum nitride tape offset layer is less than 30 Or, preferably, less than or equal to 25 .

The spacer layer in this embodiment includes germanium dioxide which is placed flat on a tantalum nitride tape offset layer formed, for example, by LPCVD high temperature oxide (HTO) deposition. The thickness of the ceria barrier layer is less than 35 Or, preferably, less than or equal to 25 . Such a three-layer tunneling layer can achieve an inverted U-shaped band energy level.

If the first position of the valence band energy level enables the electric field to induce hole tunneling in a thin region between the interface with the semiconductor body and the first position, the valence band energy level is sufficient to be after the first position The valence band energy level is raised to effectively eliminate the level of the hole tunneling barrier in the synthetic tunneling dielectric after the first position. Such a structure establishes an inverted U-shaped valence band energy level in the three-layer tunneling dielectric layer, and enables electric field assisted hole tunneling at high speed, and at the same time effectively without an electric field or When a small electric field is induced for the purpose of other operations, such as when reading data from a cell or programming an adjacent cell, leakage of charge is prevented by synthesizing the tunneling dielectric.

In a representative device, the memory material layer 115 includes an energy gap design synthetic tunneling dielectric layer including a germanium dioxide layer having a thickness of less than 2 nanometers and a tantalum nitride layer having a thickness of less than 3 nanometers. The layer and a layer of ceria having a thickness of less than 4 nm. In one embodiment, the synthetic tunneling dielectric layer includes an ultra-thin yttria layer O1 (ie, less than or equal to 15 ), ultra-thin tantalum nitride layer N1 (that is, less than or equal to 30) ) and the ultra-thin ruthenium dioxide layer O2 (that is, less than or equal to 35) ), then the interface with the semiconductor body is less than or equal to 15 The valence band energy of about 2.6 eV is increased below the offset. The O2 layer passes through the lower valence band energy level (higher hole tunneling barrier) and the higher conduction band energy level region at the second offset (ie, about 30 from the interface) To 45 The N1 layer is separated from the charge trapping layer. An electric field sufficient to induce hole tunneling raises the valence band energy level after the second position to a level effective to eliminate the hole tunneling barrier because the second position is farther from the interface. Therefore, the O2 layer does not significantly interfere with the electric field-assisted hole tunneling, while at the same time improving the ability of the design tunneling dielectric to block the spill during the low field.

The charge trapping layer in the memory material layer 115 in this embodiment includes a thickness greater than 50 The tantalum nitride, (who includes? charge trapping layer?? Silicon nitride??), for example, is formed using LPCVD. Niobium nitride. Other charge trapping materials and structures may also be employed, including, for example, yttrium oxynitride (Si _x O _y N _z ), silicon-rich nitride, silicon-rich oxide, and including embedded The trapping layer of embedded nano-particles and the like.

The blocking dielectric layer in the memory material layer 115 in this embodiment includes a thickness greater than 50 The ruthenium dioxide layer includes, for example, about 90 formed by wet conversion of a wet furnace oxidation process. . In other embodiments, high temperature oxidation or LPCVD cerium oxide can also be used. Other barrier dielectrics may include materials with a high Kappa coefficient, such as alumina.

In a representative embodiment, the tunneling layer can be 13 Thick ruthenium dioxide; with offset layer can be 20 Thick tantalum nitride; the isolation layer can be 25 Thick ceria; charge trapping layer can be 70 Thick tantalum nitride; and the barrier dielectric layer can be 90 Thick cerium oxide. The material used for the gates in word lines 116 and 117 is a P+ type polysilicon (work function of about 5.1 eV).

Figure 6 shows the X-Z plane of the charge trap memory cell formed from the word line 116 and the semiconductor strip 114 interface. Active charge trap regions 125 and 126 are formed on both sides of strip 114 between word line 116 and strip 114. In the embodiment described herein, as shown in FIG. 6, each of the memory cells is a dual gate field effect transistor having active charge storage regions 125 and 126 and is located on each side of the semiconductor strip 114. The flow of electrons depicted by solid arrows in the figure flows along the P-shaped semiconductor strip to a sense amplifier where the flow of electrons can be measured to indicate the state of the selected memory cell.

7 shows a cross-sectional view taken from the X-Y plane of the charge trap memory cell formed in the interface between the word lines 116 and 117 and the semiconductor strip 114. The current path down the semiconductor strip 114 is also shown in the figure. Even if there is a lack of source and drain doping with a conductivity type opposite the word line channel region, source/drain regions 128, 129 between the word lines 116 and 117 used as word lines and 130 can also be "no junction". In a junctionless embodiment, the charge trap field effect transistor can have a P-type channel structure. Also, in some embodiments source and drain doping can be performed in a self-aligned implant after word line shaping.

In an alternative embodiment, the semiconductor strips 111-114 can be implemented in a junctionless arrangement using a lightly doped N-type semiconductor body, thus resulting in a hidden channel field effect transistor that can operate in a depletion mode, and It has a naturally shifted lower threshold distribution of the charge trapping unit.

Figure 8 is a schematic diagram showing a plane of a memory cell having nine charge trapping cells in a NAND configuration, which represents a cube that can include many planes and many word lines. The 2 planes of the memory cells are defined at intersections of word lines 160 and 161 used as word lines WLn-1 and WLn with the first stack of semiconductor strips, the second stack of semiconductor strips, and the third stack of semiconductor strips.

The first plane of the memory cell includes memory cells 70 and 71 in a NAND string on a semiconductor strip, memory cells 73, 74 in a NAND string on a semiconductor strip, and NAND strings on a semiconductor strip Memory unit 76, 77. Either side of each NAND string is coupled to a ground select transistor (i.e., ground select transistors 90 and 72 are coupled to either side of NAND strings 70 and 71).

The second plane of the memory cell corresponds in this example to the bottom plane in the cube and includes memory cells (i.e., 80, 82, and 84) disposed in the NAND string in a similar manner to the first plane.

As shown, the word line 161 used as the word line WLn includes a vertical extension corresponding to the material of the trench 120 between the stacks in FIG. 5, in order to couple the word line 161 to all planes. Memory cells (cells 71, 74, and 77 in the first plane) of the interface regions in the trenches between the semiconductor strips.

The memory cell string in the adjacent stack is oriented at the bit line end-to-source line end orientation and the source line end-to-bit line end (source line) The end-to-bit line end orientation) alternates.

Bit lines BL _N and BL _N-1 (i.e., 96) are the end of the memory string adjacent to the string selection device. For example, in the top memory plane, bit line BL _N is the end of the memory cell string with serial select transistors 85 and 89. In contrast, the bit line is not connected to the trace 88 because the tandem of the adjacent stack is between the bit line end-to-source line end and the source line end-to-bit line end alternately. Instead, for this series, the corresponding bit line is connected to the other end of the string. In the memory plane at the bottom, the bit line BL _N-1 is the end of the memory cell string having the corresponding series of selected transistors.

The serial selection transistors 85 and 89 are connected between the respective NAND strings and the string select lines (SSL) SSL _n-1 and SSL _n in this arrangement. Similarly, in the cube on the bottom plane similar series select transistor disposed thereto in series between the respective NAND between the tandem SSL _n-1 and connected to select line SSL _n. Tandem select lines 106 and 108 connect different ridges to the gates of the select transistor in series in each memory cell string, and in this embodiment provide serial select signals SSL _n-1 , SSL _n and SSL _n+1 .

In contrast, the tandem select transistor is not connected to the puller 88 because the tandem of the adjacent stack is at the end of the bit line-to-source line and the source line end-to-bit line end The orientation alternates. Instead, for this series, the corresponding serial selection transistor is connected to the other end of the string. The NAND string with memory cells 73 and 74 also has a serial selection device (not shown) in the other end of the string. The wire 88 ends with a source line 107.

Ground selection transistors 90-95 are disposed at the first end of the NAND string. Ground selection transistors 72, 75, 78 and corresponding second planar ground selection transistors are disposed at the second end of the NAND string. Therefore, the ground selection transistors are on both ends of the memory string. The ground selection transistor couples the memory string to the source line or to the string selection device and the bit line, depending on the particular end of the memory string.

The ground selection signal GSL 159 in this embodiment is coupled to the gate of the ground selection transistor 90-95 and can be implemented using the same method as the word lines 160 and 161 (where 159 and 162 are both grounded). Signal GSL). The serial selection transistor and the ground selection transistor can use the same dielectric stack as the gate oxide, such as the memory cells in some embodiments. In other examples, a typical gate oxide layer is used. Moreover, the length and width of the channel can be adjusted according to the designer's needs to provide the switching function of the transistor.

Figure 9 is a perspective view of an alternative structure as in Figure 5. Reference numerals of similar structures are repeatedly used in this figure, and the description will not be repeated here. 9 is different from FIG. 5 in that the surface 110A of the insulating layer 110 and the sides 113A and 114A of the semiconductor strips 113 and 114 are exposed between the word lines 116 serving as word lines, which form a word line. The result of the etching process. Thus, the memory material layer 115 can be completely or partially etched between the word lines without compromising operation. However, etching through the memory layer 115 to form a dielectric charge trap structure similar to that described herein is not necessary in some constructions.

Figure 10 is a cross-sectional view of the memory cell in the X-Z plane similar to Figure 6. Figure 10 is the same as Figure 6 and depicts a structure similar to that of Figure 9 in which the memory cells implemented in the structure of Figure 5 are available. Figure 11 is a cross-sectional view of the memory cell in the X-Y plane similar to Figure 7. 11 differs from FIG. 7 in that the memory material along the side (ie, 114A) regions 128a, 129a, and 130a of the semiconductor strip 114 can be removed.

Figures 12-16 illustrate the basic flow stages of implementing a 3D memory array as described above, using only two pattern masking steps for the critical calibration steps formed by the array. In Fig. 12, a structure formed by alternately depositing insulating layers 210, 212, 214 formed using a doped semiconductor and semiconductor layers 211 and 213 in, for example, wafer array region blanket deposition is shown. According to such an embodiment, the semiconductor layers 211 and 213 can be implemented using polycrystalline germanium or epitaxial single crystal germanium having N-type or P-type doping. Inter-level insulating layers 210, 212, and 214 can be implemented using, for example, hafnium oxide, other hafnium oxide, or tantalum nitride. These layers can be formed in a number of different ways, including low pressure chemical vapor deposition processes that are useful in the art.

Figure 13 shows the result of a first lithographic patterning step for shaping a plurality of ridge stacks 250 of a semiconductor strip, wherein the semiconductor strip is implemented using the materials of the semiconductor layers 211 and 213, and is insulated by the insulating layer 212 and 214 separation. In-depth, a high aspect ratio and a plurality of layers of trenches can be formed in the stack using a lithographic process using carbon hard masks and reactive ion etching. .

Although not shown in the figure, in this step, the alternate array of memory strings is defined as: bit line end-to-source line end guidance and source line end-to-bit line end guidance.

14A and 14B relatively show the next stage of an embodiment including a programmable resistive memory structure such as an anti-fuse cell structure, and an embodiment including a programmable charge trap memory structure such as a SONOS-type memory cell structure. The next stage.

Figure 14A shows the results of a blanket deposition of memory material layer 215 in one embodiment. In this embodiment, the memory material includes a single layer similar to the anti-fuse structure shown in Figure 1. In another embodiment, an oxide process is used instead of a blanket deposition to form an oxide on the exposed side of the semiconductor strip, wherein the oxide is used as the memory material.

Figure 14B shows the results of layer 315 cladding deposition, including a multilayer charge trapping structure comprising tunneling layer 397, charge trapping layer 398, and barrier layer 399, as described above with respect to Figure 4. As shown in Figures 14A and 14B, memory layers 215 and 315 are deposited in a conformal manner over the semiconductor strip ridge stack.

Figure 15 shows the results of a height aspect ratio filling step in which a layer 225 is formed using a conductive material for use as a word line, such as an N-type or P-type doped polysilicon. Also, the telluride layer 226 can be formed over the layer 225 in an embodiment utilizing polysilicon. As shown in this figure, the trench 220 between the ridge stacks is completely filled by a high aspect ratio deposition technique such as polycrystalline germanium low pressure chemical vapor deposition in the illustrated embodiment, even if the height and width are high. The narrower and narrower grooves are as narrow as about 10 nm.

Figure 16 shows the result of a second planar scribing step for shaping complex digital element lines 260 used as word lines in a 3D memory array. The second slab engraving step utilizes a single mask to etch a high aspect ratio trench between the word lines for the critical dimension of the array. The polysilicon can be etched using an etching process that is highly selective to polysilicon and is more selective than ceria and tantalum nitride. Therefore, the alternating etch process is used to etch through the conductive and insulating layers by the same mask and terminates on the insulating layer 210 as a foundation.

In this step, the ground selection line can also be formed. In this step, the gate structure controlled by the string selection line can also be formed, even if the gate structure is conformal to the individual semiconductor strip stack.

The optional fabrication steps include forming a hard mask on the complex digital line and forming a hard mask on the gate structure. The hard mask can be formed using a relatively thin layer of tantalum nitride or other material that blocks the ion implantation process. After the hard mask is formed, implantation can be performed to increase the doping concentration in the semiconductor strip and the stairstep structure to reduce the resistance along the current path of the semiconductor strip. By utilizing the energy of the implant, it is possible to cause the implant to penetrate into the bottom of the semiconductor strip and each cover the semiconductor strip in the stack.

Subsequently, the hard mask is removed, exposing the top layer along the word line and the germanide layer on the gate structure. After an interlayer dielectric is formed on top of the array, vias are opened, and in the vias, for example, a tungsten-filled contact plug is formed to reach the top of the gate structure. surface. The overlay metal lines are scribed to connect to the column decoder circuit as an SSL line. A three-plane decoding network is created that uses a word line, a bit line, and an SSL line to access selected cells. See U.S. Patent No. 6,069,940, entitled "Plane Decoding Method and Device for Three Dimensional Memories."

Figure 17 is a partial TEM cross-sectional view of an 8-layer vertical gate, thin film transistor, and BE-SONOS charge trap NAND device that has been simulated and tested. The device was fabricated at a half pitch of 75 nm. The channel is an N-type polysilicon of about 18 nm thick. Without the use of additional joints, it becomes a jointless structure. The insulating material separating the Z-direction channels between the strips is about 40 nm thick of cerium oxide. The gate is provided by a P+ polysilicon line. The SSL and GSL devices have a longer channel length than the memory cells. The test set implements 32 word lines and a NAND series without junctions. Because the trench used to form the structure etches a tapered sidewall having a strip that tapers as the trench is deeper, and because the tapered sidewall has an insulation between the strips that are more etched relative to the polysilicon Material, so the width of the lower band in Figure 17 is greater than the width of the higher band.

Figure 17 shows the different layers of a 3D structure with different side dimensions. This different side dimension between the layers is the source of the different capacitances between the different layers of the 3D structure.

Figure 18 is a simplified block diagram of an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit line 875 includes a 3D programmable resistive memory array 860 (RRAM) implemented as described herein over a semiconductor substrate having bit line end-to-source line ends The alternate memory is guided in series with the source line end-to-bit line end and is located at either end of the tandem select line gate structure stack over all other stacks. Column decoder 861 is coupled to a plurality of word line lines 862 and is disposed along a row of memory array 860. Row decoder 863 is coupled to a plurality of SSL lines 864 disposed along rows corresponding to stacked in memory array 860 to read and program data from memory cells in array 860. Planar decoder 858 is coupled to the complex planes in memory array 860 on bit line 859. Addresses are provided on bus 865 to row decoder 863, column decoder 861, and plane decoder 858. The sense amplifier and data-in structure in block 866 is coupled to row decoder 863 via data bus 867 in this embodiment. The data is provided from the input/output port on the integrated circuit 875 through the data input line 871, or from a data source internal or external to the other integrated circuit 875 to the data input structure in block 866. In the illustrated embodiment, the integrated circuit includes other circuitry 874, such as a general purpose processor or application specific application circuitry, or a system-on-a-system that provides programmable resistor cell array support (system-on- A-chip) A combination of functional modules. The data is provided from the sense amplifier in block 866 through the data-out line 872 to the input/output ports on the integrated circuit 875 or to the data destinations internal or external to the other integrated circuits 875.

A controller implemented in this embodiment using a bias arrangement state machine 869 is used to control the supply voltage of the bias voltage generated or provided by one or more voltage supplies in block 868. Applications such as reading and programming voltages. The controller can be implemented using special purpose logic circuitry in the well-known art. In an alternate embodiment, the controller includes a general purpose processor, the controller can be implemented on the same integrated circuit, and the general purpose processor included executes a computer program to control the operation of the device. In yet another embodiment, a combination of special purpose logic circuitry and general purpose processors can be utilized to implement other controllers.

Figure 19 is a simplified block diagram of an integrated circuit in accordance with an embodiment of the present invention. The integrated circuit line 975 includes a 3D NAND flash memory array 960 having alternating memory string alignment on a semiconductor substrate implemented as described herein, and is located in a tandem select line gate having all other stacks. At either end of the stack of structures, the so-called alternate memory string alignment is oriented from the bit line end-to-source line end and the source line end-to-bit line end. Column decoder 961 is coupled to a plurality of word line lines 962 and is disposed along columns in memory array 960. Row decoder 963 is coupled to a plurality of SSL lines 964 disposed along rows corresponding to stacked in memory array 960 to read and program data from memory cells in array 960. Planar decoder 958 is coupled to a plurality of planes in memory array 960 via bit line 959. An address is provided on the bus 965 (bus) to a row decoder 963 (colum decoder), a column decoder 961 (row decoder), and a plane decoder 958 (plane decoder). The sense amplifier and data input structure in block 966 is coupled to row decoder 963 via data bus 967 in this embodiment. The data is provided from the input/output port on the integrated circuit 975 through the data input line 971, or from a data source internal or external to the other integrated circuit 975 to the data input structure in block 966. In the illustrated embodiment, the integrated circuit includes other circuitry 974, such as a general purpose processor or application specific application circuitry, or a combination of on-chip system functional modules that provide programmable resistance cell array support. . The data is provided from the sense amplifier in block 966 through the data output line 972 to the input/output ports on the integrated circuit 975 or to the data destinations internal or external to the other integrated circuit 975.

The controller implemented in this embodiment using the bias setting state machine 969 is an application for controlling the supply voltage through the bias voltage generated or provided by one or more voltage supplies in block 968, such as reading, Erase, program, erase verify, and program verify voltage. The controller can be implemented using special purpose logic circuitry in the well-known art. In an alternate embodiment, the controller includes a general purpose processor, the controller can be implemented on the same integrated circuit, and the general purpose processor included executes a computer program to control the operation of the device. In yet another embodiment, a combination of special purpose logic circuitry and general purpose processors can be utilized to implement other controllers.

20-22 illustrate a laterally directed string select line parallel to a strip of semiconductor material, a laterally directed string select line parallel to the word line, and a progressive metal layer parallel to the longitudinal guide bit line of the strip of semiconductor material. The first 3D NAND flash memory array structure.

Figure 20 is a perspective view of the structure of the first 3D NAND flash memory array. The insulating material is removed from the drawing to expose additional structures. For example, the insulating layers are removed between the semiconductor strips in the ridge stack and removed between the ridge stacks of the semiconductor strips.

The multilayer array is formed on the insulating layer and includes a plurality of word lines 425-1, ..., 425-n-1 and 425-n conformed to the plurality of ridge stacks, wherein the plurality of word lines are used Word lines WLn, WLn-1, ... WL1 are formed. The plurality of ridge stacks include semiconductor strips 412, 413, 414, and 415. The semiconductor strips in the same plane are electrically coupled to the stepped structure.

The illustrated word line number, which gradually increases from 1 to N from the rear end to the front end of the structure, is applied to even memory pages. For odd-numbered memory pages, the word line number is gradually reduced from N to 1 from the back end of the structure to the front end.

The stepped structures 412A, 413A, 414A, and 415A are the ends of the semiconductor strips, such as the ends of the semiconductor strips 412, 413, 414, and 415. As shown, these ladder structures 412A, 413A, 414A, and 415A are electrically coupled to different bit lines to connect the decoding circuitry to a selection plane in the array. These stepped structures 412A, 413A, 414A, and 415A can be scribed while forming a plurality of ridge stacks.

The stepped structures 402B, 403B, 404B, and 405B are the ends of the semiconductor strips, such as the ends of the semiconductor strips 402, 403, 404, and 405. As shown, these ladder structures 402B, 403B, 404B, and 405B are electrically coupled to different bit lines to connect the decoding circuitry to a selection plane in the array. These stepped structures 402B, 403B, 404B, and 405B can be scribed while forming a plurality of ridge stacks.

Any given semiconductor strip stack is not coupled to the ladder structures 412A, 413A, 414A, and 415A, or to the ladder structures 402B, 403B, 404B, and 405B, but is not coupled to both. The semiconductor strip stack has one of two opposite orientations of the bit line end-to-source line end guide or the source line end-to-bit line end guide. For example, the stack of semiconductor strips 412, 413, 414, and 415 has bit line end-to-source line end guidance, while the stack of semiconductor strips 402, 403, 404, and 405 has source line-to-bit lines. End oriented.

The stack of conductor strips 412, 413, 414, and 415 ends at one end by stepped structures 412A, 413A, 414A, and 415A, through SSL gate structure 419, gate select line GSL426, and word line 425-1WL to 425- N WL, the gate select line GSL427, then ends at the other end through source line 428. The stack of semiconductor strips 412, 413, 414, and 415 does not reach the stepped structures 402B, 403B, 404B, and 405B.

The stack of semiconductor strips 402, 403, 404, and 405 ends at one end by stepped structures 402B, 403B, 404B, and 405B, through SSL gate structure 409, gate select line GSL427, and word line 425-NWL to 425- 1 WL, gate select line GSL426, then end at the other end through the source line (covered by other parts of the illustration). The stack of semiconductor strips 402, 403, 404, and 405 does not reach the stepped structures 412A, 413A, 414A, and 415A.

As described in detail in the previous figures, the memory material layer separates word lines 425-1 through 425-n from semiconductor strips 412-415 and 402-405. The ground select lines GSL 426 and GSL 427 are conformed to a plurality of ridge stacks, similar to word lines.

One end of each stack of semiconductor strips ends with a stepped structure and ends with the source line as the other end. For example, the stack of semiconductor strips 412, 413, 414, and 415 end through one of the stepped structures 412A, 413A, 414A, and 415A and end through the source line 428 at the other end. At the proximal end of the figure, a portion of the semiconductor strip stack ends through the stepped structures 402B, 403B, 404B, and 405B, while all other portions of the semiconductor strip stack end through the source line. At the distal end of the figure, all of the other portions of the semiconductor strip stack are passed through the stepped structures 412A, 413A, 414A, and 415A, and the portion of the semiconductor strip stack is terminated through the source line.

The bit line and the string selection line are formed in the metal layers ML1, ML2, and ML3, and are discussed in the more obvious lower view.

The transistor is formed between the stepped structures 412A, 413A, 414A and the word line 425-1. In a transistor, a semiconductor strip (ie, 413) is used as the channel region of the device. The SSL gate structures (i.e., 419 and 409) are scribed during the same steps that shape the word lines 425-1 through 425-n. A telluride layer can be formed along the top surfaces of the word lines 425-1 through 425-n and the ground select lines 426 and 427, and over the gate structures 409 and 419. The layer of memory material 415 can be used as the gate dielectric of the transistor. These transistors are used as a series select gate coupled to the decoding circuitry to select a particular ridge stack in the array.

21 and 22 are side views of the first 3D NAND flash memory array structure shown in FIG. Figure 21 shows all three metal layers ML1, ML2 and ML3. Figure 22 shows the lower two metal layers ML1 and ML2 with the third metal layer ML3 removed to make the other metal layers easier to view.

The first metal layer ML1 includes a string selection line having a longitudinal orientation parallel to the strip of semiconductor material. These ML1 serial select lines are connected to different SSL gate structures (ie, 409 and 419) through short vias.

The second metal layer ML2 includes a string selection line having a lateral orientation parallel to the word line. These ML2 serial select lines are connected to different ML1 string select lines through short vias.

When combined, these ML1 serial select lines and ML2 tandem select lines allow the use of a series select signal to select a particular stack of semiconductor strips.

The first metal layer ML1 also includes two source lines having lateral orientations parallel to the word lines.

Finally, the third metal layer ML3 comprises a bit line having a longitudinal orientation parallel to the strip of semiconductor material. The different bit lines are electrically connected to different steps of the step structures 412A, 413A, 414A and 415A and 402B, 403B, 404B and 405B. These ML3 bit lines allow the use of bit line signals to select a particular horizontal plane of the semiconductor strip.

Since the specific word line allows the character line to select a particular column plane of the memory cell, the triple combination of the word line signal, the bit line signal, and the serial line signal is sufficient to select a particular memory from the 3D array of memory cells. unit.

23-26 illustrate a laterally directed string select line parallel to the word line, a longitudinal guide string select line parallel to the semiconductor strip, and a progressive metal layer parallel to the longitudinal guide bit line of the strip of semiconductor material. A 3D NAND flash memory array structure.

The second 3D NAND flash memory array shown in Figures 23-26 is generally similar to the first 3D NAND flash memory array shown in Figures 20-22. To facilitate viewing, Figure 26 further removes all three metal layers ML1, ML2, and ML3.

However, the second 3D NAND flash memory array shown in Figures 23-26 shows 32 word lines, while the first 3D NAND flash memory array shown in Figures 20-22 shows 8 characters. line. Other embodiments have a different number of word lines, bit lines, and tandem select lines, as well as correspondingly different numbers of semiconductor strip stacks and the like.

Moreover, the second 3D NAND flash memory array shown in Figures 23-26 shows the different stages of connecting the contact plugs to the stepped structure with polysilicon plugs, while the first 3D NAND flash memory shown in Figures 20-22 The array shows the metal contact plugs that connect the ML3 bit lines to different stages of the step structure.

Further, the second 3D NAND flash memory array shown in Figures 23-26 has a tandem select line to the ML1 decoder and a tandem select line to the SSL gate structure on the ML2, and Figures 20-22 The first 3D NAND flash memory array shown has a tandem select line to the ML2 decoder and a serial select line to the SSL gate structure on ML1.

27 is a structural diagram of the structure of the first 3D NAND flash memory array of FIGS. 20-22.

In the design of Figure 27, the semiconductor strip stack is shown as a vertical strip with a dot-dash edge. Adjacent semiconductor strip stacks alternate between opposing conductors, that is, between bit line end-to-source line end directors and source line end-to-bit line end guides. A portion of the semiconductor strip stack runs from the top bit line structure to the bottom source line structure. All other portions of the semiconductor strip stack run from the top source line structure to the bottom bit line structure.

Covering the semiconductor strip stack is a horizontal word line and horizontal ground select lines GSL (even) and GSL (odd). The semiconductor strip is stacked and is an SSL gate structure. The SSL gate structure covers a portion of the semiconductor strip stack at the top of the semiconductor strip and covers all other semiconductor strip stacks at the bottom end of the semiconductor strip. In both cases, the SSL gate structure controls the electrical connection between any of the semiconductor strip stacks and the bit line contact structures corresponding to the stack.

The character line numbers shown are gradually increased from 1 to N from the top of the figure to the bottom of the figure, and are applied to even memory pages. For odd-numbered memory pages, the word line numbers are gradually reduced from N to 1 from the top of the figure to the bottom of the figure.

Overlay word lines, ground select lines, and SSL gate structures are vertically running ML1 SSL serial select lines. Covering the ML1 SSL serial line selection is the horizontally running ML2 SSL serial line selection line. Although the ML2 SSL serial selection line is shown as the end of the corresponding ML1 SSL serial selection line in order to easily view the structure, the horizontal operation of the ML2 SSL serial selection line can be extended. The ML2 SSL serial select line carries the signal from the decoder, and the ML1 SSL serial select line couples these decoder signals to a particular SSL gate structure to select a particular semiconductor strip stack.

The source line that covers the ML1 SSL serial selection line and is an odd number and an even number.

Further, the ML2 SSL serial selection line is covered by the ML3 bit line connected to the stepped contact structure at the top and bottom ends (not shown in the figure). Through the step contact structure, the bit line can select a particular plane of the semiconductor strip.

28 is a layout diagram of the second 3D NAND flash memory array structure of FIGS. 23-26. The second 3D NAND flash memory array structure shown in FIG. 28 is substantially similar to the first 3D NAND flash memory structure design shown in FIG. However, the second 3D NAND flash memory array shown in FIG. 28 has a tandem select line to the ML1 decoder and a tandem select line to the SSL gate structure on ML2, while the first 3D shown in FIG. The NAND flash memory structure has a serial select line to the ML2 decoder and a tandem select line to the SSL gate structure on ML1.

Figure 29 is a plan view of a 3D memory array. In the array shown, Y half pitch = 32 nm and X half pitch = 43 nm. There are 4 memory layers in 3D VG NAND. The core efficiency in the array is approximately 67% (66 WLs, with SSL gates, GSL, SL, and BL contacts). When operating in a single level cell (1b/c), its density is 32Gb. The wafer size is approximately 76 mm ² .

Figure 30 illustrates a 3D NAND fast with a laterally directed string select line parallel to the word line, a longitudinal guide string select line parallel to the semiconductor strip, and a progressive metal layer parallel to the longitudinal guide bit line of the strip of semiconductor material. Flash memory array structure. Figure 30 is similar to Figure 23. Figure 30 is a comparison of the change of Figure 23 to the first set of array layer numbers (1) - (4) to the bit line, and the second set of array layer numbers (1) - (4) to include the step structure Bit line structure of 402B, 403B, 404B, and 405B. These array layer number groups are used to display that a particular bit line is electrically connected to a particular array layer location.

Figure 30 shows a memory block having a sequence of 1, 2, 3, and 4 planar positions. Correspondingly, as the bit line structure traverses from the first end to the second end, consecutively numbered bit lines 1-4 (that is, numbered from left to right, right to left, or other consecutive order) are borrowed. The step contact structure (also referred to as a bit line structure) is coupled to plane positions 1-4 (ie, numbered from top to bottom, bottom to top, or other order).

Figure 31 is a block diagram showing the structure of a 3D NAND flash memory array having bit lines labeled with the number of the access layer arrays in a particular bit line. In the example shown, as with the four bit lines that are traversed sequentially (that is, numbered from left to right, right to left, or other order), the bit lines are also in plane positions 1, 2, and 3. And 4 to mark. Therefore, as with the four bit lines that are sequentially traversed, the bit lines are also coupled to the plane positions 1-4 by a step contact structure (also referred to as a bit line structure) displayed in a dashed box. It is numbered from top to bottom, bottom to top or other order).

32 is a block diagram of a bit line 3DNAND flash memory array structure having numbered arrays accessed by bit lines, showing blocks adjacent to bit lines coupled to the array layer in different sequences. .

Figure 32 shows a translation sequence with different bit line structures having planar positions. For example, the different sequences of the different bit line structure plane positions shown are 1, 2, 3, and 4; 2, 3, 4, and 1; and 3, 4, 1, and 2. Correspondingly, the bit line running from the top to the bottom and connected to different bit line structures is connected to the plane positions 1, 2 and 3 (in order from the top bit line structure to the bottom bit line structure) . The second left bit runs from top to bottom and is connected to bit lines of different bit line structures, connected to plane positions 2, 3, and 4 (in order from top bit line structure to bottom bit line structure). The third left run from top to bottom and connected to different bit line structures is connected to plane positions 3, 4 and 1 (in order from top bit line structure to bottom bit line structure). The fourth left bit runs from top to bottom and is connected to bit lines of different bit line structures, connected to plane positions 4, 1 and 2 (in order from top bit line structure to bottom bit line structure).

In some embodiments, the number of the bit line structure and the number of the memory block are selected such that each word line has the same so-called capacitance as other word lines, because the coupling is the same. Combine in the plane position of other bit lines.

Various embodiments include a different number of bit lines and a different number of planar positions coupled to the bit lines, such as double or quadratic.

The present invention has been described in detail with reference to the preferred embodiments and examples thereof. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10, 110, 210, 212, 214. . . Insulation

11-14, 51-56, 111-114. . . Semiconductor strip

15, 115, 215, 315. . . Memory material layer

16, 17, 60-61, 116, 117, 160, 161, 260. . . Word line

18, 19, 118, 119, 226. . . Telluride

20, 120, 220. . . Trench

21-24, 121-124. . . Insulation Materials

25, 26. . . Active zone

30-35, 40-45. . . Memory unit

60-1~60-3. . . Character line extension

97, 397. . . Tunneling dielectric layer

98, 398. . . Charge storage layer

99, 399. . . Blocking dielectric layer

125, 126. . . Charge trapping area

128-130. . . Source/drain region

70, 71, 73, 74, 76, 77, 80, 82, 84. . . Memory unit in NAND string

72, 75, 78, 90-95. . . Ground selection transistor

96. . . Bit line

85, 89. . . Tandem selection transistor

88. . . Thread

106, 108. . . Serial selection line

107. . . Source line

159, 162. . . Ground selection signal

113A, 114A. . . Side of semiconductor strip

110A. . . Insulation surface

128a-130a. . . Along the side of the semiconductor strip

211, 213. . . Semiconductor layer

250. . . Ridge stacking of semiconductor strips

225. . . Floor

858, 958. . . Planar decoder

96, 859, 959. . . Bit line

860, 960. . . Memory array

861, 961. . . Column decoder

862, 962. . . Word line

863, 963. . . Row decoder

864, 964. . . Serial selection line

865, 965. . . Busbar

866, 966. . . Square

867, 967. . . Data bus

868, 968. . . Square

869, 969. . . Bias setting state machine

871, 971. . . Data input line

872, 972. . . Data output line

874, 974. . . Other circuit systems

875, 975. . . Integrated circuit

402-405, 412-415. . . Semiconductor strip

402B-405B, 412A-415A. . . Step structure

409, 419. . . Tandem selection line gate structure

426, 427. . . Ground selection line

425-1~425-N. . . Word line

428. . . Source line

1 is a perspective view of a 3D memory structure as described herein, including a plurality of planes of a strip of semiconductor material parallel to the Y-axis and disposed in a plurality of ridge stacks, a memory layer on a side of the semiconductor strip, and a plurality of conformal features. A word line disposed on the bottom surface and spanning the ridge stacks.

2 is a cross section of a memory cell taken from the X-Z plane of the structure of FIG. 1.

Figure 3 is a cross section of the memory cell taken from the X-Y plane of the structure of Figure 1.

4 is a schematic diagram of a memory having an antifuse based on the structure of FIG. 1.

5 is a perspective view of a 3D NAND flash memory structure as described herein, including a plurality of semiconductor strip planes parallel to the Y-axis and disposed in a plurality of ridge stacks, a charge trapping memory layer on a side of the semiconductor strip, and A plurality of word lines having a conformal bottom surface and disposed across the plurality of ridge stacks.

Figure 6 is a cross section of the memory cell taken from the X-Z plane of the structure of Figure 5.

Figure 7 is a cross section of the memory cell taken from the X-Y plane of the structure of Figure 5.

FIG. 8 is a schematic diagram of a NAND flash memory having the structure of FIGS. 5 and 23.

9 is a perspective view of another embodiment of a 3D NAND flash memory structure similar to that of FIG. 5 with the memory layers removed from between the word lines.

Figure 10 is a cross section of the memory cell taken from the X-Z plane of the structure of Figure 9.

Figure 11 is a cross section of the memory cell taken from the X-Y plane of the structure of Figure 9.

Figure 12 illustrates the first stage of a process for fabricating a memory device similar to that of Figures 1, 5 and 9.

Figure 13 illustrates the second stage of a process for fabricating a memory device similar to that of Figures 1, 5 and 9.

Figure 14A illustrates a third stage of making a program similar to the memory device of Figure 1.

Figure 14B is a diagram showing the third stage of manufacturing a program similar to the memory device of Figure 5.

Figure 15 is a diagram showing the third stage of manufacturing a program similar to the memory devices of Figures 1, 5 and 9.

Figure 16 illustrates the fourth stage of a process for fabricating a memory device similar to that of Figures 1, 5, and 9, followed by another stage of a hard mask and a selective implantation step.

Figure 17 is a transmission electron microscope (TEM) image of a 3D NAND flash memory array portion.

Figure 18 is a schematic diagram of an integrated circuit including a 3D programmable resistive memory array having row, column and planar decoding circuitry.

Figure 19 is a schematic diagram of an integrated circuit including a 3D NAND flash memory array having row, column and planar decoding circuitry.

20-22 illustrate a first 3D NAND flash memory array structure having a raised metal layer longitudinally parallel to the tandem select lines of the strip of semiconductor material, a tandem select line laterally parallel to the word line, and The longitudinal direction is parallel to the bit line of the strip of semiconductor material.

23-26 illustrates a second 3D NAND flash memory array structure having a raised metal layer longitudinally parallel to the tandem select lines of the semiconductor material strip, a tandem select line laterally parallel to the word line, and The longitudinal direction is parallel to the bit line of the strip of semiconductor material.

FIG. 27 is a layout diagram of the first 3D NAND flash memory array structure of FIGS. 20-22.

28 is a layout diagram of the second 3D NAND flash memory array structure of FIGS. 23-26.

Figure 29 is a plan view of a 3D memory array.

Figure 30 is a diagram showing a 3D NAND flash memory array structure accessed by bit lines and having bit lines labeled by array layer numbers.

Figure 31 is a block diagram of a 3D NAND flash memory array structure accessed by bit lines and having an array layer number designation.

32 is a design diagram of a 3D NAND flash memory array structure accessed by bit lines and having an array layer number designation, and showing adjacent blocks having bit lines coupled to the array layers in different sequences. .

ML1-3. . . Metal layer

412A~415A, 402B~405B. . . Step structure

402~405, 412~415. . . Semiconductor strip

419. . . Tandem selection line gate structure

426, 427. . . Ground selection line

425-1~425-N. . . Word line

428. . . Source line

Claims (20)

A memory device comprising: a memory array having a plurality of memory cells at a plurality of planar positions; and a plurality of step contact structures having a plurality of sequences having a plurality of planar positions, the sequences comprising at least two different a sequence, each of the sequences depicting sequential features of the planar contact locations of the step contact structures coupled to the plurality of bit lines; wherein the adjacent two steps of the step contact structures And a portion of the plurality of bit lines in the memory array in the contact structure, coupled to the memory cells located on one of the planar locations, and not in other locations located at the planar locations The memory units on the device are coupled. The memory device of claim 1, wherein the memory cells of the array are disposed along a plurality of strips of semiconductor material in a NAND string. The memory device of claim 1, wherein the memory cells of the memory array are disposed along a plurality of semiconductor material strips between the step contact structures and the plurality of source lines. The memory device of claim 1, wherein the different capacitances characterize the different planar positions of the planar locations. The memory device of claim 1, wherein the different sequences of the sequences of the step contact structures are flat The distinct capacitances depicting the different planar positional features of the planar locations are all described. The memory device of claim 1, wherein the step contact structure of the step contact structures is coupled to the planar positions of the bit lines from the step contact structures A first end of the step contact structure spans a second end corresponding to one of the step contact structures. The memory device of claim 1, wherein the memory array is divided into a plurality of memory blocks by the step contact structures. The memory device of claim 1, wherein the plurality of semiconductor material strips in the memory array are stacked in a specific semiconductor strip and one of a plurality of word lines in the memory array is a specific word line The combined selection is used to identify a particular memory unit in the memory array. The memory device of claim 1, wherein the memory cells of the memory array comprise a plurality of charge trapping structures, the charge trapping structures comprising a tunneling layer and a charge a trap layer and a barrier layer. The memory device of claim 1, comprising: a substrate; a plurality of semiconductor material strips stacked in a ridge shape, and comprising at least two strips of semiconductor material separated by an insulating material In a plurality of plane positions; a plurality of word lines disposed across the stacks and having a conformal surface with the stacks; and a plurality of memory elements located in an interface region, the memories The component establishes a memory array of the memory cells through the strips of semiconductor material and the word lines; wherein the step contact structures are located at the ends of the stacks. A memory device includes: a memory array having a plurality of memory cells in a plurality of planar positions; and a plurality of bit lines, each of the bit lines being coupled to the planar positions Having at least two different planar positions, and accessing the memory cells at the at least two different planar positions; wherein, one of the bit lines in the portion of the memory array is coupled to the planes The memory cells on one of the locations are not coupled to the memory cells located on the other of the planar locations. The memory device of claim 11, wherein the memory cells of the memory array are disposed along a plurality of semiconductor material strips in a NAND string. The memory device of claim 11, wherein the memory cells of the memory array are disposed along a plurality of semiconductor material strips between the plurality of step contact structures and the plurality of source lines. The memory device of claim 11, wherein the different capacitances describe different planar positions of the planar positions. Characteristics. The memory device of claim 13, wherein the memory array is divided into a plurality of memory blocks by the step contact structures. The memory device of claim 11, wherein a plurality of semiconductor material strips in the array are associated with a specific semiconductor strip and a combination of a plurality of word lines of the word lines in the memory array The selection is used to identify a particular memory unit in the array of memory. The memory device of claim 11, wherein the memory cells of the memory array comprise a plurality of charge trapping structures, the charge trapping structures comprising a tunneling layer and a charge a trap layer and a barrier layer. The memory device of claim 13, comprising: a substrate; a plurality of semiconductor material strips stacked in a ridge shape, and comprising at least two strips of semiconductor material separated by an insulating material a plurality of plane positions; a plurality of word lines disposed across the stacks and having a conformal surface with the stacks; and a plurality of memories located in an interface region And a memory device that establishes a memory array of the memory cells through the strips of semiconductor material and the word lines; wherein the step contact structures are located at ends of the stacks. The memory device of claim 18, wherein each of the bit lines is coupled to at least two different planar positions of the different stacked stacks of semiconductor material strips, wherein The two different planar positions include a first planar position of a first semiconductor strip stack and a second planar position of a second semiconductor strip stack such that the first semiconductor strip stack and the second semiconductor strip stack are phased Different memory blocks. The memory device of claim 18, wherein each of the bit lines is coupled to at least two different planar positions of the different stacked stacks of semiconductor material strips, wherein the two The dissimilar planar position includes the first planar position of the first semiconductor strip stack and the second planar position of the second semiconductor strip stack such that the first semiconductor strip stack and the second semiconductor strip stack are The different group of character lines of the word line are accessed.