CN105990354B - Memory component and preparation method thereof - Google Patents
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- CN105990354B CN105990354B CN201510042457.3A CN201510042457A CN105990354B CN 105990354 B CN105990354 B CN 105990354B CN 201510042457 A CN201510042457 A CN 201510042457A CN 105990354 B CN105990354 B CN 105990354B
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Abstract
The invention discloses a kind of memory component and preparation method thereof, the memory component include multiple silicon-containing conductive layers be in parallel to each other vertical stack on substrate.A plurality of serial selection line is located above silicon-containing conductive layer, and extends in a first direction.It is a plurality of serially perpendicular to silicon-containing conductive layer and serial selection line, and be electrically connected to serial selection line.It is online that multiple bit lines are located at serial selection, and extends in a second direction.Multiple groups multilayer plug structure is arranged along first direction, is serially located in multiple between adjacent two multilayer plug structures respectively.Wherein, each multilayer plug structure includes multiple interlayer plugs, each interlayer plug conducting corresponding with a silicon-containing conductive layer.A plurality of metal word lines.Wherein, each metal word lines extend in a first direction, and are electrically connected with the interlayer plug that same silicon-containing conductive layer is connected.
Description
Technical field
The invention relates to a kind of semiconductor elements and preparation method thereof, and in particular to a kind of memory component
And preparation method thereof.
Background technique
Non-volatile memory device, such as flash memory are stored in storage unit with also not losing when removing power supply
Information characteristic.It has been widely used in the solid-state large-capacity for portable music player, mobile phone, digital camera etc.
Storage application.In order to reach the demand with more high density storage capacity, there is the three-dimensional storage of various different structures at present
Device element, such as with single grid (single-gate) storage unit, bigrid (double gate) storage unit, and surround
The three-dimensional flash memory element of formula grid (surrounding gate) storage unit, is suggested.
Three-dimensional storage element, such as vertical channel formula (vertical-channel, VC) three dimensional NAND flash element, tool
There are many layer laminate (memory layer) structures, can reach higher storage volume, with more excellent characteristic electron, such as with
Good data save reliability and service speed.However, as component size continues downsizing, by conducting wire, such as wordline or
Source electrode line, resistance and capacitor caused by signal propagation delay (RC delay), will become influence three-dimensional storage element wipe
One of the principal element of service speeds such as remove and program.Industry uses the metal compared with low-resistance value as vertical channel formula more at present
The grid of three dimensional NAND flash element, to reduce the time delay of wordline.
However, the metal gates manufacturing process of vertical channel formula three dimensional NAND memory element, it is necessary to be initially formed through more
It etches channel in layer stacked structure, then with another etching, is removed via etching channel more sacrificial in layer stacked structure
Domestic animal layer, can carry out the filling of metal gates (wordline).The setting for etching channel, can occupy the formation space of storage unit, shadow
Ring the storage volume of element.In addition being easy residual sacrificial layer in multi-layer laminate structure, or storage is damaged because of overetch
Layer, and storage unit defect is caused, seriously affect the storage volume and process yields of vertical channel formula three dimensional NAND flash element.
Therefore, in need that a kind of more advanced memory component and preparation method thereof is provided, to improve known technology institute face
The problem of facing.
Summary of the invention
One embodiment of this specification is to provide a kind of memory component.This memory component includes multiple siliceous leads
Electric layer, a plurality of serial selection line (selection lines), a plurality of serial (string), multiple bit lines (bit lines), more
Group multilayer plug structure and a plurality of metal word lines (metal strapped word line).Wherein, silicon-containing conductive layer is phase
Mutual vertical stack in parallel is on substrate.Serial selection line is located above silicon-containing conductive layer, and extends in a first direction.It is serial to hang down
Directly in silicon-containing conductive layer and serial selection line, and it is electrically connected to serial selection line.Bit line is located above serial selection line, and edge
Second direction extends, and is electrically connected respectively with serial.Multilayer plug structure is arranged along first direction, by multiple serial points
It is not located between two adjacent multilayer plug structures.Wherein, each multilayer plug structure includes multiple interlayer plugs, often
The conducting corresponding with a silicon-containing conductive layer of one interlayer plug.Metal word lines extend in a first direction, and each metal word lines
It is electrically connected with the interlayer plug that the same silicon-containing conductive layer is connected.
Another embodiment of this specification is to provide a kind of production method of memory component, and this method includes following
Step: first in the multiple silicon-containing conductive layers for forming vertical stack on substrate and being parallel to each other.Later, it is formed a plurality of serial vertical
Wear silicon-containing conductive layer.A plurality of serial selection line is formed on silicon conducting layer, and extends in a first direction serial selection line,
And it is serial to be electrically connected these.Then, multiple groups multilayer plug structure is formed, is arranged along first direction, by multiple serial points
It is not located between adjacent two multilayers plug structure.Wherein, each multilayer plug structure includes multiple interlayer plugs, each
The conducting corresponding with a silicon-containing conductive layer of interlayer plug.It is subsequent, it is online rectangular at multiple bit lines in serial selection, make bit line along the
Two directions extend, and with this few serial electric connection.A plurality of metal word lines are formed above multilayer plug structure, along first
Direction extends, and makes each metal word lines and the interlayer plug electric connection of the same siliceous conduction is connected.
According to above-described embodiment, the present invention is to provide a kind of memory component and preparation method thereof.It is deposited in three-dimensional
Multiple groups are formed in the multi-layer laminate structure of memory element along the multilayer plug structure of serial selection line setting arranged in parallel, by shape
It is serially located between two adjacent multilayer plug structures respectively at a plurality of in multi-layer laminate structure, and makes multilayer plug
Each interlayer plug that structure is included, respectively conducting corresponding with a silicon-containing conductive layer in multi-layer laminate structure.And with
Multiple interlayer plugs that same silicon-containing conductive layer is connected are electrically connected by metal word lines.Pass through multilayer plug structure and metal word lines
Connection, to reduce the overall resistivity of grid layer in three-dimensional storage element, to reduce caused by grid resistance and capacitor
Signal propagation delay phenomenon.Again since three-dimensional storage element is to be not required to be additionally formed as grid using siliceous conductive material
Metal gates can expand the frequency bandwidth of serial selection line, known technology be solved, because using caused by metal gate process
The problem of storage volume and process yields can not improve.
Detailed description of the invention
In order to be clearer and more comprehensible to the above embodiment of the present invention and other objects, features and advantages, spy lift it is several compared with
Good embodiment, and cooperate institute's accompanying drawings, it is described in detail below:
Figure 1A is that the part-structure that an embodiment according to the present invention is painted the multi-layer laminate structure being formed on substrate is saturating
View；
Figure 1B be formed in the structure for be shown in Figure 1A it is a plurality of it is serial after part-structure perspective view；
Fig. 1 C is the structure top view according to depicted in Figure 1B；
Fig. 1 D is that a plurality of part-structure perspective formed after a plurality of serial selection line is formed in the structure for be shown in 1B
Figure；
Fig. 1 E is the structure top view according to depicted in Fig. 1 D；
Fig. 1 F be shown in Fig. 1 D structure on form the part knot after multiple groups multilayer plug structure and contact plunger
Structure perspective view；
Fig. 1 G is the structure top view according to depicted in Fig. 1 F；
Fig. 1 H is the structure top view after forming a plurality of source electrode line and bit line in the structure for be shown in Fig. 1 G；
Fig. 1 I is the structure top view after forming a plurality of metal word lines in the structure for be shown in Fig. 1 H；
Fig. 2A to Fig. 2 D is that serial part knot technique structure section signal is formed depicted in an embodiment according to the present invention
Figure；
Fig. 3 is another step structure pattern for being painted multilayer plug structure according to another embodiment of the present invention；
Fig. 4 A is along part-structure sectional view depicted in tangent line S1 depicted in Fig. 1 H；
Fig. 4 B is along part-structure sectional view depicted in tangent line S2 depicted in Fig. 1 H；
Fig. 5 is the part of ground plane depicted according to another embodiment of the present invention, source contact structures and source electrode line
Structural profile illustration；
Fig. 6 A is along part-structure sectional view depicted in tangent line S3 depicted in Fig. 1 I；
Fig. 6 B is along part-structure sectional view depicted in tangent line S4 depicted in Fig. 1 I；And
Fig. 7 is the part of vertical channel formula three dimensional NAND memory element depicted according to another embodiment of the present invention
Structure top view.
[symbol description]
10: multi-layer laminate structure
100: vertical channel formula three dimensional NAND flash element
101: substrate
102,112,122,132 and 142: silicon-containing conductive layer
103: insulating layer 104: serial
104a: accumulation layer 104b: channel layer
105: opening 106: serial selection line
107: source contact structures 107a: dielectric material layer
107b: conductive material 108: opening
109: hard mask layer 110: multilayer plug structure
110a, 110b, 110c and 110d: interlayer plug
113: concatenation metal wire 114: contact plunger
115: source electrode 116: bit line
117a, 117b, 117c and 117d: metal word lines
118: source electrode line 119: guide hole
200: 301 ground plane of three-dimensional storage element
303: insulating layer A: region
The distance between D1: two adjacent multilayer plug structures
The distance between D2: two adjacent source contact structures
Specific embodiment
The present invention provide a kind of memory component with and preparation method thereof, can reduce the overall resistivity of memory component with
Reduce signal propagation delay phenomenon caused by resistance and capacitor.In order to the above embodiment of the present invention and other purposes, spy
Advantage of seeking peace can be clearer and more comprehensible, and vertical channel formula three dimensional NAND flash element 100 be cited below particularly as preferred embodiment, and match
Institute's accompanying drawings are closed to elaborate.
But it must be noted that these specific case study on implementation and method, be not intended to limit the invention.The present invention still may be used
It is implemented using other features, element, method and parameter.The it is proposed of preferred embodiment is only of the invention to illustrate
Technical characteristic, the scope of the claims being not intended to limit the invention.Have usually intellectual in the technical field, it can basis
The description of following description is not departing from scope of the invention, makees impartial modification and variation.Different embodiments with
Among schema, identical element will be indicated with identical component symbol.
The method of production vertical channel formula three dimensional NAND flash element 100 includes the following steps: first in shape on substrate 101
At a multi-layer laminate structure 10.Figure 1A is please referred to, Figure 1A is that an embodiment according to the present invention is painted to be formed on the substrate 101
10 part-structure perspective view of multi-layer laminate structure.In the present embodiment, multi-layer laminate structure 10 includes multiple silicon-containing conductive layers
102,112,122,132 and 142 and multiple insulating layers 103.Wherein, silicon-containing conductive layer 102,112,122,132 and 142 and multiple
Insulating layer 103 is along Z-direction cross laminates heap in parallel to each other.
Among some embodiments of the present invention, silicon-containing conductive layer 102,112,122,132 and 142 preferably can be by polycrystalline
Silicon material is constituted；Insulating layer 103 can be preferably made of silica (silicon oxide) material.Although Figure 1A is drawn
The multi-layer laminate structure 10 shown only includes 5 layers of silicon-containing conductive layer 102,112,122,132 and 142 and 4 layer insulatings 103.But
It is only to illustrate, and among other embodiments, the quantity of silicon-containing conductive layer and insulating layer is not limited thereto.
Later, a plurality of serial 104 are formed and vertically wears silicon-containing conductive layer 102,112,122,132 and 142 and insulating layer
103.Figure 1B and Fig. 1 C is please referred to, Figure 1B is that the part-structure after forming a plurality of serial 104 in the structure for be shown in Figure 1A is saturating
View.Fig. 1 C is the structure top view according to depicted in Figure 1B.
Among one embodiment of the invention, each serial 104 all includes an an accumulation layer 104a and channel layer 104b.
Accumulation layer 104a, which can be, to be made of a silicon nitride (silicon nitride) layer, one silica layer and a silicon nitride layer
NON structure.Channel layer 104b is preferably polycrystalline silicon material.By these serial 104 and silicon-containing conductive layer 102,112,122,132
With 142 staggeredly, can define multiple storage units (cells) for being arranged as multiple row (rows) and multirow (columns).
Such as.Among some embodiments of the present invention, the arrangement mode of storage unit can be a matrix array
(matrix array).Among other embodiments of the invention, the arrangement mode of storage unit may be a honeycomb
Array (honeycomb array).It will be appreciated, however, that the embodiment of the present invention is not with the arrangement of this two kinds of storage units
Aspect is limited, any design specification (design rule) suitable for three-dimensional storage element, all without departing from the spiritual model of this case
It encloses.
A to Fig. 2 D referring to figure 2., Fig. 2A to Fig. 2 D be an embodiment according to the present invention be painted to be formed serial 104 portion
Division technique structural profile illustration.Serial 104 formation may include following step: first with etching technics in multilayer laminated knot
Multiple openings 105 are formed in structure 10 (including silicon-containing conductive layer 102,112,122,132 and 142 and insulating layer 103), to expose
A part of substrate 101 (as depicted in Fig. 2A).Then, in opening sidewalls and bottom deposit accumulation layer 104a, then at accumulation layer
The upper deposited semiconductor material of 104a, such as polysilicon or germanium, to form channel layer 104b (as depicted in Fig. 2 B).Later, logical
One layer of hard mask layer 109 is deposited on channel layer 104b, is used and is formed serial 104 (as depicted in Fig. 2 C) in 105 side walls that are open.
It is subsequent, then with anisotropic etching removal hard mask layer 109 and a part of accumulation layer 104a and channel layer 104b, and incite somebody to action
The substrate 101 of a part is exposed by opening 105.And it with polysilicon selective is formed on being exposed to outer substrate 101
Source electrode 115 makes serial 104 electric connections of substrate 101 with the ground plane as vertical channel formula three dimensional NAND flash element 100
(as depicted in Fig. 2 D).
In addition it in the technique of production serial 104, further includes and forms multiple source contact knots in multi-layer laminate structure 10
Structure 107.Wherein, these source contact structures 107 are to be arranged along the x axis, these is made serial 104 to be located in phase respectively
(Fig. 1 C is please referred to) between adjacent two source contact structures 107.
In the present embodiment, the generation type of source contact structures 107 is while forming opening 105, to etch work
Skill forms multiple shaped openings extended along Y direction in silicon conducting layer 102,112,122,132 and 142 and insulating layer 103
108, to expose a part of substrate 101.And then in formation dielectric material layer 107a on the side wall of shaped opening, and to lead
Electric material 107b, such as polysilicon fill up a shaped opening 108, to form multiple strip source contacts extended along Y direction
Structure 107.
Then, the silicon-containing conductive layer 102 of top layer is patterned, to form a plurality of serial selection in silicon-containing conductive layer 102
Line 106, and extend these serial selection lines 106 along the x axis.It please refers to Fig. 1 D and Fig. 1 E, Fig. 1 D and is shown in 1B
The part-structure perspective view after a plurality of serial selection line 106 is formed in structure.Fig. 1 E is in the structure according to depicted in Fig. 1 D
View.In some embodiments of the invention, the step of patterning silicon-containing conductive layer 102 of top layer, is included in siliceous conduction
A plurality of shallow ridges 111 is formed on layer 102, uses and the silicon-containing conductive layer 102 of top layer is partitioned into multiple bands, and then define more
Serial selection line 106.
Wherein, the corresponding a part of each serial selection line 106 these serial 104, and it is corresponding serial in this
104 electrical connections.It can be and arranged in a manner of matrix array for example, among some embodiments of the present invention, serial 104, and
Each serial selection line 106 can correspond to 5 to 10 rows serial 104, and with serial 104 electrical connection of this 5 to 10 row.In this hair
Among bright some embodiments, serial 104 be can be with the arrangement of honeycomb array manner, and each serial selection line 106 is then right
Answer 4 to 20 rows serial 104, and with serial 104 electrical connection of this 4 to 20 row.
And among the present embodiment, serial 104 be with the arrangement of honeycomb array manner, and each serial selection line 106 is then
Corresponding 4 rows serial 104, and with serial 104 electrical connection of this 4 row.By same serial selection line 106, this 4 row can be gone here and there
Serial 104 storage unit corresponding to row select line 106 is read simultaneously, and then service speed can be improved.It adds, serially
104 do not use metal gates, therefore are not required to space needed for reserving etching channel between serial selection line 106, can make to go here and there
Therefore (bandwidth) frequency bandwidth of row select line 106 expands.Vertical channel formula three dimensional NAND flash element can not only be increased
100 storage volume can also make the overall power consumption (power of vertical channel formula three dimensional NAND flash element 100
Consumption) decline, and then reduce interference when reading storage unit between consecutive storage unit.
It is subsequent.Multiple groups multilayer plug structure 110 is formed in multi-layer laminate structure 10, is arranged along the x axis, it will be more
A serial 104 are located in respectively between adjacent two multilayers plug structure 110.In addition, forming the same of multilayer plug structure 110
When, a contact plunger 114 generally can be also formed on each serial selection line 106.Please referring to Fig. 1 F and Fig. 1 G, Fig. 1 F is
Be shown in Fig. 1 D structure on form the part-structure perspective view after multiple groups multilayer plug structure 110 and contact plunger 114.
Fig. 1 G is the structure top view according to depicted in Fig. 1 F.
Among the present embodiment, each multilayer plug structure 110 include multiple interlayer plugs, such as 110a, 110b,
110c and 110d；And each interlayer plug 110a, 110b, 110c and 110d and silicon-containing conductive layer 112,122,132 and 142
The corresponding conducting of one of them.Wherein, interlayer plug 110a and the corresponding conducting of silicon-containing conductive layer 112；Interlayer plug 110b and siliceous
The corresponding conducting of conductive layer 122；Interlayer plug 110c and the corresponding conducting of silicon-containing conductive layer 132；And interlayer plug 110d and siliceous
The corresponding conducting of conductive layer 142.Plug 110a, 110b, 110c and 110d of same group of multilayer plug structure 110, are along the y axis
Arrangement, and form ladder-like (staircase) structure of straight line of a parallel Y direction.But straight line step structure not with
This is limited, among another embodiment of the invention, plug 110a, 110b, 110c of same group of multilayer plug structure 110 and
110d can be divided into multiple groups, such as 2 groups, arrange along the y axis, and form the straight line step structure of two parallel Y directions
(showing as depicted in fig. 3).
It is worth noting that, the deciding means of the distance between two adjacent multilayer plug structures 110 D1, are with reference to positioned at two
The overall resistance of silicon-containing conductive layer 112,122,132 and 142 between adjacent multilayer plug structure 110, and consider vertical logical
The operation efficiency of road formula three dimensional NAND flash element 100.In some embodiments of the invention, two adjacent multilayer plug structure
The distance between 110 D1, can be substantially between 500 microns to 50 microns.It is preferable then 100 microns can be substantially.
In addition, the deciding means of the distance between two adjacent source contact structures 107 D2, and with reference to positioned at two-phase neighbour source
The overall resistance of substrate 101 (ground plane) and vertical channel formula three dimensional NAND flash element between pole contact structures 107
100 operation efficiency.Among some embodiments of the present invention, the distance between adjacent two source contact structures 107 can be real
Matter is more than or equal to 20 microns (μm).
Although and it is worth noting that, in the aforementioned embodiment by two adjacent source contacts (for the sake of briefly describing)
The distance between structure 107 and two adjacent the distance between multilayer plug structures 110 are schematically shown as roughly the same.Also it is
It says, an one group of multilayer plug structure 110 of corresponding collocation of source contact structures 107.But source contact structures 107 and multilayer plug
The configuration of structure 110 is not limited thereto fixed.Among the other embodiment of the present invention, two adjacent source contact structures 107
The distance between and the distance between two adjacent multilayer plug structures 110 can be different.In other words, two adjacent multilayer plug
It may include more source contact structures 107 between structure 110.It is subsequent, a plurality of source electrode is formed above source contact structures 107
Line 118 extends source electrode line 118 along the y axis, and is electrically connected with source contact structures 107.And in serial selection line
106 top formed multiple bit lines 116, extend each bit line 116 along the y axis, and in same serial selection line 106
One serial 104 corresponding be electrically connected.Fig. 1 H is please referred to, Fig. 1 H is that a plurality of source electrode line 118 is formed in the structure for be shown in Fig. 1 G
With the structure top view after bit line 116.Among the present embodiment, source electrode line 118 is parallel with bit line 116, and the two and serial
Selection line 106 is directly handed over.
In some embodiments of the invention, source electrode line 118 and bit line 116 can be formed in identical or different metal
In online layer M1.Such as A and Fig. 4 B, Fig. 4 A are along part-structure depicted in tangent line S1 depicted in Fig. 1 H referring to figure 4.
Sectional view；Fig. 4 B is along part-structure sectional view depicted in tangent line S2 depicted in Fig. 1 H.Among the present embodiment, source electrode
Line 118 and bit line 116 are formed in identical metal layer in online layer M1.Each bit line 116 is then serial by being located at
104 and metal in guide hole 119 between online layer M1, corresponding with one serial 104 are electrically connected.
Although it is otherwise noted that being all using substrate 101 as ground plane in the foregoing embodiments
(grounding layer) makes serial 104 source electrode 115 pass through substrate 101 and source contact structures 107 and source electrode line 118
It is electrically connected.But the ground plane structure of vertical channel formula three dimensional NAND flash element 100 is not limited thereto.Referring to figure 5., scheme
5 be the part knot of ground plane 301 depicted according to another embodiment of the present invention, source contact structures 107 and source electrode line 118
Structure diagrammatic cross-section.
In the present embodiment, the structure of Fig. 5 is similar with the structure of Fig. 4 B, the difference is that ground plane 301, can be positioned at base
Another conductive material layer between plate 101 and silicon-containing conductive layer 142.Serial 104 source electrode 115 is by ground plane 301, source
Pole contact structures 107 and with source electrode line 118 be electrically connected.Wherein, between substrate 101 and ground plane 301 and ground plane 301
Between silicon-containing conductive layer 142, it is isolated respectively with an insulating layer 303.
Then, formed above multilayer plug structure 110, bit line 116 and source electrode line 118 a plurality of metal word lines 117a,
117b, 117c and 117d extend along the x axis, and keep each metal word lines 117a, 117b, 117c or 117d and conducting same
Multiple interlayer plug 110a, 110b, 110c or 110d of one silicon-containing conductive layer 112,122,132 or 142 are electrically connected.Separately
Outside, while forming metal word lines 117a, 117b, 117c and 117d, generally also will form concatenation metal wire 113, be used to
The contact plunger 114 for connecting serial selection line 106 is electrically connected.
Such as Fig. 1 I is please referred to, Fig. 1 I is that a plurality of metal word lines 117a, 117b, 117c are formed in the structure for be shown in Fig. 1 H
With the structure top view after 117d and concatenation metal wire 113.Among the present embodiment, metal word lines 117a is different from being located at
In group multilayer plug structure 110, and the multiple interlayer plug 110a for simultaneously turning on silicon-containing conductive layer 112 are electrically connected；Metal word
Line 117b from be located in different groups of multilayer plug structures 110, and simultaneously turn on multiple interlayer plug 110b of silicon-containing conductive layer 122
It is electrically connected；Metal word lines 117c from be located in different groups of multilayer plug structures 110, and simultaneously turn on silicon-containing conductive layer 132
Multiple interlayer plug 110c are electrically connected；Metal word lines 117c from be located in different groups of multilayer plug structures 110, and simultaneously turn on
Multiple interlayer plug 110c of silicon-containing conductive layer 132 are electrically connected.
And plug 110a, 110b, 110c and 110d of same group of multilayer plug structure 110, then it is ladder-like according to straight line
The arrangement of structure sequence, and correspond to each other simultaneously with metal word lines 117a, 117b, 117c and the 117d arranged according to sequence of positions
It is electrically connected.Such as among the present embodiment, plug 110a is corresponding and is electrically connected metal word lines 117a；Plug 110b is corresponding simultaneously
It is electrically connected metal word lines 117b；Plug 110c is corresponding and is electrically connected metal word lines 117c；Plug 110d is corresponding and electrically connects
Meet metal word lines 117d.In other words, the configuration of plug 110a, 110b, 110c and 110d of same group of multilayer plug structure 110,
Depending on the position of necessary complexed metal wordline 117a, 117b, 117c and 117d.In some embodiments of the invention, metal word
Spacing between line 117a, 117b, 117c and 117d is equal to each other.Therefore plug 110a in same group of multilayer plug structure 110,
The configuration of 110b, 110c and 110d can be equidistant configuration.
But among other embodiments of the invention, plug 110a, 110b in same group of multilayer plug structure 110,
The configuration of 110c and 110d can be Unequal distance configuration.Please referring to Fig. 6 A and Fig. 6 B, Fig. 6 A is along tangent line depicted in Fig. 1 I
Part-structure sectional view depicted in S3；Fig. 6 B is along part-structure sectional view depicted in tangent line S4 depicted in Fig. 1 I.
Among the present embodiment, since metal word lines 117a, 117b, 117c and 117d are and the concatenation metal that connect contact plunger 114
Line 113 is formed in identical metal in online layer M2, and extending direction having the same.In other words, metal wire is concatenated
113 be interspersed be arranged between metal word lines 117a, 117b, 117c and 117d.
Therefore, non-essential electrical property is generated with metal wire 113 is concatenated in order to avoid plug 110a, 110b, 110c and 110d
Connection, among the present embodiment, the distance between plug 110b and 110c of same group of multilayer plug structure 110 P2 can be more same
The distance between the plug 110a and 110b of group multilayer plug structure 110 the distance between P2 or plug 110c and 110d P3 long.
Wherein, distance P3 and P3 can be equal.
Among some embodiments of the present invention, and plug 110a, 110b, 110c in same group of multilayer plug structure 110
In the configuration of 110d, N number of unequal distance is at least had.Wherein N is equal to the plug with same group of multilayer plug structure 110
The quantity of the concatenation metal wire 113 (or being equal to serial selection line 106) of 110a, 110b, 110c and 110d interaction arrangement.It is subsequent again
It carries out multiple last part technologies (not being painted), i.e. the preparation of completion vertical channel formula three dimensional NAND flash element 100 (carrys out table with Fig. 1 I
Show).Due to, in an embodiment of the present invention, vertical channel formula three dimensional NAND flash element 100 be using silicon-containing conductive layer 112,
122,132 and 142 it is used as grid；And it is set by multilayer plug structure 110 and metal word lines 117a, 117b, 117c and 117
It sets, reduces the overall resistance of the grid of silicon-containing conductive layer 112,122,132 and 142, it is even up to identical with metal gates
Resistance value can reduce signal propagation delay phenomenon caused by grid resistance and capacitor.Therefore, using provided by the present invention vertical
Channel-type three dimensional NAND flash element 100, can be to avoid metal gate process, to vertical due to crossing plating etching or residual sacrificial layer
Adverse effect caused by channel-type three dimensional NAND flash element 100.It adds, vertical channel formula three dimensional NAND flash element
It does not need to form the channel for being used to etching sacrificial layer in multi-layer laminate structure 10 in 100 manufacturing process.Therefore, can subtract
The distance between few two adjacent serial selection lines 106, the frequency bandwidth of further expansion serial selection line 106, increase can accommodate
Serial 104 quantity expands volumes of storage space.
Fig. 7 is please referred to, Fig. 7 is the part of three-dimensional storage element 200 depicted according to another embodiment of the present invention
Structure top view.The structure vertical channel-type three dimensional NAND flash element 100 of three-dimensional storage element 200 is similar, and difference only exists
There is more multilayer plug structure 110 and source contact structures 107 in three-dimensional storage element 200.It is more for macroscopic
Layer plug structure 110 and the serial selection line 106 that each extends along the X direction are overlapped, and each is serially selected
Line 106 is partitioned into multiple regions A.In the present embodiment, each serial selection line 106 is partitioned by multilayer plug structure 110
At least ten region A.Wherein, a contact plunger 114 is configured on the A of each region, respectively via a concatenation metal wire 113
It is electrically connected in decoder (not being painted).
For the sake of for a clear description, Fig. 5 clipped element, such as metal word lines 117a, 117b, 117c and 117d, source
Polar curve 118, and be not painted.Have usually intellectual in the field, when can by preceding description content and referring to correlative type,
Understand the configuration of three-dimensional storage element 200.
According to above-described embodiment, the present invention is to provide a kind of memory component and preparation method thereof.It is deposited in three-dimensional
Multiple groups are formed in the multi-layer laminate structure of memory element along the multilayer plug structure of serial selection line setting arranged in parallel, by shape
It is serially located between two adjacent multilayer plug structures respectively at a plurality of in multi-layer laminate structure, and makes multilayer plug
Each interlayer plug that structure is included, respectively conducting corresponding with a silicon-containing conductive layer in multi-layer laminate structure.And with
Multiple interlayer plugs that same silicon-containing conductive layer is connected are electrically connected by metal word lines.Pass through multilayer plug structure and metal word lines
Connection, to reduce the overall resistivity of grid layer in three-dimensional storage element, to reduce caused by grid resistance and capacitor
Signal propagation delay phenomenon.Again since three-dimensional storage element is to be not required to be additionally formed as grid using siliceous conductive material
Metal gates can expand the frequency bandwidth of serial selection line, known technology be solved, because using caused by metal gate process
The problem of storage volume and process yields can not improve.
In some embodiments of the invention, further include formed in the multi-layer laminate structure of three-dimensional storage element it is multiple
The extending direction of source contact structures, parallel serial selection line is arranged, and will be formed in a plurality of string in multi-layer laminate structure
Row is located in respectively between two adjacent source contact plugs, and it is vertical along extend through multi-layer laminate structure and and electrical property of substrate
Connection.By the setting of source contact structures, the overall resistivity for reducing source electrode in three-dimensional storage element can reach, also to subtract
Signal propagation delay phenomenon caused by few source resistance and capacitor.
Although the present invention has been disclosed as a preferred embodiment, however, it is not to limit the invention.Skill belonging to the present invention
Has usually intellectual in art field, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Cause
This, protection scope of the present invention is subject to be defined depending on appended claims range.
Claims (9)
1. a kind of memory component, comprising:
Multiple silicon-containing conductive layers, vertical stack is on a substrate in parallel to each other；
A plurality of serial selection line is located above these silicon-containing conductive layers, and extends along a first direction；
It is a plurality of serially perpendicular to these silicon-containing conductive layers and these serial selection lines, and be electrically connected to these serial selection lines；
Multiple bit lines are located above these serial selection lines, and extend along a second direction, serially electrically connect with these respectively
It connects；
Multiple groups multilayer plug structure, is arranged along the first direction, these are serially located in these multilayer plugs respectively
Between the adjacent pairs of structure；Wherein, these each multilayer plug structures include multiple interlayer plugs, these each interlayer plugs with
The corresponding conducting of the one of these silicon-containing conductive layers；And
A plurality of metal word lines extend along the first direction；Wherein, these each metal word lines and be connected these silicon-containing conductive layers it
These interlayer plugs with one are electrically connected, and wherein these multilayer plug structures are Chong Die with these each serial selection lines, and
These each serial selection lines are partitioned into multiple regions；Wherein these each regions are to be concatenated by a contact plunger with one
Metal wire is electrically connected, and these concatenation metal wires are interspersed are arranged between these metal word lines.
2. memory component according to claim 1, wherein have between two these adjacent multilayer plug structures between
A distance between 500 microns to 50 microns.
3. memory component according to claim 1, wherein these plugs of these each multilayer plug structures along this
The arrangement of two directions, forms a step structure.
4. memory component according to claim 3, wherein these plugs of these each multilayer plug structures each other it
Between there is at least N kind difference spacing, wherein N is equal to the number of these serial selection lines.
5. memory component according to claim 1, further includes: multiple source contact structures are arranged along the first direction
Setting, is located in these serially respectively between the adjacent pairs of these source contact plugs.
6. memory component according to claim 5, wherein these each source contact structures are along the second direction
Extension in a strip shape, and vertical edge extends through these silicon-containing conductive layers, and connect with the electrical property of substrate.
7. memory component according to claim 5, further includes:
One ground plane, between these silicon-containing conductive layers and the substrate；And
Multiple source electrodes, each these are serially in electrical contact by these source electrode one of them and the ground plane；Wherein, each
These source contact structures and the ground plane are in electrical contact.
8. a kind of production method of memory component, comprising:
In the multiple silicon-containing conductive layers for forming vertical stack on a substrate and being parallel to each other；
It is formed and a plurality of serially vertically wears these silicon-containing conductive layers；
In forming a plurality of serial selection line in these silicon-containing conductive layers, and extend these serial selection lines along a first direction,
And it is electrically connected that corresponding these are serial；
Multiple groups multilayer plug structure is formed, is arranged along the first direction, these is serially located in these multilayers respectively
Between the adjacent pairs of plug structure；Wherein, these each multilayer plug structures include multiple interlayer plugs, these each interlayers are inserted
Fill in conducting corresponding with the one of these silicon-containing conductive layers；
It is online rectangular at multiple bit lines in these serial selections, extend these bit lines along a second direction, and with it is a plurality of these
It is serial to be electrically connected；And
A plurality of metal word lines are formed above these multilayer plug structures, extend these metal word lines along the first direction；Its
In, these each metal word lines and be connected these silicon-containing conductive layers with one these interlayer plugs be electrically connected, wherein this
A little multilayer plug structures are Chong Die with these each serial selection lines, and these each serial selection lines are partitioned into multiple regions；
Wherein these each regions are to concatenate metal wire with one by a contact plunger to be electrically connected, and these concatenation metal wires are to wear
Insert row is listed between these metal word lines.
9. the production method of memory component according to claim 8 further includes to form multiple source contact structures, edge should
First direction is arranged, and is located in these serially respectively between the adjacent pairs of these source contact plugs.
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| US10373904B2 (en) * | 2017-08-28 | 2019-08-06 | Micron Technology, Inc. | Semiconductor devices including capacitors, related electronic systems, and related methods |
| JP2020035926A (en) * | 2018-08-30 | 2020-03-05 | キオクシア株式会社 | Semiconductor storage device |
| CN114649345A (en) * | 2021-03-26 | 2022-06-21 | 长江存储科技有限责任公司 | Semiconductor device with a plurality of transistors |
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| CN102194793A (en) * | 2010-02-19 | 2011-09-21 | 三星电子株式会社 | Three-dimensional semiconductor device |
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| TWI490862B (en) * | 2011-01-19 | 2015-07-01 | Macronix Int Co Ltd | Memory architecture of 3d array with improved uniformity of bit line capacitances |
| KR20120136535A (en) * | 2011-06-09 | 2012-12-20 | 에스케이하이닉스 주식회사 | Semiconductor memory device |
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| CN102194793A (en) * | 2010-02-19 | 2011-09-21 | 三星电子株式会社 | Three-dimensional semiconductor device |
| CN102760739A (en) * | 2011-04-26 | 2012-10-31 | 爱思开海力士有限公司 | Semiconductor memory device and method of manufacturing the same |
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