KR20110013699A - Vertical channel type non-volatile memory device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A vertical channel type nonvolatile memory device and a method for manufacturing the same are provided to reduce the resistance of a word-line by patterning one word-line into a plurality of word-line patterns and connecting the word-line patterns to an identical metal wiring. CONSTITUTION: Multi-layered word-lines are stacked on a substrate. A word-line on each layer is patterned into multiple word-line patterns(WL00~WL03, WL10~WL13, WL20~WL23). The multi-layered word-lines are in contact with metal wirings(M0~M3) through a contact plug. The word-line on each layer is in connection with an identical metal wiring. A plurality of memory blocks(MB_0~MB_N) respectively includes a plurality of structures.

Description

Vertical channel type nonvolatile memory device and method of manufacturing the same {VERTICAL CHANNEL TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a vertical channel type nonvolatile memory device and a method of manufacturing the same.

A non-volatile memory device is a memory device in which stored data is retained even if power supply is interrupted. Recently, as the degree of integration of a memory device having a two-dimensional structure in which a memory device is manufactured in a single layer on a silicon substrate has reached a limit, a nonvolatile memory device having a three-dimensional structure in which memory cells are stacked vertically from a silicon substrate has been proposed. .

Hereinafter, a method of manufacturing a nonvolatile memory device having a three-dimensional structure and a problem thereof according to the prior art will be described in detail with reference to the accompanying drawings.

1A to 1C are perspective views illustrating a method of manufacturing a vertical channel type nonvolatile memory device according to the prior art. However, it should be noted that, for convenience of description, structures, such as a source region, a lower selection transistor, and an upper selection transistor, are omitted and are shown mainly in the memory cell.

As shown in FIG. 1A, a plurality of interlayer insulating films 11 and conductive films 12 are alternately formed on a substrate 10 on which desired substructures such as a source region, a bottom select transistor, and the like are formed.

Subsequently, the interlayer insulating film 11 and the conductive film 12 are etched to form a channel trench for exposing the surface of the substrate 10. Subsequently, after the charge blocking film, the charge trap film, and the tunnel insulating film (not shown) are formed on the inner wall of the channel trench, the channel film is embedded in the channel trench to form the channel CH. As a result, a plurality of memory cells MC0 to MC3 stacked along the channel CH are formed.

Subsequently, a plurality of interlayer insulating layers 11 and conductive layers 12 having a plurality of memory cells MC0 to MC3 are etched to perform a memory block separation process for separating the plurality of memory blocks MB0 and MB1, respectively. .

As shown in FIG. 1B, the interlayer insulating film 11 and the conductive film 12 of the plurality of memory blocks MB0 and MB1 are patterned stepwise to expose the surfaces of the plurality of conductive films 12, respectively. . As described above, the step of patterning the plurality of interlayer insulating films 11 and the conductive films 12 in a stepped manner is called a slimming process, which is a contact that is connected to the surfaces of the plurality of conductive films 12 in a subsequent process. In order to form a plug, it is a process of exposing the surface of the conductive film 12 of multiple layers. As a result, all of the conductive films 12 of a plurality of layers are exposed by each layer.

As illustrated in FIG. 1C, an insulating film (not shown) is formed on the entire structure of the resultant of the slimming process, and then etched to form contact holes for exposing the plurality of conductive films 12, respectively.

Subsequently, a plurality of contact plugs C0 to C3 connected to the plurality of conductive films 12 are formed by filling the conductive film in the contact hole. Subsequently, metal wires M0 to M3 respectively connected to the plurality of contact plugs C0 to C3 are formed.

2 is a plan view illustrating a chip configuration of a vertical channel type nonvolatile memory device according to the related art.

As shown, the chip includes a cell region CELL and a peripheral circuit region PERI, wherein a plurality of memory blocks MB_0 to MB_N are formed in the cell region CELL, and X is formed in the peripheral circuit region PERI. A decoder (X-DECODER) is formed.

As described above, the plurality of memory blocks MB_0 to MB_N are patterned stepwise by a slimming process, and the conductive film of each layer is transferred to the X-decoder X-DECODER by the plurality of metal wires M0 to M3. Connected.

As described above, the plurality of conductive layers, that is, the plurality of word lines WL0 to WL3 are connected to the plurality of metal lines M0 to M3, respectively, so that the plurality of word lines WL0 to WL3 are driven by driving the memory elements. Each input voltage can be applied to

According to the related art as described above, after the multilayer interlayer insulating film 11 and the conductive film 12 are alternately deposited on the substrate 10, the charge blocking film and the charge trap film for forming the memory cell MC Since the tunnel film and the channel film are formed, there is a problem that the material of the conductive film 12 is limited to the polysilicon film. That is, due to the characteristics of the process, since the word lines WL0 to WL3 made of a low resistance material such as a metal film cannot be formed, the sheet resistance Rs of the word lines WL0 to WL3 increases.

In addition, since an input voltage (for example, a program voltage) is applied and transmitted only through one side of the word lines WL0 to WL3, a voltage gradually decreases in the process of applying the input voltage. In addition, a delay occurs due to the transmission of the input voltage.

As a result, not only the program / erase speed of the memory device is lowered, but also the program / lead time is increased, resulting in a problem that the characteristics of the memory device are degraded.

The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a vertical channel type nonvolatile memory device and a method of manufacturing the same, which are suitable for improving the driving speed of a memory device by reducing the resistance of a word line.

In order to achieve the above object, the present invention provides a vertical channel type nonvolatile memory device including a plurality of memory cells stacked along a channel protruding from a substrate, comprising: a plurality of word lines stacked on a substrate; And a plurality of metal wires respectively connected to the word lines of the plurality of layers, wherein the word lines of each layer are connected to the same metal wire a plurality of times.

In addition, the present invention provides a vertical channel type nonvolatile memory device including a plurality of memory cells stacked along a channel protruding from a substrate, comprising: a plurality of word lines stacked on a substrate; And a plurality of metal lines respectively connected to the plurality of word lines, wherein each word line includes a plurality of word line patterns, and the plurality of word line patterns are connected to the same metal line for each layer. It features.

In addition, the present invention provides a method for manufacturing a vertical channel type nonvolatile memory device including a plurality of memory cells stacked along a channel protruding from a substrate, the method comprising: alternately forming a plurality of interlayer insulating films and conductive films on a substrate; And a plurality of metal wires connected to the conductive films of the plurality of layers, respectively, and connected to the conductive film of one layer a plurality of times.

In addition, the present invention provides a method of manufacturing a vertical channel type nonvolatile memory device including a plurality of memory cells stacked along a channel protruding from a substrate, the method comprising: alternately forming a plurality of interlayer insulating films and conductive films on a substrate; Etching the plurality of interlayer insulating layers and conductive layers to form a plurality of structures including a plurality of conductive layer patterns; And forming a plurality of metal wires connected to the plurality of conductive films, respectively, such that a plurality of conductive film patterns formed on each layer are connected to the same metal wires for each layer.

According to the present invention, the driving speed of a memory element can be improved by connecting a plurality of word lines stacked on a substrate to the same metal wiring a plurality of times. In addition, after patterning one word line into a plurality of word line patterns, the plurality of word line patterns may be connected to the same metal line for each layer, thereby reducing the resistance of the word lines to improve the driving speed of the memory device.

In the following, the most preferred embodiment of the present invention is described. In the drawings, thickness and spacing are expressed for convenience of description and may be exaggerated compared to actual physical thickness. In describing the present invention, well-known structures irrelevant to the gist of the present invention may be omitted. In adding reference numerals to the components of each drawing, it should be noted that the same components as much as possible, even if displayed on different drawings.

3A and 3B illustrate a structure and a manufacturing method of a vertical channel type nonvolatile memory device according to a first embodiment of the present invention.

3A is a diagram illustrating a chip configuration of a vertical channel type nonvolatile memory device according to a first embodiment of the present invention. As shown, the vertical channel type nonvolatile memory device according to the first embodiment of the present invention includes a plurality of metal lines connected to a plurality of word lines WL0 to WL3 and a plurality of word lines stacked on a substrate, respectively. (M0 to M3), and the word lines WL0 to WL3 of each layer are connected to the same metal wirings M0 to M3 a plurality of times.

The word lines WL0 to WL3 of the plurality of layers are connected to the metal lines M0 to M3 through contact plugs. The contact plugs are formed at predetermined intervals in the word lines WL0 to WL3 of each layer, thereby providing the words of each layer. The lines WL0 to WL3 may be connected to the same metal wires M0 to M3 a plurality of times.

Here, the number of times that the word lines WL0 to WL3 of each layer are connected to the same metal wirings M0 to M3, that is, the number of contact plugs connected to the word lines WL0 to WL3 of each layer is wordline ( It is preferable to consider the sheet resistance of WL0 to WL3 and the driving speed of the memory element. For example, as the sheet resistance of the word line increases, it is desirable to increase the number of times of contact with the metal wiring, that is, the number of contact plugs.

In the drawing, as an example, the word lines WL0 to WL3 of each layer are connected to the same metal line twice. As described above, both sidewalls of the plurality of memory blocks MB_0 to MB_N are patterned stepwise by a slimming process, and word lines of each layer using the stepped sidewalls of both ends of the memory blocks MB_0 to MB_N. It is preferable to form a plurality of contact plugs connected to WL0 to WL3.

According to the present invention as described above, by connecting the word lines (WL0 ~ WL3) of each layer with the same metal wiring (M0 ~ M3) a plurality of times, it is possible to quickly apply the input voltage through the metal wiring (M0 ~ M3). have. That is, the limitations due to the sheet resistances of the word lines WL0 to WL3 may be overcome, and the driving speed of the memory device may be improved.

3B is a perspective view illustrating a structure of a vertical channel type nonvolatile memory device according to a first embodiment of the present invention. However, in this drawing, only a plurality of word lines, an interlayer insulating film, a contact plug, and a metal wiring, which are stacked on a substrate, are illustrated for convenience of description, and other structures and material films are omitted.

As shown, a plurality of interlayer insulating films 31 and conductive films 32 are alternately formed on the substrate 30. Here, the conductive layer 32 is to form the word lines WL0 to WL3 described above and may include, for example, a polysilicon layer. In addition, the interlayer insulating layer 31 is used to separate the plurality of conductive layers 32, that is, the plurality of word lines WL0 to WL3 from each other, and may include, for example, an oxide layer.

Subsequently, a memory block separation process of etching the plurality of interlayer insulating layers 31 and the conductive layers 32 to separate the plurality of memory blocks is performed. In this embodiment, the memory block separation process is not separately illustrated.

Subsequently, a plurality of layers of the interlayer insulating film 31 and the conductive film 32 are etched to expose the surfaces of the plurality of conductive films 32 a plurality of times, respectively. In the drawing, as an example, a case in which the surface of the plurality of conductive films 32 are exposed twice at both ends through a slimming process of stepwise patterning both sidewalls of the plurality of memory blocks MB_0 to MB_N is shown. It is shown.

Subsequently, an insulating film (not shown) is formed on the entire structure of the resultant patterned staircase, and the insulating film is etched to form contact holes for exposing the surfaces of the plurality of conductive films 32, respectively. Subsequently, a plurality of contact plugs C0 to C3 connected to the plurality of conductive films 32 are formed by filling a conductive film in the contact hole.

Subsequently, metal wirings M0 to M3 connected to the conductive films 32 of a plurality of layers but connected to the conductive film 32 of one layer a plurality of times are formed. Here, the conductive layers 32 of each layer are connected to the same metal wiring a plurality of times through the plurality of contact plugs C0 to C3.

For example, the first conductive film 32 deposited on the substrate 30 is connected to the same metal wiring M0 twice through two contact plugs CO. That is, since one end and the other end of the word line W0 are connected to the metal line M0 by the contact plug C0, the plurality of memory cells belonging to the page PAGE connected to the word line W0 may be metal. The input voltage is applied at about the same time through the wiring M0.

4A and 4B illustrate a structure and a manufacturing method of a vertical channel type nonvolatile memory device according to a second embodiment of the present invention.

4A is a diagram illustrating a chip configuration of a vertical channel type nonvolatile memory device according to a second embodiment of the present invention. As shown, the vertical channel type nonvolatile memory device according to the second embodiment of the present invention includes a plurality of metal lines connected to a plurality of word lines WL0 to WL3 and a plurality of word lines stacked on a substrate, respectively. (M0 to M3), wherein the word lines WL0 to WL3 of each layer are patterned into a plurality of word line patterns WL00 to WL03, WL10 to WL13, and WL20 to WL23, respectively, so that the same metal lines M0 to M3 are formed for each layer. M3).

The plurality of memory blocks MB_0 to MB_N each include a plurality of structures A0 to A2. Here, the structures A0 to A2 are formed by alternately stacking a plurality of word line patterns and an interlayer insulating layer, and are intended to reduce the resistance of the word lines by reducing the area of the word lines.

The number of structures A0 to A2 included in one memory block MB_0 to MB_N may be determined in consideration of the area of each word line pattern WL00 to WL23, that is, the resistance of the word line. In the drawing, as an example, one memory block MB includes three structures A0 to A2, but this is for convenience of description and the present invention is not limited thereto. .

At this time, in the etching process for separating the plurality of structures A0 to A2, the word lines WL0 to WL3 of each layer are patterned into the plurality of word line patterns WL00 to WL23. As described above, by patterning the word lines WL0 to WL3 of each layer into a plurality of word line patterns WL00 to WL03, WL10 to WL13, and WL20 to WL23, the resistance of the word lines can be reduced as compared with the conventional art.

For example, the first wordline deposited on the substrate is patterned into three wordline patterns WL00, WL10, WL20. That is, the plurality of structures A0 to A2 each include word line patterns WL00 to WL23, and the word line patterns WL00, WL10, WL20 / WL01, WL11, WL21 / WL02, WL12, and WL22 / are formed on the same layer. WL03, WL13, and WL23 are connected to the same metal wiring (M0 / M1 / M2 / M3).

The plurality of word line patterns WL00 to WL23 are connected to the same metal wirings M0 to M3 through layers by contact plugs, and the word line patterns WL00 to WL23 of the respective layers of the plurality of structures A0 to A2. By forming a plurality of contact plugs to be connected, the plurality of word line patterns WL00 to WL23 may be connected to the same metal wires M0 to M3 for each layer.

According to the present invention as described above, the surface resistance of the word line can be reduced by patterning the word lines WL0 to WL3 of each layer into a plurality of word line patterns WL00 to WL23. In addition, the metal lines M0 to M3 are formed by a strapping method of connecting the word line patterns WL00 to WL03, WL10 to WL13, and WL20 to WL23 formed on the same layer to the same metal lines M0 to M3. The input voltage may be applied to the plurality of word line patterns WL00 to WL03, WL10 to WL13, and WL20 to WL23 at about the same time. That is, not only the sheet resistance of the word line is reduced, but also the driving speed of the memory device can be improved.

4B is a perspective view illustrating a structure of a vertical channel type nonvolatile memory device according to a second embodiment of the present invention. However, in the drawings, only a plurality of word lines and interlayer insulating films, contact plugs, and metal wirings stacked on the substrate are shown for convenience of description, and other structures and material films are omitted.

As shown, a plurality of interlayer insulating films 41 and conductive films 42 are alternately formed on the substrate 40. The conductive layer 42 is formed to form the word lines WL0 to WL3 described above, and may include, for example, a polysilicon layer. In addition, the interlayer insulating layer 41 is used to separate the plurality of conductive layers 42, that is, the plurality of word lines WL0 to WL3 from each other, and may include, for example, an oxide layer.

Subsequently, the plurality of interlayer insulating layers 41 and 42 are etched to form a plurality of structures A0 to A2 including a plurality of conductive layer patterns, that is, word line patterns. The forming of the plurality of structures A0 to A2 may be performed through a conventional memory block separation process. In the drawing, the plurality of conductive film patterns are shown by the reference numerals "WL00 to WL03, WL10 to WL13, WL20 to WL23" in order to distinguish the structures according to the structures A0 to A2 and layers (0 to 3).

In the drawing, as an example, one memory block includes three structures A0 to A2. Accordingly, the conductive layers 42 of each layer may have three conductive layer patterns. Is patterned. For example, the first conductive layer 42, that is, the word line WL0, deposited on the substrate 40 is patterned into three word line patterns WL00 to WL02.

Subsequently, sidewalls of the plurality of structures A0 to A3 are patterned stepwise to expose surfaces of the plurality of conductive layer patterns WL00 to WL03, WL10 to WL13, and WL20 to WL23, respectively. In the drawing, as an example, a case of patterning both sidewalls of the plurality of structures A0 to A3 in a stepped manner, but only one sidewall of the structures A0 to A3 may be patterned.

Subsequently, an insulating film (not shown) is formed on the entire structure of the resultant patterned staircase, and the insulating film is etched to form contact holes for exposing the surfaces of the plurality of conductive films 42, respectively. Subsequently, a plurality of contact plugs C0 to C3 connected to the plurality of conductive films 42 are formed by filling a conductive film in the contact hole.

Subsequently, a plurality of metal lines may be connected to the plurality of conductive layers 42, respectively, such that the plurality of conductive layer patterns WL00 to WL03, WL10 to WL13, and WL20 to WL23 are connected to the same metal lines M0 to M3 for each layer. (M0 to M3) are formed. Here, the conductive layer patterns WL00 to WL03, WL10 to WL13, and WL20 to WL23 of each layer are connected to the same metal wirings M0 to M3 through the plurality of contact plugs C0 to C3.

For example, the first conductive layer 42 deposited on the substrate 40 is patterned into three conductive layer patterns WL00, WL10, and WL20, and two conductive layer patterns WL00, WL10, WL20 is connected to the same metal wiring M0. That is, by reducing the word line resistance by patterning the word lines of each layer into a plurality of word line patterns, the driving speed of the memory device can be improved by applying an input voltage to the plurality of word line patterns at substantially the same time through the metal wiring. have.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1C are cross-sectional views illustrating a method of manufacturing a vertical channel type nonvolatile memory device according to the prior art.

2 is a plan view showing a chip configuration of a vertical channel type nonvolatile memory device according to the prior art.

3A and 3B illustrate a structure and a manufacturing method of a vertical channel type nonvolatile memory device according to a first embodiment of the present invention.

4A and 4B illustrate a structure and a manufacturing method of a vertical channel type nonvolatile memory device according to a second embodiment of the present invention.

[Description of Symbols for Main Parts of Drawing]

30, 40 substrate 31, 41 interlayer insulating film

32,42: conductive film

Claims (15)

In the vertical channel type nonvolatile memory device including a plurality of memory cells stacked along a channel protruding from the substrate, A plurality of word lines stacked on the substrate; And A plurality of metal wires respectively connected to the plurality of word lines; ≪ / RTI > The word lines of each layer are connected to the same metal wiring multiple times Vertical channel type nonvolatile memory device. The method of claim 1, The plurality of word lines, Alternately stacked with a plurality of interlayer insulating films on the substrate, and patterned stepwise to expose the surface of the plurality of word lines a plurality of times, respectively. Vertical channel type nonvolatile memory device. The method of claim 1, A plurality of contact plugs connected to the word lines of the plurality of layers to connect the word lines of each layer to the same metal line a plurality of times; Vertical channel type nonvolatile memory device further comprising. In the vertical channel type nonvolatile memory device including a plurality of memory cells stacked along a channel protruding from the substrate, A plurality of word lines stacked on the substrate; And A plurality of metal wires respectively connected to the plurality of word lines; ≪ / RTI > Word lines in each layer It includes a plurality of word line patterns, the plurality of word line patterns are connected to the same metal line for each layer Vertical channel type nonvolatile memory device. The method of claim 4, wherein The plurality of structures in which the plurality of word line patterns and the plurality of interlayer insulating layers are alternately stacked Vertical channel type nonvolatile memory device further comprising. The method of claim 5, The plurality of structures, Stepped patterned to expose surfaces of the plurality of wordline patterns, respectively Vertical channel type nonvolatile memory device. The method of claim 5, The plurality of structures constitute one memory block. Vertical channel type nonvolatile memory device. The method of claim 4, wherein A plurality of contact plugs connected to the plurality of word line patterns to connect the plurality of word line patterns with the same metal line for each layer; Vertical channel type nonvolatile memory device further comprising. In the vertical channel type nonvolatile memory device manufacturing method comprising a plurality of memory cells stacked along a channel protruding from the substrate, Alternately forming a plurality of interlayer insulating films and conductive films on the substrate; Forming a plurality of metal wires connected to the conductive films of the plurality of layers, respectively, and connected to the conductive film of one layer a plurality of times. Vertical channel type nonvolatile memory device manufacturing method comprising a. The method of claim 9, After the forming of the plurality of interlayer insulating films and conductive films, Patterning the plurality of interlayer insulating films and the conductive films in a stepped manner such that the surfaces of the plurality of conductive films are each exposed a plurality of times; Forming an insulating film on the entire structure of the resultant patterned step; Etching the insulating film to form contact holes exposing surfaces of the plurality of conductive films, respectively; And Filling a conductive film in the contact hole to form a plurality of contact plugs respectively connected to the plurality of conductive films; The vertical channel type nonvolatile memory device manufacturing method further comprising. The method of claim 10, The conductive film of each layer, Connected to the same metal wiring a plurality of times by the plurality of contact plugs. A vertical channel type nonvolatile memory device manufacturing method. In the vertical channel type nonvolatile memory device manufacturing method comprising a plurality of memory cells stacked along a channel protruding from the substrate, Alternately forming a plurality of interlayer insulating films and conductive films on the substrate; Etching the plurality of interlayer insulating layers and conductive layers to form a plurality of structures including a plurality of conductive layer patterns; And Forming a plurality of metal wires connected to the plurality of conductive films, respectively, such that the plurality of conductive film patterns are connected to the same metal wires for each layer; Vertical channel type nonvolatile memory device manufacturing method comprising a. 13. The method of claim 12, After forming the plurality of structures, Stepwise patterning sidewalls of the plurality of structures such that surfaces of the plurality of conductive layer patterns are exposed; Forming an insulating film on the entire structure of the step patterned resultant; Etching the insulating film to form contact holes exposing the plurality of conductive film patterns, respectively; And Filling a conductive layer in the contact hole to form a plurality of contact plugs respectively connected to the plurality of conductive layer patterns The vertical channel type nonvolatile memory device manufacturing method further comprising. The method of claim 13, The plurality of conductive film patterns formed in the respective layers, The plurality of contact plugs are connected to the same metal wiring for each layer. A vertical channel type nonvolatile memory device manufacturing method. 13. The method of claim 12, The plurality of structures constitute one memory block. A vertical channel type nonvolatile memory device manufacturing method.

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