TW201637243A - Package substrate - Google Patents

Abstract

A package substrate is provided, including a dielectric structure having first and second dielectric portions, and a circuit layer disposed on the dielectric structure. The first dielectric portion has a different coefficient of thermal expansion than that of the second dielectric portion which can be used to balance the difference of the thermal expansion coefficient between the package substrate and the chip to thereby minimize the degree of package warpage.

Description

Package substrate

The invention relates to a package substrate, in particular to a package substrate used in a semiconductor package process.

In the development of semiconductor packaging, the long-term use of a lead frame as a carrier for carrying a wafer is mainly due to its low manufacturing cost and high reliability. However, with the rapid development of the electronics industry, electronic products tend to be light and thin in terms of type, and in terms of functions, they are oriented toward high-performance, high-function, and high-speed research and development. Therefore, in order to satisfy the high integration and miniaturization requirements of the semiconductor device, the lead frame is gradually replaced by a package substrate having a high density and fine pitch line in the packaging process.

As shown in FIG. 1A, the conventional package substrate 1 includes a dielectric structure 10, a first wiring layer 11 and a second wiring layer 12 disposed on the dielectric structure 10, and the dielectric structure 10 has a core layer 100. And a plurality of first dielectric layers 101 and a plurality of second dielectric layers 102 respectively disposed on opposite sides of the core layer 100.

In the packaging process, the semiconductor wafer 13 is disposed on the first dielectric layer 101 and electrically connected to the first line by wire bonding (or flip chip). The layer 11 is then coated with the encapsulant 14 to form a package.

However, the thickness of the conventional package substrate 1 is extremely thin and presents a full-faceted surface pattern in the process, and the materials and thicknesses of the first and second dielectric layers 101, 102 are the same, so in the packaging process, the package substrate 1 in the temperature cycle, the semiconductor wafer 13 (or the encapsulant 14) is likely to have a thermal expansion coefficient difference (CTE Mismatch), so that the package substrate 1 is prone to warpage, as above Case (dotted outline shown in Fig. 1A) or recessed condition (dashed outline of package substrate 1' shown in Fig. 1B), resulting in poor planarity of the package, so that when subsequently placed on the board , the problem of non-sticking (Non wetting) will occur, and the electrical connection will be poor.

Furthermore, the warpage also causes the semiconductor wafer 13 to be chipped, resulting in a decrease in product yield.

Further, if the thickness of the dielectric layer is increased, the warpage can be slowed down, but the thickness of the package substrate 1 is increased, so that it does not meet the requirements of lightness, thinness, and shortness.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a difficult problem to be overcome in the industry.

The present invention provides a package substrate, comprising: a dielectric structure, comprising a first dielectric portion and a second dielectric portion, wherein the first dielectric portion is thermally expanded The coefficient is different from the thermal expansion coefficient of the second dielectric portion; and the wiring layer is disposed on the dielectric structure.

In the above package substrate, the first dielectric portion has a plurality of first dielectric layers. For example, the thermal expansion coefficients of the first dielectric layers are the same or different; or the thickness of each of the first dielectric layers is equal or unequal.

In the above package substrate, the second dielectric portion has a plurality of second dielectric layers. For example, each of the second dielectric layers has the same or different coefficients of thermal expansion; or each of the second dielectric layers has the same or unequal thickness. Alternatively, in the second dielectric layers, the second dielectric layer farthest from the first dielectric portion has a thermal expansion coefficient smaller than that of the other second dielectric layers.

In the foregoing package substrate, the thickness of the first dielectric portion is equal to or not equal to the thickness of the second dielectric portion.

In the above package substrate, the first dielectric portion is adjacent to the second dielectric portion.

In the package substrate, the core layer is further included between the first dielectric portion and the second dielectric portion.

In the foregoing package substrate, an insulating protective layer is further included on the dielectric structure and the circuit layer is exposed.

As can be seen from the above, the package substrate of the present invention is mainly characterized in that the thermal expansion coefficient of the first dielectric portion is different from the thermal expansion coefficient of the second dielectric portion, so that the package substrate is used in the packaging process compared to the prior art. During the temperature cycle, the first and second dielectric portions have different amounts of expansion and contraction, thereby balancing the difference in thermal expansion coefficient between the package substrate and the wafer (or the encapsulant) to reduce the deformation of the package substrate.

1,1',2,2',3,4‧‧‧Package substrate

10,20,20’,30,40‧‧‧ dielectric structure

100,400‧‧‧ core layer

101, 301a, 401a, 401b‧‧‧ first dielectric layer

102,302a,402a,402b‧‧‧second dielectric layer

11, 21‧‧‧ first circuit layer

12,22‧‧‧second circuit layer

13‧‧‧Semiconductor wafer

14‧‧‧Package colloid

20a, 30a‧‧‧ first side

20b, 30b‧‧‧ second side

200‧‧‧conductive blind hole

201, 201', 301, 401‧‧‧ First Dielectric Department

202,202’, 302, 402‧‧‧Second Dielectric Department

33‧‧‧Electronic components

330‧‧‧Electrical bumps

34a‧‧‧First insulation protection layer

34b‧‧‧Second insulation protection layer

35‧‧‧Conducting components

400a‧‧‧ first surface

400b‧‧‧second surface

t,d,T,D,T',D',h1,h2,h2'‧‧‧ thickness

1A is a schematic cross-sectional view of a conventional semiconductor package; 1B is a schematic cross-sectional view of a conventional package substrate; FIG. 2 is a cross-sectional view showing a first embodiment of the package substrate of the present invention; and FIG. 2' is a cross-sectional view showing a second embodiment of the package substrate of the present invention; FIG. 3 is a cross-sectional view showing a third embodiment of the package substrate of the present invention; and FIG. 4 is a cross-sectional view showing a fourth embodiment of the package substrate of the present invention.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2 is a schematic cross-sectional view showing a first embodiment of the package substrate 2 of the present invention.

As shown in FIG. 2, the package substrate 2 is a coreless state including a dielectric structure 20, a first wiring layer 21, and a second wiring layer 22.

The dielectric structure 20 has a first side 20a and a second side 20b opposite to each other, and the dielectric structure 20 includes a pair of first dielectric portions 201 and a pair of second sides 20b that should be on the first side 20a. The second dielectric portion 202, wherein the first dielectric portion 201 has a thermal expansion coefficient (for example, 5 ppm/° C.) greater than a thermal expansion coefficient of the second dielectric portion 202 (for example, 1.8 ppm/° C.).

The first circuit layer 21 is disposed on the first dielectric portion 201.

The second circuit layer 22 is disposed on the second dielectric portion 202, and the first circuit layer 21 and the second circuit layer 22 are electrically connected by the conductive blind vias 200.

In this embodiment, the first dielectric portion 201 is a single dielectric layer, and the second dielectric portion 202 is a single dielectric layer, that is, the package substrate 2 has two dielectric layers, and the The first dielectric portion 201 is adjacent to the second dielectric portion 202.

Moreover, the surface of the first dielectric portion 201 is the surface of the first side 20a, and the surface of the second dielectric portion 202 is the surface of the second side 20b.

In addition, the thickness t of the first dielectric portion 201 is equal to the thickness d of the second dielectric portion 202. However, in other embodiments, the thickness of the first dielectric portion 201 may not be equal to the second dielectric portion 202. thickness.

Therefore, the package substrate 2 of the embodiment is provided by the first dielectric portion 201 The thermal expansion coefficient is greater than the thermal expansion coefficient of the second dielectric portion 202. Therefore, during the packaging process, the first and second dielectric portions 201, 202 are different in expansion and contraction during the temperature cycling, thereby balancing the package substrate. 2 The difference in thermal expansion coefficient between the semiconductor wafer (or the encapsulant) causes the package substrate 2 to be deformed by a convex warp as shown in FIG. 1A by 5% to 50%.

On the other hand, if the thermal expansion coefficient of the first dielectric portion 201 is smaller than the thermal expansion coefficient of the second dielectric portion 202, the package substrate 2 can be deformed by a concave warp as shown in FIG. 1B. Reduce 5% to 50%.

The second drawing is a schematic cross-sectional view showing a second embodiment of the package substrate 2' of the present invention. The difference between this embodiment and the first embodiment lies in the configuration of the dielectric structure 20', and the other configurations are substantially the same, so that the differences will be described in detail below, and the same points will not be described again.

As shown in FIG. 2', the package substrate 2' is a coreless layer, and the thermal expansion coefficient (eg, 5 ppm/° C.) of the first dielectric portion 201' is greater than the thermal expansion of the second dielectric portion 202'. Coefficient (eg 1.8ppm/°C).

In this embodiment, the first dielectric portion 201' is a two-layer dielectric layer, and the second dielectric portion 202' is a single dielectric layer, that is, the package substrate 2' has three dielectric layers. And the first dielectric portion 201' is pressed adjacent to the second dielectric portion 202'.

Furthermore, the thickness of each dielectric layer of the first dielectric portion 201' may or may not be equal to the thickness of the second dielectric portion 202'.

Moreover, each of the dielectric layers of the first dielectric portion 201' has the same thermal expansion coefficient (e.g., 5 ppm/°C); in other embodiments, the first dielectric portion 201' Each of the dielectric layers may have a different thermal expansion coefficient, but is greater than a thermal expansion coefficient of the second dielectric portion 202'.

Therefore, the package substrate 2 ′ of the embodiment has a thermal expansion coefficient of the first dielectric portion 201 ′ that is smaller than a thermal expansion coefficient of the second dielectric portion 202 ′, so that the package substrate 2 ′ is at a temperature during the packaging process. During the cycle, the first and second dielectric portions 201', 202' have different amounts of expansion and contraction, thereby balancing the difference in thermal expansion coefficient between the package substrate 2' and the semiconductor wafer (or encapsulant), so that the package substrate 2' The amount of deformation of the overhang warp as shown in Fig. 1A can be reduced by 5% to 50%.

Fig. 3 is a schematic cross-sectional view showing a third embodiment of the package substrate 3 of the present invention. The difference between this embodiment and the second embodiment lies in the configuration of the dielectric structure 30, and the other configurations are substantially the same, so the differences will be described in detail below, and the same points will not be described again.

As shown in FIG. 3, the package substrate 3 has a coreless layer, the first dielectric portion 301 has a plurality of first dielectric layers 301a, and the second dielectric portion 302 has a plurality of second dielectric layers. 302a, that is, the package substrate 3 has four dielectric layers, and the thickness T of the first dielectric portion 301 is equal to the thickness D of the second dielectric portion 302.

In this embodiment, each of the first dielectric layers 301a has the same thermal expansion coefficient (for example, 5 ppm/° C.), and each of the second dielectric layers 302a has the same thermal expansion coefficient (eg, 1.8 ppm/° C.). The thermal expansion coefficient of the first dielectric portion 301 is greater than the thermal expansion coefficient of the second dielectric portion 302.

Furthermore, the thickness of each of the first dielectric layers 301a may be the same (all 30um) or different, and the thickness of each of the second dielectric layers 302a may be the same (both 30um) or not the same.

Therefore, the package substrate 3 of the present embodiment has a thermal expansion coefficient of the first dielectric portion 301 greater than a thermal expansion coefficient of the second dielectric portion 302. Therefore, during the packaging process, the package substrate 3 is subjected to temperature cycling. The amount of expansion and contraction of the first and second dielectric portions 301, 302 is different, thereby balancing the difference in thermal expansion coefficient between the package substrate 3 and the electronic component 33 (or the encapsulant) to be described later, so that the package substrate 3 is generated as shown in FIG. 1A. The amount of deformation of the convex warp can be reduced by 5% to 50%.

Further, as is apparent from the first to third embodiments, if the package substrates 2, 2', 3 are in a coreless state, the number of dielectric layers may be singular or even.

Fig. 4 is a schematic cross-sectional view showing a fourth embodiment of the package substrate 4 of the present invention. The difference between this embodiment and the third embodiment lies in the configuration of the dielectric structure 40, and the other configurations are substantially the same, so the differences will be described in detail below, and the same points will not be described again.

As shown in FIG. 4, the package substrate 4 has a core layer. Therefore, the package substrate 4 further includes a core layer 400 sandwiched between the first dielectric portion 401 and the second portion. Between the dielectric portions 402, that is, the core layer 400 has a first surface 400a and a second surface 400b. The first dielectric portion 401 is disposed on the first surface 400a, and the second dielectric portion 402 is disposed. On the second surface 400b.

In this embodiment, the first dielectric portion 401 has a plurality of first dielectric layers 401a, 401b, and the second dielectric portion 402 has a plurality of second dielectric layers 402a, 402b.

Furthermore, the thermal expansion coefficients of the first dielectric layers 401a, 401b are uniform Same as, for example, 5ppm/°C.

Moreover, the thermal expansion coefficients of the second dielectric layers 402a, 402b are different. For example, the second dielectric layer 402b farthest from the first dielectric portion 401 (or farthest from the core layer 400, ie, the outermost side) has a thermal expansion coefficient (eg, 1.8 ppm/° C.) smaller than the other second dielectrics. The coefficient of thermal expansion of layer 402a (e.g., 5 ppm / ° C).

In addition, the thickness T' of the first dielectric portion 401 is different from the thickness D' of the second dielectric portion 402. For example, each of the first dielectric layers 401a, 401b has a thickness h1 of 30 um, and the inner second dielectric layer 402a has a thickness h2 of 35 um, and the outermost second dielectric layer 402b has a thickness h2'. The thickness T' of the first dielectric portion 401 is smaller than the thickness D' of the second dielectric portion 402.

Therefore, the thermal expansion coefficient of the package substrate 4 of the present embodiment by the outermost second dielectric layer 402b is smaller than the thermal expansion coefficient of each of the first dielectric layers 401a, 401b and the other second dielectric layer 402a, and The thickness T' of the first dielectric portion 401 is smaller than the thickness D' of the second dielectric portion 402. Therefore, during the packaging process, the amount of expansion and contraction of the dielectric layer is different when the package substrate 4 is temperature-circulated (thickness is different) Thicker, the degree of warpage is small), thereby balancing the difference in thermal expansion coefficient between the package substrate 4 and the semiconductor wafer (or encapsulant), so that the package substrate 4 is warped as shown in FIG. 1A. The amount of deformation can be reduced by 15% to 50%.

It can be seen from the fourth embodiment that by using different CTEs and different thicknesses, the effect of adjusting warpage can be enhanced, and the package substrate 4 can be reduced in warpage during temperature rise and fall to improve product yield.

Furthermore, the larger dielectric layer of the CTE is cheaper. Therefore, when the dielectric layer is more than three layers, a dielectric layer with a larger CTE can be selected to reduce the cost of the package substrate.

Also, in the multilayer dielectric layer, the CTE of each dielectric layer may be decreased or increased from one side of the dielectric structure to the other.

In the first to fourth embodiments, the package substrate 2, 2', 3, 4 may include an insulating protective layer such as a solder resist layer, which is disposed on the dielectric structure 20, 20', 30, 40 and exposed a circuit layer for the circuit layer to incorporate other components.

Specifically, as shown in FIG. 3, the package substrate 3 further includes a first insulating protective layer 34a, and is disposed on the first dielectric portion 301 and exposes the first circuit layer 21 for the first circuit layer. 21 is bonded to a conductive member 35 such as a solder ball. Therefore, the first side 30a (or the first dielectric portion 301) of the dielectric structure 30 serves as a ball-planting side.

Alternatively, the package substrate 3 further includes a second insulating protective layer 34b disposed on the second dielectric portion 302 and exposing the second wiring layer 22 for the second wiring layer 22 to bond with the electronic component 33. Therefore, the second side 30b (or the second dielectric portion 302) of the dielectric structure 30 serves as a crystallizing side.

In this embodiment, the electronic component 33 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor.

Furthermore, the electronic component 33 is coupled to and electrically connected to the second circuit layer 22 by a plurality of conductive bumps 330. However, in other embodiments, the electronic component 33 can also be disposed in a wire package or embedded manner. The second dielectric portion 302 is on.

Moreover, the crystallizing side and the ball-planting side of the dielectric structure 30 are determined according to the process, and are not limited to the above.

In summary, the package substrate of the present invention has the thermal expansion coefficient of the first dielectric portion different from the thermal expansion coefficient of the second dielectric portion, so that the amount of expansion and contraction of each dielectric portion is different to reduce the package. The shape of the substrate warp.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Package substrate

20‧‧‧Dielectric structure

20a‧‧‧ first side

20b‧‧‧ second side

200‧‧‧conductive blind hole

201‧‧‧First Dielectric Department

202‧‧‧Second Dielectric Department

21‧‧‧First line layer

22‧‧‧Second circuit layer

t,d‧‧‧thickness

Claims (12)

A package substrate includes a dielectric structure including a first dielectric portion and a second dielectric portion, wherein a thermal expansion coefficient of the first dielectric portion is different from a thermal expansion coefficient of the second dielectric portion And a circuit layer disposed on the dielectric structure. The package substrate of claim 1, wherein the first dielectric portion has a plurality of first dielectric layers. The package substrate of claim 2, wherein each of the first dielectric layers has the same or different thermal expansion coefficients. The package substrate of claim 2, wherein the thickness of each of the first dielectric layers is equal or unequal. The package substrate of claim 1, wherein the second dielectric portion has a plurality of second dielectric layers. The package substrate of claim 5, wherein each of the second dielectric layers has the same or different thermal expansion coefficients. The package substrate of claim 5, wherein the thickness of each of the second dielectric layers is equal or unequal. The package substrate of claim 5, wherein, among the second dielectric layers, a second dielectric layer farthest from the first dielectric portion has a thermal expansion coefficient smaller than the other second dielectric layers Thermal expansion coefficient. The package substrate of claim 1, wherein the thickness of the first dielectric portion is equal to or not equal to the thickness of the second dielectric portion. The package substrate according to claim 1, wherein the first A dielectric portion is adjacent to the second dielectric portion. The package substrate according to claim 1, further comprising a core layer interposed between the first dielectric portion and the second dielectric portion. The package substrate according to claim 1, further comprising an insulating protective layer disposed on the dielectric structure and exposing the circuit layer.