TW201635438A - Semiconductor device and method of forming the same - Google Patents

Abstract

Provided is a semiconductor device including a substrate, a magnetic composite layer, an inductor and a capacitor. The substrate has a first area and a second area and has a metal layer and an insulating layer formed thereon. The magnetic composite layer is disposed on the insulating layer in the first and second areas. The inductor is completely covered by the magnetic composite layer of the first area. The capacitor is disposed in the second area, and the magnetic composite layer of the second area serves as an electrode of the capacitor. A method of forming a semiconductor device is further provided.

Description

Semiconductor component and method of manufacturing same

The present invention relates to an integrated circuit and a method of fabricating the same, and more particularly to a semiconductor device and a method of fabricating the same.

With the development of multi-function wafers, it has become a trend to integrate components of different functions, such as inductors and capacitors, on a single wafer. However, the fabrication of inductors and capacitors is usually done separately, requiring multiple masks and complex process steps, which increases cost and reduces competitiveness.

In addition, the existing front-end process has a limited area of inductors and capacitors, and is therefore not suitable for today's power supply systems. Therefore, how to make large-area inductors and capacitors with simple process steps has gained high attention in the industry.

In view of the above, the present invention provides a semiconductor device and a method of fabricating the same that can be easily integrated with a capacitor using an existing pad process.

The present invention provides a method of manufacturing a semiconductor device. A substrate is provided. The substrate has a first region, and a metal layer and an insulating layer have been formed on the substrate. A first magnetic layer is formed on the insulating layer of the first region. A spiral pattern is formed on the first magnetic layer of the first region. A dielectric layer is formed that covers the spiral pattern and at least exposes the first surface of the first magnetic layer on the outer side of the spiral pattern. A second magnetic layer is formed that covers the dielectric layer and is in contact with the first surface of the first magnetic layer.

In an embodiment of the invention, the dielectric layer exposes a second surface of the first magnetic layer at the center of the spiral pattern, and the two magnetic layers are in contact with the second surface of the first magnetic layer.

In an embodiment of the invention, the substrate further has a second region. The first magnetic layer is further formed on the insulating layer of the second region. In the step of forming the spiral pattern in the first region, a plurality of block patterns are simultaneously formed on the first magnetic layer of the second region. The dielectric layer further covers the block pattern of the second region. The second magnetic layer further covers the dielectric layer of the second region.

In an embodiment of the invention, the first region is an inductor region and the second region is a capacitor region.

In an embodiment of the invention, the spiral pattern includes a first dielectric pattern and a first non-magnetic metal pattern from bottom to top, and each of the block patterns includes a second dielectric pattern from bottom to top. Two non-magnetic metal patterns. Further, the first non-magnetic metal pattern and the second non-magnetic metal pattern are formed simultaneously with the bonding pad.

In an embodiment of the invention, the first magnetic layer includes a first ferromagnetic layer from the bottom to the first barrier layer, and the second magnetic layer includes a second barrier layer from the bottom to the top Two ferromagnetic layers.

The present invention further provides a semiconductor device including a substrate, a magnetic composite layer, an inductor, and a capacitor. The substrate has a first region and a second region, and a metal layer and an insulating layer have been formed on the substrate. The magnetic composite layer is disposed in the first zone and the second zone. On the edge layer. The inductor is completely covered in the magnetic composite layer of the first region. The capacitor is disposed in the second region, and the magnetic composite layer of the second region serves as an electrode of the capacitor.

In an embodiment of the invention, the magnetic composite layer includes a first magnetic layer and a second magnetic layer. The first magnetic layer is disposed below the inductor. The second magnetic layer covers the top and sides of the inductor.

In an embodiment of the invention, the first magnetic layer includes a first ferromagnetic layer from the bottom to the first barrier layer, and the second magnetic layer includes a second barrier layer from the bottom to the top Two ferromagnetic layers.

In an embodiment of the invention, the semiconductor device further includes a first magnetic layer, a spiral pattern, a second magnetic layer, and a dielectric layer. The first magnetic layer is disposed on the insulating layer of the first region. The spiral pattern is disposed on the first magnetic layer of the first region. The second magnetic layer covers the spiral pattern and is in contact with at least the first surface of the first magnetic layer on the outer side of the spiral pattern. The dielectric layer is disposed between the spiral pattern and the second magnetic layer.

In an embodiment of the invention, the second magnetic layer is further in contact with the second surface of the first magnetic layer at the center of the spiral pattern.

In an embodiment of the invention, the first magnetic layer is disposed on the insulating layer of the second region. A plurality of block patterns are disposed on the first magnetic layer of the second region. The second magnetic layer further covers at least a portion of the block pattern. The dielectric layer is further disposed between each of the block patterns and the second magnetic layer.

In an embodiment of the invention, the spiral pattern includes a first dielectric pattern and a first non-magnetic metal pattern from bottom to top, and each of the block patterns includes a second dielectric pattern from bottom to top. Two non-magnetic metal patterns.

Based on the above, in the present invention, the process of forming the pad is used, and more The next two layers of magnetic material can be used to make inductors and capacitors simultaneously. In other words, the existing back-end process can be used to easily integrate the inductor and the capacitor, which greatly reduces the cost and enhances the competitiveness.

The above described features and advantages of the invention will be apparent from the following description.

100‧‧‧Base

100a‧‧‧First District

100b‧‧‧Second District

102‧‧‧metal layer

104‧‧‧Insulation

105‧‧‧First ferromagnetic layer

106, 106'‧‧‧ first magnetic layer

107‧‧‧First barrier layer

108‧‧‧Interlayer dielectric layer

108a‧‧‧First dielectric pattern

108b‧‧‧Second dielectric pattern

109‧‧‧Spiral pattern

110‧‧‧Non-magnetic metal layer

110a‧‧‧First non-magnetic metal pattern

110b‧‧‧Second non-magnetic metal pattern

111‧‧‧block pattern

112‧‧‧ dielectric material layer

113‧‧‧ dielectric layer

114‧‧‧ first surface

116‧‧‧ second surface

118, 118'‧‧‧ first magnetic layer

117‧‧‧second barrier layer

119‧‧‧Second ferromagnetic layer

120, 120'‧‧‧ magnetic composite layer

122‧‧‧ openings

1A-1F are schematic cross-sectional views showing a method of fabricating a semiconductor device according to an embodiment of the invention.

2 is a top plan view of an inductor according to an embodiment of the invention.

3 is a top plan view of a capacitor according to an embodiment of the invention.

4 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention.

The spirit of the invention lies in the simultaneous fabrication of two passive components (such as inductors and capacitors) by means of the subsequent pad process, which can not only achieve the purpose of easy integration, but also form a passive component with a large enough area to comply with the existing power supply system. Demand.

1A-1F are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the invention.

First, referring to FIG. 1A, a substrate 100 is provided. Substrate 100 can be a semiconductor substrate, such as a germanium containing substrate. In an embodiment, the metal layer 102 and the insulating layer 104 have been formed on the substrate 100. The material of the metal layer 102 includes a metal such as aluminum, copper, tungsten, nickel, cobalt, titanium or an alloy thereof. The material of the insulating layer 104 includes cerium oxide (TEOS-SiO ₂ ), borophosphoquinone glass (BPSG), phosphoric bismuth glass (PSG), hydrogenated sesquioxide (HSQ) formed by tetraethoxy siloxane. Fluorinated glass (FSG), undoped bismuth glass (USG), tantalum nitride, bismuth oxynitride, low dielectric materials having a dielectric constant of less than 4, or combinations thereof. The method of forming the metal layer 102 and the insulating layer 104 each includes performing a suitable deposition process such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process.

In an embodiment, a gate, a contact window, an insulating layer, etc., which are well known to those skilled in the art, may be disposed between the substrate 100 and the metal layer 102. However, for clarity of explanation, it is not shown in FIG. In the picture.

Further, the substrate 100 may have a first region 100a and a second region 100b. In the following embodiments, the first region 100a is an inductor region and the second region 100b is a capacitor region. However, the present invention is not limited thereto.

Referring to FIG. 1A, the first magnetic layer 106, the interlayer dielectric layer 108 and the non-magnetic metal layer 110 are sequentially formed on the insulating layer 104 of the first region 100a and the second region 100b. The material of the first magnetic layer 106 includes a ferromagnetic material containing at least one of cobalt (Co), iron (Fe), and nickel (Ni). More specifically, the material of the first magnetic layer 106 includes Mn-Zn, Cu-Zn, Ni-Zn, Fe-Ni-Mo, Fe-Co-Ni, Fe-Si, Al-Fe, Fe-Si-Al. Or an alloy thereof or a combination thereof. The material of the first magnetic layer 106 may also include an amorphous or nano-crystal alloy. The material of the interlayer dielectric layer 108 includes cerium oxide (TEOS-SiO ₂ ), borophosphoquinone glass (BPSG), phosphorous bismuth glass (PSG), and hydrogenated sesquioxide (HSQ) formed by tetraethoxy siloxane. ), fluorocarbon glass (FSG), undoped bismuth glass (USG), tantalum nitride, bismuth oxynitride, a low dielectric material having a dielectric constant of less than 4, or a combination thereof. The material of the non-magnetic metal layer 110 includes aluminum (Al), gold (Au), copper (Cu), titanium (Ti), tantalum (Ta), or an alloy thereof. The methods of forming the first magnetic layer 106, the interlayer dielectric layer 108, and the non-magnetic metal layer 110 each include performing a suitable deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

In an embodiment, after the step of forming the interlayer dielectric layer 108 and before the step of forming the non-magnetic metal layer 110, further comprising forming a plurality of conductive plugs (not shown), the conductive plugs inter-layer dielectric The layer 108, the first magnetic layer 106, and the insulating layer 104 are electrically connected to the metal layer 102.

Then, referring to FIG. 1B, the interlayer dielectric layer 108 and the non-magnetic metal layer 110 are patterned to form a spiral pattern 109 on the first magnetic layer 106 of the first region 100a, while being the first in the second region 100b. A plurality of block patterns 111 are formed on the magnetic layer 106. More specifically, the patterning step includes a lithography process that patterns the interlayer dielectric layer 108 into a first dielectric pattern 108a, a second dielectric pattern 108b, and patterns the non-magnetic metal layer 110 into The first non-magnetic metal pattern 110a and the second non-magnetic metal pattern 110b. In this embodiment, the spiral pattern 107 includes a first dielectric pattern 108a and a first non-magnetic metal pattern 110a from bottom to top, and each of the block patterns 111 includes a second dielectric pattern 108b from bottom to top. The second non-magnetic metal pattern 110b.

It is to be noted that, in the first region 100a, the first non-magnetic metal pattern 110a in the spiral pattern 109 functions as an inductor, so that the pitch of the spiral pattern 109 is large, and the resistance of the inductor can be made. The value is reduced. As the inductor A top view of a non-magnetic metal pattern 110a is shown in FIG. Further, although the shape of the inductor is illustrated by a rectangular spiral in FIG. 2, it is not intended to limit the present invention. In another embodiment, the shape of the inductor may also be a circular spiral or an octagonal spiral or the like.

In addition, in the second region 100b, the second non-magnetic metal pattern 110b in the block pattern 111 is an electrode of a metal-insulator-metal (MIM) capacitor, so the pitch of the block pattern 111 Smaller, the density of the capacitor can be increased. A top view of the first non-magnetic metal pattern 110b as a capacitor electrode is shown in FIG. Further, although the shape of the capacitor electrode is illustrated in FIG. 3 as a grid, it is not intended to limit the present invention. In another embodiment, the shape of the capacitor electrode may also be linear, columnar, array, or the like.

In particular, the non-magnetic metal layer 110 may be a pad metal layer. In this case, the first non-magnetic metal pattern 110a and the second non-magnetic metal pattern 110b may be formed simultaneously with the pad. In other words, an additional process step is not required, and the inductor of the first region 100a (for example, the first non-magnetic metal pattern 110a) and the capacitor electrode of the second region 100b (for example, the second) can be simultaneously completed by using the original pad process. Fabrication of the non-magnetic metal pattern 110b).

Next, referring to FIG. 1C, a dielectric material layer 112 is formed on the first magnetic layer 106 of the first region 100a and the second region 100b. More specifically, in the first region 100a, the dielectric material layer 112 covers the spiral pattern 109 and a portion of the first magnetic layer 106 exposed between the spiral patterns 109. Similarly, in the second region 100b, the dielectric material layer 112 covers the portion of the first magnetic layer 106 exposed between the bulk pattern 111 and the bulk pattern 111. In one embodiment, the material of the dielectric material layer 112 includes a tantalum nitride, an oxide/nitride/oxide (ONO) composite layer, or a dielectric material having a dielectric constant higher than 4. For example, HfO ₂ , TiO ₂ , ZrO ₂ , Ta ₂ O ₅ or Al ₂ O _{3 ,} etc., and the formation method thereof includes performing a chemical vapor deposition process, a thermal oxidation process, or an atomic layer deposition process. In another embodiment, the material of the dielectric material layer 112 comprises ruthenium dioxide (TEOS-SiO ₂ ), bisphosphonium bismuth glass (BPSG), phosphorous bismuth glass (PSG), hydrogenation formed by tetraethoxy siloxane. Bismuth sesquioxide (HSQ), fluorocarbon glass (FSG), undoped bismuth glass (USG), tantalum nitride, bismuth oxynitride, low dielectric materials having a dielectric constant of less than 4, or combinations thereof, and their formation The method includes performing a suitable deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

Next, referring to FIG. 1D, a photolithography process is performed to remove a portion of the dielectric material layer 112 of the first region 100a to form a dielectric layer 113. The dielectric layer 113 exposes at least the first surface 114 of the first magnetic layer 106 on the outer side of the spiral pattern 109. In an embodiment, the dielectric layer 113 exposes the second surface 116 of the first magnetic layer 106 at the center of the spiral pattern 109, as shown in FIG. 1D. In another embodiment (not shown), the dielectric layer 113 may also expose a portion of the first magnetic layer 106 between any two adjacent spirals of the spiral pattern 109, depending on customer needs.

Then, referring to FIG. 1E, a second magnetic layer 118 is formed that covers the dielectric layer 113 and is in contact with the first surface 114 of the first magnetic layer 106 and the second surface 116. The material of the second magnetic layer 118 includes a ferromagnetic material containing at least one of cobalt, iron, and nickel. More specifically, the material of the second magnetic layer 118 includes Mn-Zn, Cu-Zn, Ni-Zn, Fe-Ni-Mo, Fe-Co-Ni, Fe-Si, Al-Fe, Fe-Si-Al. Or an alloy thereof or a combination thereof. The material of the second magnetic layer 118 may also include an amorphous or nano-crystal alloy. A method of forming the second magnetic layer 118 includes performing Suitable deposition processes, such as chemical vapor deposition processes, physical vapor deposition processes or atomic layer deposition processes, and the like. The material of the second magnetic layer 118 and the first magnetic layer 106 may be the same or different. In this embodiment, the second magnetic layer 118 and the first magnetic layer 106 constitute the magnetic composite layer 120.

It is to be noted that, since the second magnetic layer 118 and the first magnetic layer 106 are in contact with each other at least on the outer side of the spiral pattern 109, the inductor (for example, the first non-magnetic metal pattern 110a) may be completely covered on the magnetic composite layer. In 120, the inductance value of the inductor is further increased. In one embodiment, the second magnetic layer 118 and the first magnetic layer 106 are not only in contact with each other on the outer side of the spiral pattern 109 but also connected to each other at the center of the spiral pattern 109. In this way, the inductor (for example, the first The non-magnetic metal pattern 110a) can not only be completely covered in the magnetic composite layer 120, but also can form two magnetic circuits to increase the magnetic flux and further increase the inductance value of the inductor.

Next, referring to FIG. 1F, a lithography process is performed to remove a portion of the magnetic composite layer 120 to form an opening 122 in the magnetic composite layer 120. Specifically, the opening 122 penetrates the second magnetic layer 118 and the first magnetic layer 106, and a portion of the insulating layer 104 is exposed.

Next, a passivation layer (not shown) is formed to fill the opening 122 to isolate the inductor of the first region 100a from the capacitor of the second region 100b. The material of the passivation layer includes tantalum nitride, tantalum oxide, tantalum carbide and aluminum oxide, and the formation method thereof includes performing a suitable deposition process such as a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. Thus far, the fabrication of the semiconductor device of the present invention has been completed.

Hereinafter, the structure of the semiconductor element of the present invention will be described with reference to FIG. 1F. As shown in FIG. 1F, the semiconductor device of the present invention includes a substrate 100 and a first magnetic layer. 106. A spiral pattern 109, a plurality of block patterns 111, a second magnetic layer 118, and a dielectric layer 113. The substrate 100 has a first region 100a and a second region 100b, and a metal layer 102 and an insulating layer 104 have been formed on the substrate 100. The first magnetic layer 106 and the second magnetic layer 118 constitute the magnetic composite layer 120.

In the first region 100a, the first magnetic layer 106 is disposed on the insulating layer 104, and the spiral pattern 109 is disposed on the first magnetic layer 106. The spiral pattern 109 includes a first dielectric pattern 108a and a first non-magnetic metal pattern 110a from bottom to top. In an embodiment, the spiral first non-magnetic metal pattern 110a can function as an inductor. The second magnetic layer 118 covers the spiral pattern 109 and is in contact with at least the first surface 114 of the first magnetic layer 106 on the outer side of the spiral pattern 109. In an embodiment, the second magnetic layer 118 is further in contact with the second surface 116 of the first magnetic layer 106 at the center of the spiral pattern 109. The dielectric layer 113 is disposed between the spiral pattern 109 and the second magnetic layer 118.

In particular, the inductor (eg, the first non-magnetic metal pattern 110a) is entirely encapsulated in the magnetic composite layer 120 of the first region 100a. More specifically, the magnetic composite layer 120 includes a first magnetic layer 106 and a second magnetic layer 118. The first magnetic layer 106 is disposed under the inductor (eg, the first non-magnetic metal pattern 110a), and the second magnetic layer 118 A top surface and a side surface of the inductor (for example, the first non-magnetic metal pattern 110a) are covered. In the semiconductor device of the present invention, since the inductor of the first region 100a (for example, the first non-magnetic metal pattern 110a) is entirely covered in the magnetic composite layer 120, magnetic leakage or electromagnetic interference can be avoided, thereby increasing the inductor. Inductance value.

In addition, the first magnetic layer 106 is disposed on the insulating layer 104 of the second region 100b, and the block pattern 111 is disposed on the first magnetic layer 106 of the second region 100b. Each block pattern 111 includes a second dielectric pattern 108b and a second non-magnetic layer from bottom to top. Metal pattern 110b. The second magnetic layer 118 more covers at least a portion of the block pattern 111. In an embodiment, the block pattern 111 not covered by the second magnetic layer 118 is used, for example, for electrical connection with a wire or a conductive plug. The dielectric layer 113 is further disposed between each of the block patterns 111 and the second magnetic layer 118.

In particular, the capacitor is disposed in the second region 100b, and the magnetic composite layer 120 of the second region 100b can serve as an electrode of the capacitor. More specifically, the magnetic composite layer 120 includes a first magnetic layer 106 and a second magnetic layer 118, and the capacitor is a dual metal-insulator-metal (MIM) capacitor, wherein the second magnetic layer 118 (as a top electrode) The dielectric layer 113 and the first non-magnetic metal pattern 110b (as a bottom electrode) constitute a first capacitor, and the first non-magnetic metal pattern 110b (as a top electrode), the second dielectric pattern 108b and the first magnetic layer 106 (as a bottom electrode) constitutes a second capacitor. Here, although not shown, those skilled in the art can form a plurality of conductive plugs electrically connected to the required capacitor electrodes according to the circuit layout requirements, so as to design the first capacitor and the second capacitor as Used in parallel or in series.

In this embodiment, a planar inductor and a dual MIM capacitor are taken as an example, but the invention is not limited thereto. Those of ordinary skill in the art will appreciate that any semiconductor component that is integrally covered with a magnetic material and that is a magnetic component that is at least one electrode of the capacitor falls within the scope of the present invention. In a similar manner, the three-dimensional inductor and the three-dimensional capacitor can be easily fabricated by using the back-end process to increase the inductance value and the capacitance density.

Further, in the above embodiments, the single-layer first magnetic layer 106 and the single-layer second magnetic layer 118 are exemplified, but are not intended to limit the present invention. In another embodiment, the first magnetic layer 106 and the second magnetic layer 118 may also be a double layer or a multilayer structure.

4 is a cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. 4 is similar to the structure of FIG. 1F, and the difference is only in the composition of the magnetic composite layer, and the differences will be described in detail below, and the same portions will not be described again.

More specifically, as shown in Fig. 4, the magnetic composite layer 120' includes a first magnetic layer 106' and a second magnetic layer 118'. The first magnetic layer 106' includes a first ferromagnetic layer 105 and a first barrier layer 107 from bottom to top, and the second magnetic layer 118' includes a second barrier layer 117 and a second ferromagnetic layer from bottom to top. Layer 119.

The first ferromagnetic layer 105 is similar in material to the first magnetic layer 106, the second ferromagnetic layer 119 is similar in material to the second magnetic layer 118, and each of which includes a high resistance ferromagnetic material. The materials of the first ferromagnetic layer 105 and the second ferromagnetic layer 119 may be the same or different.

The first barrier layer 107 and the second barrier layer 117 each comprise a low resistance material such as Ti, TiN, Ta, TiN or a combination thereof, and the method of forming each comprises performing a suitable deposition process, such as a chemical vapor deposition process, Physical vapor deposition process or atomic layer deposition process, and the like. The material of the first barrier layer 107 and the second barrier layer 117 may be the same or different.

In particular, in this embodiment, a low-resistance first is disposed between the high-resistance first ferromagnetic layer 105/second ferromagnetic layer 119 and the inductor (eg, the first non-magnetic metal pattern 110a) A barrier layer 107 / second barrier layer 117, in this arrangement, not only increases the inductance of the inductor, but also reduces the skin effect.

In summary, in the present invention, by using the existing pad process, the magnetic materials of the upper and lower layers can be used to simultaneously complete the fabrication of the inductor and the capacitor, which can not only achieve the purpose of easy integration, but also form an inductor and Capacitors have a large enough area to meet the needs of existing power supply systems. In addition, the inductor produced by the invention The inductor is a fully shielded or coated inductor with high inductance and low electromagnetic interference (EMI). Further, the capacitor fabricated by the present invention is a double MIM capacitor having a high capacitance density. Therefore, the method of the present invention can utilize the existing back-end process to simultaneously produce high-Q inductors and high-Q capacitors, thereby greatly reducing costs and improving competitiveness.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

100a‧‧‧First District

100b‧‧‧Second District

102‧‧‧metal layer

104‧‧‧Insulation

106‧‧‧First magnetic layer

108a‧‧‧First dielectric pattern

108b‧‧‧Second dielectric pattern

109‧‧‧Spiral pattern

110a‧‧‧First non-magnetic metal pattern

110b‧‧‧Second non-magnetic metal pattern

111‧‧‧block pattern

113‧‧‧ dielectric layer

114‧‧‧ first surface

116‧‧‧ second surface

118‧‧‧First magnetic layer

120‧‧‧Magnetic composite layer

122‧‧‧ openings

Claims (13)

A method of fabricating a semiconductor device, comprising: providing a substrate having a first region, wherein a metal layer and an insulating layer are formed on the substrate; and forming a first magnetic layer on the insulating layer of the first region Forming a spiral pattern on the first magnetic layer of the first region; forming a dielectric layer covering the spiral pattern and exposing at least one of the first magnetic layers on the outer side of the spiral pattern a first surface; and a second magnetic layer overlying the dielectric layer and in contact with the first surface of the first magnetic layer. The method of fabricating a semiconductor device according to claim 1, wherein the dielectric layer exposes a second surface of the first magnetic layer at a center of the spiral pattern, and the two magnetic layers are The second surface of the first magnetic layer is in contact. The method of manufacturing a semiconductor device according to claim 1, wherein: the substrate further has a second region; the first magnetic layer is further formed on the insulating layer of the second region; In the step of forming the spiral pattern, a plurality of block patterns are simultaneously formed on the first magnetic layer of the second region; the dielectric layer further covers the block patterns of the second region; and the second The magnetic layer further covers the dielectric layer of the second region. The method of manufacturing a semiconductor device according to claim 3, wherein the first region is an inductor region, and the second region is a capacitor region. A method of manufacturing a semiconductor device according to claim 3, wherein The spiral pattern includes a first dielectric pattern and a first non-magnetic metal pattern from bottom to top; each of the block patterns includes a second dielectric pattern from bottom to top and a second non-magnetic metal a pattern; and the first non-magnetic metal pattern and the second non-magnetic metal patterns are formed simultaneously with the pad. The method of manufacturing a semiconductor device according to claim 3, wherein the first magnetic layer comprises a first ferromagnetic layer and a first barrier layer from bottom to top; and the second magnetic layer comprises a second barrier layer and a second ferromagnetic layer from bottom to top. A semiconductor device comprising: a substrate having a first region and a second region, and a metal layer and an insulating layer are formed on the substrate; a magnetic composite layer disposed in the first region and the second region On the insulating layer; an inductor is completely covered in the magnetic composite layer of the first region; and a capacitor is disposed in the second region, and the magnetic composite layer of the second region serves as the capacitor electrode. The semiconductor device of claim 7, wherein the magnetic composite layer comprises: a first magnetic layer disposed under the inductor; and a second magnetic layer covering the top surface of the inductor and side. A method of manufacturing a semiconductor device according to claim 8, wherein The first magnetic layer includes a first ferromagnetic layer and a first barrier layer from bottom to top; and the second magnetic layer includes a second barrier layer and a second iron from bottom to top. Magnetic layer. The semiconductor device of claim 7, further comprising: a first magnetic layer disposed on the insulating layer of the first region; a spiral pattern disposed on the first magnetic region of the first region a second magnetic layer covering the spiral pattern and contacting at least a first surface of the first magnetic layer on the outer side of the spiral pattern; and a dielectric layer disposed on the spiral pattern and the layer Between the second magnetic layers. The semiconductor device of claim 10, wherein the second magnetic layer is further in contact with a second surface of the first magnetic layer at the center of the spiral pattern. The semiconductor device of claim 10, wherein: the first magnetic layer is further disposed on the insulating layer of the second region; and the plurality of block patterns are disposed on the first magnetic region of the second region The second magnetic layer further covers at least a portion of the block patterns; and the dielectric layer is disposed between the block patterns and the second magnetic layer. The semiconductor device of claim 12, wherein: the spiral pattern comprises a first dielectric pattern and a first non-magnetic metal pattern from bottom to top; and each of the block patterns comprises a bottom-up a second dielectric pattern and a second non-magnetic metal pattern.