CN113506669A - Semiconductor package device and method of manufacturing the same - Google Patents
Semiconductor package device and method of manufacturing the same Download PDFInfo
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- CN113506669A CN113506669A CN202110632516.8A CN202110632516A CN113506669A CN 113506669 A CN113506669 A CN 113506669A CN 202110632516 A CN202110632516 A CN 202110632516A CN 113506669 A CN113506669 A CN 113506669A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000696 magnetic material Substances 0.000 claims abstract description 83
- 239000007769 metal material Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims abstract description 15
- 239000011810 insulating material Substances 0.000 claims description 86
- 239000000758 substrate Substances 0.000 claims description 20
- 238000005498 polishing Methods 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 11
- 238000004806 packaging method and process Methods 0.000 abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 239000004642 Polyimide Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- TZVIJZJPKDHUTG-UHFFFAOYSA-N [B].[Ta].[Zr].[Co] Chemical compound [B].[Ta].[Zr].[Co] TZVIJZJPKDHUTG-UHFFFAOYSA-N 0.000 description 1
- ZGWQKLYPIPNASE-UHFFFAOYSA-N [Co].[Zr].[Ta] Chemical compound [Co].[Zr].[Ta] ZGWQKLYPIPNASE-UHFFFAOYSA-N 0.000 description 1
- KGWWEXORQXHJJQ-UHFFFAOYSA-N [Fe].[Co].[Ni] Chemical compound [Fe].[Co].[Ni] KGWWEXORQXHJJQ-UHFFFAOYSA-N 0.000 description 1
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- 229910010272 inorganic material Inorganic materials 0.000 description 1
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- 239000000203 mixture Substances 0.000 description 1
- 238000010943 off-gassing Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/24—Magnetic cores
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2804—Printed windings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F2017/0086—Printed inductances on semiconductor substrate
Abstract
The present disclosure relates to a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes: the magnetic material comprises a base material, wherein a groove is formed in the base material, and a first magnetic material and a first metal material are sequentially arranged in the groove from an outer layer to the center; the second magnetic material is positioned above the opening of the groove; the first magnetic material, the first metal material and the second magnetic material together form an inductance structure. The semiconductor packaging device can form a groove type inductance structure, can effectively reduce the thickness of the inductance structure and enable the surface of a base material to be flat, and further reduces the overall size of electronic equipment. In addition, the semiconductor packaging device is formed without the aid of a stripping process, so that the problems of gas pollution or metal residue and the like generated by the stripping process can be avoided, and the product yield is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor packaging device and a method for manufacturing the same.
Background
Because of the special structure of the single chip inductor (on-chip inductor), in order to avoid the overall yield from being affected by unnecessary damage to the structure caused by the etching process, a required structure needs to be formed by a Lift-off process.
The Lift-off process is to evaporate the metal after the photolithography process, and then dissolve the sacrificial layer to peel off the metal adhesion in other areas, thereby forming the required metal pattern. The lift-off process can be effectively applied in a scenario where an etching process cannot be employed. However, in the lift-off process, the sacrificial layer (e.g. photoresist) is liable to generate gas contamination (outgassing) during the formation of the metal layer, thereby affecting the bonding effect between the metal and the substrate. In addition, if the opening angle of the sacrificial layer is insufficient, it cannot be effectively removed, and thus the metal layer on the surface of the sacrificial layer remains, resulting in product loss (product loss rate greater than 20%, for example).
Therefore, a new technical solution is needed to solve at least one of the above technical problems.
Disclosure of Invention
The present disclosure provides a semiconductor package device and a method of manufacturing the same.
In a first aspect, the present disclosure provides a semiconductor package device, comprising:
the magnetic material comprises a base material, wherein a groove is formed in the base material, and a first magnetic material and a first metal material are sequentially arranged in the groove from an outer layer to the center;
a second magnetic material located above the opening of the trench;
the first magnetic material, the first metal material and the second magnetic material together form an inductance structure.
In some optional embodiments, the semiconductor package device further includes: and the first insulating material is positioned between the first magnetic material and the first metal material.
In some optional embodiments, the semiconductor package device further includes: and the second insulating material covers the opening of the groove and at least partially covers the second magnetic material.
In some optional embodiments, the semiconductor package device further includes: and a third insulating material located between the outer surface of the first magnetic material and the inner surface of the groove.
In some alternative embodiments, the upper surfaces of the first magnetic material, the first metal material, and the first insulating material are coplanar.
In some alternative embodiments, the upper surface of the second magnetic material and the upper surface of the second insulating material are coplanar, and the upper surface of the second magnetic material is exposed.
In some alternative embodiments, there is a space between the second magnetic material and the first metal material, the space being filled with the second insulating material.
In some optional embodiments, the semiconductor package device further includes:
a second metal material located on the outer surface of the third insulating material;
the first metal material, the first insulating material, the first magnetic material, the third insulating material and the second metal material together form a capacitor structure.
In some optional embodiments, the semiconductor package device further includes:
and a fourth insulating material located between the outer surface of the second metal material and the inner surface of the recess.
In some alternative embodiments, the material of the substrate is polyimide or silicon dioxide.
In some alternative embodiments, the first metal material has a square, circular or triangular shape in longitudinal section.
In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, including:
forming a trench on a substrate;
sequentially forming a third insulating material, a first magnetic material, a first insulating material and a first metal material from the outer layer to the center in the groove;
forming a second insulating material over the trench;
and forming a second magnetic material in the second insulating material, wherein the first magnetic material, the first metal material and the second magnetic material jointly form an inductance structure.
In some optional embodiments, the sequentially forming a third insulating material, a first magnetic material, a first insulating material, and a first metal material from an outer layer to a center in the trench includes:
forming the third insulating material in the trench;
forming the first magnetic material on the surface of the third insulating material;
forming the first insulating material on the surface of the first magnetic material;
and forming the first metal material on the surface of the first insulating material.
In some optional embodiments, the forming a second insulating material over the trench includes:
leveling the upper surfaces of the base material, the third insulating material, the first magnetic material, the first insulating material, and the first metal material by polishing;
and forming the second insulating material on the polished upper surface.
In some optional embodiments, said forming a second magnetic material within said second insulating material comprises:
forming an opening on the surface of the second insulating material;
forming the first magnetic material in the opening;
and reducing the thickness of the second insulating material by polishing, and only keeping the first magnetic material at the bottom of the opening.
In the semiconductor packaging device and the manufacturing method thereof provided by the disclosure, the groove is arranged on the substrate, the first magnetic material and the first metal material are arranged in the groove, and the second magnetic material is arranged above the opening of the groove, so that the groove type inductance structure can be formed, the thickness of the inductance structure can be effectively reduced, the surface of the substrate is flat, and the overall size of the electronic equipment is further reduced. In addition, the semiconductor packaging device provided by the disclosure is formed without a stripping process, so that the problems of gas pollution or metal residue and the like generated by the stripping process can be avoided, and the yield of products can be improved.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIGS. 1A and 1B are schematic diagrams of a semiconductor package device in the prior art;
fig. 2-4 are first through third schematic views of a semiconductor package device according to an embodiment of the present invention;
fig. 5 to 13 are schematic views of a method of manufacturing a semiconductor package device according to an embodiment of the present invention.
Description of the symbols:
11. a substrate; 12. a magnetic film; 13. a light resistance; 100. a substrate; 210. a first magnetic material; 220. a second magnetic material; 310. a first metal material; 320. a second metal material; 410. a first insulating material; 420. a second insulating material; 430. a third insulating material; 440. a fourth insulating material; 800. opening a hole; 900. and (4) a groove.
Detailed Description
The following description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples, and the technical problems and effects solved by the present invention will be readily apparent to those skilled in the art from the description of the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined by the claims and the appended claims, and therefore, they are not technically essential, and any structural modification, proportion change, or size adjustment should be within the scope of the present disclosure without affecting the function and achievement of the present disclosure. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship thereof may be regarded as the scope of the present invention without substantial technical changes.
It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1A and 1B are schematic views of a semiconductor package device in the prior art, which illustrate problems in the manufacturing process of the prior art semiconductor package device. As shown in fig. 1A and 1B, in manufacturing a conventional semiconductor package device by a lift-off process, a photoresist 13 is provided on a surface of a substrate 11, and an opening is formed in the photoresist 13 by exposure. In addition, the magnetic film 12 is formed on the surface of the substrate 11 by Physical Vapor Deposition (PVD) and the magnetic film 12 is also formed on the surface of the photoresist 13. The photoresist 13 is then removed by dissolution. Since part of the magnetic film 12 is attached to the surface of the photoresist 13, after the photoresist 13 is removed, the magnetic film 12 attached thereto is also removed, and only the magnetic film 12 on the surface of the substrate 11 remains. In the above process, as shown in fig. 1A, the photoresist 13 may generate gas contamination at the time of formation of the magnetic film 12, which may affect the bonding between the magnetic film 12 and the substrate 11 (as shown by the dotted line in fig. 1A). In addition, as shown in fig. 1B, if the opening angle of the photoresist 13 is insufficient, the magnetic film 12 is formed on the sidewall of the photoresist 13, so that the photoresist 13 cannot be effectively removed, resulting in metal residue. The above problems all affect the yield of the product.
Fig. 2-4 are first to third schematic views of semiconductor package devices according to embodiments of the present invention.
As shown in fig. 2, the semiconductor package device in this embodiment includes a substrate 100, a first magnetic material 210, a first metal material 310, and a second magnetic material 220.
In the present embodiment, the substrate 100 is provided with a groove 900. The first magnetic material 210 and the first metal material 310 are sequentially disposed in the groove 900 from the outer layer to the center. The second magnetic material 220 is located above the opening of the trench 900.
In the present embodiment, the first magnetic material 210, the first metal material 310 and the second magnetic material 220 together form an inductor structure.
In the present embodiment, the substrate 100 may be an organic material such as Polyimide (PI), or an inorganic material such as silicon dioxide (SiO 2).
In the present embodiment, the semiconductor package device further includes a first insulating material 410. The first insulating material 410 is located between the first magnetic material 210 and the first metal material 310.
In this embodiment, the semiconductor package device further includes a second insulating material 420. The second insulating material 420 covers the opening of the trench 900 and at least partially covers the second magnetic material 220. For example, in fig. 2, the second insulating material 420 covers the lower surface and the periphery of the second magnetic material 220. The first insulating material 410 and the second insulating material 420 may be made separately or integrally.
In this embodiment, there is a space between the second magnetic material 220 and the first metal material 310, and the space is filled with the second insulating material 420.
In the present embodiment, the semiconductor package device further includes a third insulating material 430. The third insulating material 430 is located between the outer surface of the first magnetic material 210 and the inner surface of the recess.
In the present embodiment, the material of the first magnetic material 210 and the second magnetic material 220 may be selected from Cobalt Zirconium Tantalum (CZT), Cobalt Zirconium Tantalum Boron (CZTB), nickel iron alloy (NiFe), iron nickel cobalt alloy (FeNiCo), and the like.
In the present embodiment, the material of the first insulating material 410, the second insulating material 420, and the third insulating material 430 may be selected from silicon oxide (SiO), silicon nitride (SiN), polyimide, or the like.
In this embodiment, the material of the first metal material 310 may be selected from copper, gold, silver, or the like.
In the present embodiment, the upper surfaces of the first magnetic material 210, the first metal material 310 and the first insulating material 410 are coplanar. Wherein, the two surfaces are coplanar, which means that the height difference between the two surfaces is not more than a preset value. The preset value is, for example, 5 micrometers (μm), 2 micrometers (μm), 1 micrometer (μm), or 0.5 micrometers (μm), etc.
In this embodiment, the upper surface of the second magnetic material 220 and the upper surface of the second insulating material 420 are coplanar, and the upper surface of the second magnetic material 220 is exposed.
In one example, as shown in fig. 3, the semiconductor package device further includes a second metal material 320. The second metal material 320 is located on the outer surface of the third insulating material 430. The first metal material 310, the first insulating material 410, the first magnetic material 210, the third insulating material 430 and the second metal material 320 form a capacitor structure. Therefore, the capacitor and the inductor can be integrated into the same element, so that the size of the packaging structure is reduced, and the size of the electronic equipment is further reduced. The material of the second metal material 320 may be selected from copper, gold, silver, or the like.
In the above example, the semiconductor package device further includes a fourth insulating material 440. Fourth insulating material 440 is located between the outer surface of second metal 320 and the inner surface of the recess.
In one example, as shown in fig. 4, the longitudinal cross-section of the trench 900 may be square, triangular, circular, or the like. The shape of the longitudinal cross section of the first metal material 310 in the groove 900 is identical to the shape of the longitudinal cross section of the groove 900, and may be square, circular, triangular, or the like.
In the semiconductor package device and the manufacturing method thereof provided by the present disclosure, the trench 900 is disposed on the substrate 100, the first magnetic material 210 and the first metal material 310 are disposed in the trench 900, and the second magnetic material 220 is disposed above the opening of the trench 900, so that a trench-type inductor structure can be formed, the thickness of the inductor structure can be effectively reduced, the surface of the substrate 100 is flat, and the overall size of the electronic device is reduced.
The embodiment also provides a manufacturing method of the semiconductor packaging device. As shown in fig. 5-13, the method includes the steps of:
in a first step, a trench 900 is formed in the substrate 100. As shown in fig. 5, a trench 900 having a square cross section may be formed in the substrate 100 by etching or the like.
In the second step, a third insulating material 430, a first magnetic material 210, a first insulating material 410, and a first metal material 310 are sequentially formed in the trench 900 from the outer layer toward the center. As shown in fig. 6, the third insulating material 430 may be formed on the inner surface of the trench 900 by Chemical Vapor Deposition (CVD). As shown in fig. 7, the first magnetic material 210 is formed on the surface of the third insulating material 430 by Physical Vapor Deposition (PVD). Then, as shown in fig. 8, a first insulating material 410 is formed on the surface of the first magnetic material 210 by chemical vapor deposition or the like. Finally, as shown in fig. 9, a first metal material 310 is formed on the surface of the first insulating material 410 by Plating (Plating) or the like.
Third, a second insulating material 420 is formed over trench 900. As shown in fig. 10, the upper surfaces of the substrate 100, the third insulating material 430, the first magnetic material 210, the first insulating material 410, and the first metal material 310 may be leveled by Chemical Mechanical Polishing (CMP) or the like. Next, as shown in fig. 11, a second insulating material 420 is formed on the upper surface of the polished structure.
Fourth, a second magnetic material 220 is formed in the second insulating material 420, wherein the first magnetic material 210, the first metal material 310 and the second magnetic material 220 together form an inductor structure. As shown in fig. 12, an opening 800 may be formed on the surface of the second insulating material 420. As shown in fig. 13, the second magnetic material 220 is formed in the opening 800. Finally, the thickness of the second insulating material 420 is reduced by polishing, and only the first magnetic material 210 at the bottom of the opening 800 remains, thereby obtaining the semiconductor package device shown in fig. 2.
The method for manufacturing a semiconductor package device in this embodiment can achieve the technical effects of the semiconductor package device described above, and will not be described herein again. In addition, the semiconductor packaging device provided by the disclosure can be formed without a stripping process through the above process, so that the problems of gas pollution or metal residue and the like generated by the stripping process can be avoided, and the yield of products can be improved.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.
Claims (10)
1. A semiconductor package device, comprising:
the magnetic material comprises a base material, wherein a groove is formed in the base material, and a first magnetic material and a first metal material are sequentially arranged in the groove from an outer layer to the center;
a second magnetic material located above the opening of the trench;
the first magnetic material, the first metal material and the second magnetic material together form an inductance structure.
2. The semiconductor package device of claim 1, wherein the semiconductor package device further comprises: and the first insulating material is positioned between the first magnetic material and the first metal material.
3. The semiconductor package device of claim 2, wherein the semiconductor package device further comprises: and the second insulating material covers the opening of the groove and at least partially covers the second magnetic material.
4. The semiconductor package device according to claim 3, wherein the semiconductor package device further comprises: and a third insulating material located between the outer surface of the first magnetic material and the inner surface of the groove.
5. The semiconductor package device according to claim 3, wherein an upper surface of the second magnetic material and an upper surface of the second insulating material are coplanar, the upper surface of the second magnetic material being exposed.
6. The semiconductor package device according to claim 3, wherein a space exists between the second magnetic material and the first metal material, the space being filled with the second insulating material.
7. A method of manufacturing a semiconductor package device, comprising:
forming a trench on a substrate;
sequentially forming a third insulating material, a first magnetic material, a first insulating material and a first metal material from the outer layer to the center in the groove;
forming a second insulating material over the trench;
and forming a second magnetic material in the second insulating material, wherein the first magnetic material, the first metal material and the second magnetic material jointly form an inductance structure.
8. The method of claim 7, wherein said sequentially forming a third insulating material, a first magnetic material, a first insulating material, and a first metal material from an outer layer to a center within said trench comprises:
forming the third insulating material in the trench;
forming the first magnetic material on the surface of the third insulating material;
forming the first insulating material on the surface of the first magnetic material;
and forming the first metal material on the surface of the first insulating material.
9. The method of claim 8, wherein said forming a second insulating material over said trench comprises:
leveling the upper surfaces of the base material, the third insulating material, the first magnetic material, the first insulating material, and the first metal material by polishing;
and forming the second insulating material on the polished upper surface.
10. The method of claim 7, wherein said forming a second magnetic material within said second insulating material comprises:
forming an opening on the surface of the second insulating material;
forming the first magnetic material in the opening;
and reducing the thickness of the second insulating material by polishing, and only keeping the first magnetic material at the bottom of the opening.
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| CN202110632516.8A CN113506669A (en) | 2021-06-07 | 2021-06-07 | Semiconductor package device and method of manufacturing the same |
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| TW201635438A (en) * | 2015-03-20 | 2016-10-01 | 聯華電子股份有限公司 | Semiconductor device and method of forming the same |
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