TW201631640A - 電晶體裝置及其成型方法 - Google Patents

電晶體裝置及其成型方法 Download PDF

Info

Publication number
TW201631640A
TW201631640A TW104139900A TW104139900A TW201631640A TW 201631640 A TW201631640 A TW 201631640A TW 104139900 A TW104139900 A TW 104139900A TW 104139900 A TW104139900 A TW 104139900A TW 201631640 A TW201631640 A TW 201631640A
Authority
TW
Taiwan
Prior art keywords
layer
work function
field effect
effect transistor
type field
Prior art date
Application number
TW104139900A
Other languages
English (en)
Other versions
TWI671806B (zh
Inventor
安藤崇志
巴拉吉 坎南
維傑 拿拉亞南
Original Assignee
格羅方德半導體Ｕｓ２有限責任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 格羅方德半導體Ｕｓ２有限責任公司 filed Critical 格羅方德半導體Ｕｓ２有限責任公司
Publication of TW201631640A publication Critical patent/TW201631640A/zh
Application granted granted Critical
Publication of TWI671806B publication Critical patent/TWI671806B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
    • H01L29/66863—Lateral single gate transistors
    • H01L29/66871—Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本發明揭示一種形成一電晶體裝置之方法，包含：在一基板上形成一界面層及一介電層；以及在該介電層上形成一功函數金屬層，該功函數金屬層包含一鈦-鋁-碳-氧(titanium-aluminum-carbon-oxygen；TiAlCO)層。

Description

電晶體裝置及其成型方法
本發明一般而言係關於半導體裝置製造，且更具體而言，係關於具有經改良負偏壓溫度不穩定性(negative bias temperature instability；NBTI)效能之取代閘極(replacement gate)p型場效電晶體(p-type field effect transistor；PFET)材料。
場效電晶體(field effect transistor；FET)在電子工業中被廣泛地用於切換、放大、濾波以及與類比及數位二種電訊號相關之其他任務。在此等場效電晶體當中最常見的係為金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field-effect transistor；MOSFET或MOS)，其中一閘極結構被供電以在一半導體本體之一下伏通道區域中形成一電場，藉此電子能夠行進穿過該半導體本體之一源極區域與一汲極區域間之通道。互補(complementary)金屬氧化物半導體場效電晶體(CMOS)裝置已被廣泛用於半導體工業中，其中使用n型及p型二種電晶體(NMOS及PMOS)來製作邏輯電路及其他電路。
一場效電晶體之源極區域及汲極區域通常係藉由在通道之二側上向一半導體本體之複數個目標區域添加摻雜劑而形成。一閘極結構 係形成於通道上方，該閘極結構包含位於該通道上方之一閘極電介質及位於該閘極電介質上方之一閘極導體。該閘極電介質係為一絕緣體材料，其在一電壓被施加至閘極導體時防止大的洩漏電流流入至通道中，同時容許所施加閘極電壓以一可控方式在通道區域中設置一橫向電場。習用金屬氧化物半導體場效電晶體通常包含藉由在一矽晶圓表面上沈積或生長二氧化矽(silicon dioxide；SiO2)或氮氧化矽(silicon oxynitride；SiON)而形成之一閘極電介質，其中SiO2上形成有經摻雜多晶矽以充當閘極導體。
半導體裝置製造的持續趨勢包含電裝置特徵大小之減小(即，按比例縮小)以及在裝置切換速度及功率消耗方面之裝置效能改良。可藉由減小裝置之閘極導體下方之介於源極區域與汲極區域間之距離(稱作閘極長度或通道長度)且藉由減小形成於半導體表面上之閘極電介質層之厚度來改良金屬氧化物半導體場效電晶體效能。然而，在可將SiO2閘極電介質之厚度減小達到的程度上會存在電性局限及實體局限。舉例而言，薄SiO2閘極電介質易於出現閘極穿隧洩漏電流，此係由電子直接穿隧過薄閘極電介質而引起。
對閘極電介質之按比例縮小係為改良進階場效電晶體之效能方面的一項挑戰。在採用一基於氧化矽之閘極電介質之一場效電晶體中，穿過閘極電介質之洩漏電流隨著閘極電介質厚度減小而以指數方式增加。在氧化矽閘極電介質之一厚度係為約1.1奈米或更低時，此等裝置通常變得太易於洩漏以致不能提供高效能。
因此，最近在金屬氧化物半導體場效電晶體及互補金屬氧化物半導體場效電晶體按比例縮小方面所做的努力已集中於介電常數較SiO2之介電常數為大(例如，大於約3.9)之高k介電材料。高k介電材料可被形 成為較已按比例縮小之SiO2為厚之一層，但仍產生等效之場效效能。因高k材料層可較厚，同時仍提供與一薄得多的SiO2層等效之電效能，故此等高k介電材料之相對電效能常常以等效氧化物厚度(equivalent oxide thickness；EOT)來表達。由於介電常數「k」高於二氧化矽，因此一較厚高k介電層可用於減輕穿隧洩漏電流，同時仍達成與一較薄熱生長SiO2層等效之電效能。
在一態樣中，一種形成一電晶體裝置之方法包含：在一基板上形成一界面層(interfacial layer)及一介電層；以及在該介電層上形成一功函數金屬層(workfunction metal layer)，該功函數金屬層包含一鈦-鋁-碳-氧(titanium-aluminum-carbon-oxygen；TiAlCO)層。
在另一態樣中，一種形成一電晶體裝置之方法包含：在一基板的一部分上形成一界面層及一介電層，該部分係對應於一被移除虛設閘極結構；在該介電層上形成一p型場效電晶體(p-type field effect transistor；PFET)功函數金屬層，該功函數金屬層包含一鈦-鋁-碳-氧(TiAlCO)層；以及在該p型場效電晶體功函數金屬層上形成一閘極金屬層，藉此界定一閘極堆疊。
在又一態樣中，一種電晶體裝置包含：一界面層及一介電層，形成於一基板的一部分上，該部分對應於一被移除虛設閘極結構；一p型場效電晶體(PFET)功函數金屬層，形成於該介電層上，該功函數金屬層包含一鈦-鋁-碳-氧(TiAlCO)層；以及一閘極金屬層，形成於該p型場效電晶體功函數金屬層上，藉此界定一閘極堆疊。
100‧‧‧半導體結構
102‧‧‧半導體基板
104‧‧‧淺溝槽隔離結構
106‧‧‧源極與汲極延伸區域
108‧‧‧源極與汲極區域
110‧‧‧側壁間隔件
112‧‧‧層間介電層
114‧‧‧凹槽
116‧‧‧界面氧化物層
118‧‧‧高k介電層
120‧‧‧p型場效電晶體功函數金屬層/鈦-鋁-碳-氧層
122‧‧‧剩餘金屬層
600‧‧‧製程流程、第一製程流程
602~616‧‧‧步驟
700‧‧‧製程流程、第二製程流程
702~716‧‧‧步驟
參照實例性附圖，其中在該若干圖中，相同元件之編號亦相同：第1圖至第5圖係為一種為一p型場效電晶體(PFET)裝置形成一高k閘極堆疊之方法之一實例性實施例之剖視圖，其中：第1圖例示移除形成於一半導體基板上之一犧牲虛設閘極結構；第2圖例示在第1圖所示結構上形成一界面層(interfacial layer；IL)及一高k介電層；第3圖例示在第2圖所示高k介電層上形成一鈦-鋁-碳-氧(TiAlCO)p型場效電晶體功函數金屬層，從而使得負偏壓溫度不穩定性效能得以改良；第4圖例示在第3圖所示結構上形成閘極堆疊之一或多個其他金屬層以界定一金屬閘電極材料；第5圖例示將第4圖所示結構平坦化，以界定一高k金屬閘極電晶體結構；第6圖係為例示根據本發明一實施例，一種為一互補金屬氧化物半導體場效電晶體裝置形成一高k閘極堆疊之方法之一流程圖；以及第7圖係為例示根據本發明另一實施例，一種為一互補金屬氧化物半導體場效電晶體裝置形成一高k閘極堆疊之方法之一流程圖。
對於未來之技術而言，為得到一高效能互補金屬氧化物半導體場效電晶體裝置，應將閘極電介質的基於反轉電容之氧化物等效厚度(亦簡稱為「反轉厚度(inversion thickness)」(Tinv))按比例減小至低於約11埃(angstrom；Å)。Tinv衡量每閘極電壓擺動之增量反轉電荷密度(incremental inversion charge density)。由於反轉層量子化及多晶矽閘極空乏效應，Tinv厚於等效氧化物厚度。因此，將等效氧化物厚度按比例縮小亦會使得Tinv按比例縮小。
一種取代閘極製程架構會避免在一閘極先製(gate first)架構中所見之功函數材料穩定性問題。此處，使用一虛設閘極結構來自對準源極與汲極之植入及退火，隨後剝除虛設閘極材料並將其取代為高k金屬閘極材料。雖然此製程較一閘極先製技術複雜，但一取代閘極流程之優點包含使用單獨之p型場效電晶體金屬及n型場效電晶體金屬以使功函數最佳化。另外，該二種金屬皆未被暴露於高溫，而簡化了材料選擇。此外，多晶矽閘極移除實際上可用於提高應變(strain)技術，藉此增加驅動電流。
負偏壓溫度不穩定性(NBTI)係為取代閘極製程在等效氧化物厚度按比例縮小方面之一嚴重問題，且已知此問題與將氮併入至Si/SiO2界面中相關聯。已發現，金屬氮化物(例如，TiN)會引起此種將氮併入至Si/SiO2界面中且使得負偏壓溫度不穩定性惡化。當前，TiN係業內最常用之p型場效電晶體功函數設定材料，且在本發明之前，一直不存在經過製造證實的替代金屬。亦已知負偏壓溫度不穩定性隨著跨閘極氧化物之電場增加而加劇，且因此，等效氧化物厚度(Tinv)之增加會實質上改良負偏壓溫度不穩定性。然而，因等效氧化物厚度(Tinv)之增加亦使得效能劣化，故此種選項並非係為較佳的。
首先參照第1圖至第5圖，其顯示一種為一p型場效電晶體(PFET)裝置形成一高k閘極堆疊之方法之一實例性實施例的一系列剖視圖。將瞭解，雖然具體例示了p型場效電晶體裝置形成，但根據互補金屬氧化物半導體場效電晶體製作技術，亦可存在包含n型場效電晶體裝置(未具體顯示)之其他區。另外，儘管實例性實施例係以取代閘極平坦場效電晶體裝置為背景而繪示，但亦將瞭解，此等製程亦同等適用於取代閘極鰭式場效電晶體(FinFET)裝置。
如第1圖中所示，一半導體結構100包含其中形成有複數個淺溝槽隔離結構104之一半導體基板102。半導體基板102包含一半導體材料，該半導體材料可選自(但不限於)矽、鍺、矽-鍺合金、矽-碳合金、矽-鍺-碳合金、砷化鎵、砷化銦、磷化銦、III-V族化合物半導體材料、II-VI族化合物半導體材料、有機半導體材料及其他化合物半導體材料。在半導體基板102之半導體材料係為一單晶含矽半導體材料之情形下，該單晶含矽半導體材料可選自一單晶矽、一單晶矽-碳合金、一單晶矽-鍺合金及一單晶矽-鍺-碳合金。
一般而言，半導體基板102之半導體材料可適當地摻雜有p型摻雜劑原子或n型摻雜劑原子。半導體基板102之摻雜劑濃度可介於自約1.0×1015原子/立方公分至約1.0×1019原子/立方公分，且更具體而言自約1.0×1016原子/立方公分至約3.0×1018原子/立方公分之範圍內，但本文中亦涵蓋更小及更大之摻雜劑濃度。另外，半導體基板102可係為一塊體(bulk)基板、一絕緣體上半導體(semiconductor-on-insulator；SOI)或絕緣體上矽(silicon-on-insulator；SOI)基板、或者一混合基板。淺溝槽隔離結構104包含一介電材料(諸如氧化矽或氮化矽)，且係藉由此項技術中眾所周知 之方法而形成。
如第1圖中亦例示，半導體結構100係為取代閘極場效電晶體技術之一實例。因此，該裝置包含藉由在已設置一虛設閘極結構(未顯示)之情形下進行離子植入而形成之複數個源極與汲極延伸區域106。源極與汲極延伸區域106具有與導電類型與基板102之摻雜相反之一摻雜。舉例而言，若基板102具有一p型摻雜，則源極與汲極延伸區域106具有一n型摻雜，且反之亦然。第1圖中亦繪示複數個源極與汲極區域108，舉例而言，源極與汲極區域108係藉由進行導電類型與延伸區域106相同之離子植入而形成。源極與汲極區域108係在已設置該虛設閘極結構以及複數個側壁間隔件110之情形下被植入。舉例而言，側壁間隔件110係藉由沈積一保形介電材料層(例如，一不透氧材料，諸如氮化矽)、隨後進行一非等向性離子蝕刻而形成。該介電材料層的直接形成於該虛設閘極結構之側壁上之部分在該非等向性蝕刻之後保留，以構成側壁間隔件110。
在移除虛設閘極結構之前，在裝置之複數個頂表面上形成一層間介電(interlevel dielectric；ILD)層112。層間介電層112包含一介電材料，諸如氧化矽、氮化矽、氮氧化矽或其一組合。另一選擇為，層間介電層112可包含介電常數小於3.9(例如，氧化矽之介電常數)且更具體而言小於2.5之一低k介電材料。實例性低k介電材料包含有機矽酸鹽玻璃(organosilicate glass；OSG)及SiLK®。層間介電層112被平坦化為暴露出該虛設閘極結構之一頂表面。
根據一取代閘極製程，第1圖顯示，該虛設閘極結構已如經由一或多個蝕刻製程被移除，以形成一凹槽114，凹槽114暴露出基板102的與場效電晶體通道之位置對應之一頂表面。下文中，將根據形成一取代閘 極p型場效電晶體裝置來闡述該等製程圖。
然後，如第2圖中所示，在基板102的位於閘極側壁間隔件110間之已暴露半導體表面上形成一界面氧化物層(interfacial oxide layer；IL)116。在一實例性實施例中，界面氧化物層116係藉由一化學氧化物製程而形成，諸如藉由一濕式化學氧化，其包含在65℃下以氫氧化銨、過氧化氫及水(呈一1：1：5比率)之一混合物處理已清潔(例如，藉由氫氟酸)之半導體表面102。另一選擇為，該化學氧化物層亦可藉由在臭氧水溶液(ozonated aqueous solution)中處理HF位於最上(HF-last)之半導體表面而形成，其中臭氧濃度通常自百萬分之(part per million；ppm)2至百萬分之40不等，但並不限於此範圍。然而，將瞭解，界面氧化物層116可係藉由此項技術中已知的其他製程而形成，例如，藉由對SiO2之原子層沈積(atomic layer deposition；ALD)或藉由在一O2或NH3周圍環境中進行快速熱退火(rapid thermal anneal；RTA)。界面氧化物層116之形成使得形成於其上之一高k介電層118能夠成核，高k介電層118包含介電常數大於氮化矽之介電常數(7.5)之一介電金屬氧化物。
高k介電層118可係藉由此項技術中眾所周知之方法形成，舉例而言，包含化學氣相沈積(chemical vapor deposition；CVD)、原子層沈積(ALD)、分子束沈積(molecular beam deposition；MBD)、脈衝雷射沈積(pulsed laser deposition；PLD)、液態源霧化化學沈積(liquid source misted chemical deposition；LSMCD)等。在一實例性實施例中，高k介電層118之介電金屬氧化物包含金屬及氧，且選擇地包含氮及/或矽。高k介電材料之特定實例包含(但不限於)：HfO2、ZrO2、La2O3、Al2O3、TiO2、SrTiO3、LaAlO3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、SrTiOxNy、 LaAlOxNy、Y2OxNy、其矽酸鹽、及其一合金。x之各值獨立地係為自0.5至3，且y之各值獨立地係為自0至2。高k介電層118之厚度可係為自約1奈米至約10奈米，且更具體而言係為自約1.5奈米至約3奈米。在形成高k介電層118之後，可執行一選擇性退火以使高k材料緻密化。
如上所示，將複合介電堆疊116/118之等效氧化物厚度及Tinv按比例縮小可在p型場效電晶體裝置中導致諸如負偏壓溫度不穩定性等效能問題，此係由於自習用TiN功函數金屬之氮併入Si/SiO2界面中。因此，第3圖例示在高k介電層118上形成一新穎p型場效電晶體功函數金屬層120。具體而言，金屬層120包含一鈦-鋁-碳-氧(TiAlCO)層，該TiAlCO層具有如下之一原子濃度範圍：對於鈦，10%至20%；對於鋁，10%至20%；對於碳，5%至15%；以及對於氧，45%至75%。p型場效電晶體功函數金屬層120可係例如使用原子層沈積被形成為約5奈米(nanometer；nm)或更小之一厚度，且具有處於約4.70電子伏特(electron volt；eV)至5.17電子伏特之範圍內，且更具體而言係約4.9電子伏特之一功函數。
使用TiAlCO作為p型場效電晶體裝置之一功函數設定金屬會提供一種防止氮致負偏壓溫度不穩定性劣化、同時亦選擇性地使p型場效電晶體裝置之等效氧化物厚度(Tinv)增加俾使n型場效電晶體裝置效能得以維持之解決方案。
在形成TiAlCO層120作為一功函數設定金屬之後，可接著形成閘極堆疊之一或多個剩餘金屬層122，如第4圖中所示。舉例而言，該一或多個金屬層可包含一潤濕氮化鈦沈積層、以及鋁、摻鈦鋁、鎢或銅其中之一或多者。在第5圖中，諸如藉由化學機械拋光(chemical mechanical polishing；CMP)將該結構平坦化，以界定一閘極後製或閘極取代電晶體裝 置。自此開始，可以現有之處理技術(例如，閘極端子、源極端子及汲極端子之矽化物觸點形成、上部層級佈線形成等)繼續。
在互補金屬氧化物半導體場效電晶體裝置處理之背景中，預期在為p型場效電晶體裝置及n型場效電晶體裝置二者移除虛設閘極之後且在形成界面層及高k層之後，可在n型場效電晶體功函數金屬之前或之後形成TiAlCO p型場效電晶體功函數金屬。在第6圖及第7圖之流程圖中概括各該實施例。
如第6圖中所示，一第一製程流程600始於在方塊602處以在一開口中形成一界面層及一高k層(例如SiO2/HfO2)，該開口係因移除虛設閘極材料而產生。此亦顯示於如上所述之第2圖中。於在方塊604中進行一選擇性沈積後退火之後，製程流程600繼續進行至方塊606以沈積TiAlCO p型場效電晶體功函數金屬層(亦參見第3圖)。在此實施例中，TiAlCO係首先在裝置之p型場效電晶體區域及n型場效電晶體區域二者上形成。出於圖案化目的，亦可在TiAlCO p型場效電晶體功函數金屬層上形成一選擇性TiN層，如方塊608中所示。
在方塊610中，如此項技術中所已知的那樣以微影方式對裝置進行圖案化，以自裝置之複數個n型場效電晶體部分移除TiAlCO p型場效電晶體功函數金屬層(及選用TiN層)。此後，在裝置之p型場效電晶體部分仍受保護之情形下，沈積n型場效電晶體功函數金屬，如方塊612中所示。舉例而言，適合之n型場效電晶體功函數金屬可包含TiN及TiAlC。在沈積n型場效電晶體功函數金屬之後，可如方塊614中所示使用一潤濕TiN沈積，以將在方塊616中填充之後續閘極金屬黏附至該功函數金屬(亦參見第4圖)。
另一選擇為，在第7圖中，一第二製程流程700始於在方塊702處以在一開口中形成一界面層及一高k層(例如SiO2/HfO2)，該開口係因移除虛設閘極材料而產生。同樣，此亦顯示於如上所述之第2圖中。於在方塊704中進行一選用沈積後退火之後，製程流程700繼續進行至方塊706以沈積n型場效電晶體功函數金屬層(例如，TiN、TiAlC)。在此實施例中，n型場效電晶體功函數金屬係首先在裝置之p型場效電晶體區域及n型場效電晶體區域二者上形成。出於圖案化目的，亦可在n型場效電晶體功函數金屬層上形成一選用TiN層，如方塊708中所示。
在方塊710中，如此項技術中所已知的那樣以微影方式對裝置進行圖案化，以自裝置之複數個p型場效電晶體部分移除n型場效電晶體功函數金屬層(及選用TiN層)。此後，在裝置之n型場效電晶體部分仍受保護之情形下，沈積TiAlCO p型場效電晶體功函數金屬層，如方塊712中所示。合適在沈積p型場效電晶體功函數金屬之後，可如方塊714中所示使用一濕式TiN沈積，以將在方塊716中填充之後續閘極金屬黏附至該功函數金屬。
儘管已參照一或多個較佳實施例闡述了本發明，但熟習此項技術者將理解，可作出各種改變，且可用等效物代替本發明之元件，此並不背離本發明之範疇。另外，可對本發明之教示作出諸多潤飾以適應一特定情形或材料，此並不背離本發明之本質範疇。因此，本發明並不意欲限於作為預期用於執行本發明之最佳方式而揭示之特定實施例，而是本發明將包含歸屬於隨附申請專利範圍之範疇內之所有實施例。
600‧‧‧製程流程、第一製程流程
602~616‧‧‧步驟

Claims (20)

  1. 一種形成一電晶體裝置之方法，該方法包含：在一基板上形成一界面層(interfacial layer)及一介電層；以及在該介電層上形成一功函數金屬層(workfunction metal layer)，該功函數金屬層包含一鈦-鋁-碳-氧(titanium-aluminum-carbon-oxygen；TiAlCO)層。
  2. 如請求項1所述之方法，其中該電晶體裝置係為一p型場效電晶體(p-type field effect transistor；PFET)裝置。
  3. 如請求項1所述之方法，其中該TiAlCO層具有如下之一原子濃度範圍：對於鈦，10%至20%；對於鋁，10%至20%；對於碳，5%至15%；以及對於氧，45%至75%。
  4. 如請求項3所述之方法，其中該TiAlCO層具有處於約4.70電子伏特(electron volt；eV)至5.17電子伏特之範圍內之一功函數。
  5. 如請求項3所述之方法，其中該TiAlCO層具有約4.9電子伏特之一功函數。
  6. 如請求項1所述之方法，其中該功函數金屬層係使用原子層沈積(atomic layer deposition；ALD)被形成為約5奈米(nanometer；nm)或更小之一厚度。
  7. 如請求項1所述之方法，更包含在該功函數金屬層上形成一閘極金屬層，藉此界定一閘極堆疊。
  8. 一種形成一電晶體裝置之方法，該方法包含：在一基板的一部分上形成一界面層及一介電層，該部分係對應於一 被移除虛設閘極結構；在該介電層上形成一p型場效電晶體(PFET)之功函數金屬層，該功函數金屬層包含一鈦-鋁-碳-氧(TiAlCO)層；以及在該p型場效電晶體功函數金屬層上形成一閘極金屬層，藉此界定一閘極堆疊。
  9. 如請求項8所述之方法，其中該TiAlCO層具有如下之一原子濃度範圍：對於鈦，10%至20%；對於鋁，10%至20%；對於碳，5%至15%；以及對於氧，45%至75%。
  10. 如請求項9所述之方法，其中該TiAlCO層具有處於約4.70電子伏特(eV)至5.17電子伏特之範圍內之一功函數。
  11. 如請求項9所述之方法，其中該TiAlCO層具有約4.9電子伏特之一功函數。
  12. 如請求項8所述之方法，其中該功函數金屬層係使用原子層沈積(ALD)被形成為約5奈米(nm)或更小之一厚度。
  13. 如請求項8所述之方法，更包含：自該基板之一n型場效電晶體(n-type field effect transistor；NFET)區域移除該TiAlCO層，並在該基板之該n型場效電晶體區域中形成一n型場效電晶體功函數金屬層。
  14. 如請求項13所述之方法，其中該p型場效電晶體功函數金屬層係在該n型場效電晶體功函數金屬層之前形成。
  15. 如請求項13所述之方法，其中該n型場效電晶體功函數金屬層係在該p型場效電晶體功函數金屬層之前形成。
  16. 一種電晶體裝置，包含：一界面層及一介電層，形成於一基板的一部分上，該部分對應於一被移除虛設閘極結構；一p型場效電晶體(PFET)功函數金屬層，形成於該介電層上，該功函數金屬層包含一鈦-鋁-碳-氧(TiAlCO)層；以及一閘極金屬層，形成於該p型場效電晶體功函數金屬層上，藉此界定一閘極堆疊。
  17. 如請求項16所述之裝置，其中該TiAlCO層具有如下之一原子濃度範圍：對於鈦，10%至20%；對於鋁，10%至20%；對於碳，5%至15%；以及對於氧，45%至75%。
  18. 如請求項17所述之裝置，其中該TiAlCO層具有處於約4.70電子伏特(eV)至5.17電子伏特之範圍內之一功函數。
  19. 如請求項17所述之裝置，其中該TiAlCO層具有約4.9電子伏特之一功函數。
  20. 如請求項16所述之裝置，其中該功函數金屬具有約5奈米(nm)或更小之一厚度。
TW104139900A 2014-12-08 2015-11-30 電晶體裝置及其成型方法 TWI671806B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/563,009 US9449887B2 (en) 2014-12-08 2014-12-08 Method of forming replacement gate PFET having TiALCO layer for improved NBTI performance
US14/563,009 2014-12-08

Publications (2)

Publication Number Publication Date
TW201631640A true TW201631640A (zh) 2016-09-01
TWI671806B TWI671806B (zh) 2019-09-11

Family

ID=56095058

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104139900A TWI671806B (zh) 2014-12-08 2015-11-30 電晶體裝置及其成型方法

Country Status (3)

Country Link
US (1) US9449887B2 (zh)
TW (1) TWI671806B (zh)
WO (1) WO2016094126A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9761699B2 (en) * 2015-01-28 2017-09-12 International Business Machines Corporation Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
US9583486B1 (en) * 2015-11-19 2017-02-28 International Business Machines Corporation Stable work function for narrow-pitch devices
WO2019231489A1 (en) 2018-05-29 2019-12-05 Micron Technology, Inc. Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
US10971407B2 (en) 2019-06-05 2021-04-06 International Business Machines Corporation Method of forming a complementary metal oxide semiconductor device having fin field effect transistors with a common metal gate
US11646311B2 (en) * 2019-09-23 2023-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of fabricating the same
CN113401904B (zh) * 2021-05-25 2023-08-01 西安交通大学 氧原子原位掺杂MAX相和原位掺杂MXene柔性膜电极材料及其制备方法和应用

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7030430B2 (en) 2003-08-15 2006-04-18 Intel Corporation Transition metal alloys for use as a gate electrode and devices incorporating these alloys
US7075161B2 (en) * 2003-10-23 2006-07-11 Agilent Technologies, Inc. Apparatus and method for making a low capacitance artificial nanopore
US7105889B2 (en) 2004-06-04 2006-09-12 International Business Machines Corporation Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics
US7242055B2 (en) 2004-11-15 2007-07-10 International Business Machines Corporation Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide
US7667277B2 (en) 2005-01-13 2010-02-23 International Business Machines Corporation TiC as a thermally stable p-metal carbide on high k SiO2 gate stacks
JP5070702B2 (ja) 2006-01-19 2012-11-14 富士通セミコンダクター株式会社 半導体装置の製造方法及び製造装置
US20080237683A1 (en) * 2007-03-30 2008-10-02 Min Kyu S High-k trilayer dielectric device and methods
US7855153B2 (en) * 2008-02-08 2010-12-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8003507B2 (en) 2008-08-18 2011-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of integrating high-K/metal gate in CMOS process flow
TWI536451B (zh) 2010-04-26 2016-06-01 應用材料股份有限公司 使用具金屬系前驅物之化學氣相沉積與原子層沉積製程之ｎ型金氧半導體金屬閘極材料、製造方法及設備
US8847333B2 (en) 2011-09-01 2014-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Techniques providing metal gate devices with multiple barrier layers
US8704280B2 (en) 2011-09-22 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with strained channels induced by high-k capping metal layers
US20130087856A1 (en) 2011-10-05 2013-04-11 International Business Machines Corporation Effective Work Function Modulation by Metal Thickness and Nitrogen Ratio for a Last Approach CMOS Gate
CN104081545A (zh) * 2011-12-01 2014-10-01 夸克星有限责任公司 固态照明装置及其制造方法
US8716118B2 (en) 2012-01-06 2014-05-06 International Business Machines Corporation Replacement gate structure for transistor with a high-K gate stack
US20130264680A1 (en) * 2012-04-05 2013-10-10 Uchicago Argonne Llc NANOLAMINATES OF Al2O3/TiO2 WITH GIANT DIELECTRIC CONSTANT LOW-LEAKAGE-LOW LOSS-EXTENDED FREQUENCY OPERATION FOR NEW-GENERATION NANOELECTRONICS AND ENERGY STORAGE DEVICES
KR101909205B1 (ko) 2012-04-20 2018-10-17 삼성전자 주식회사 핀형 전계 효과 트랜지스터를 구비한 반도체 소자
CN103855006A (zh) * 2012-11-30 2014-06-11 中国科学院微电子研究所 半导体器件的制造方法
US9059315B2 (en) 2013-01-02 2015-06-16 International Business Machines Corporation Concurrently forming nFET and pFET gate dielectric layers
US9190409B2 (en) 2013-02-25 2015-11-17 Renesas Electronics Corporation Replacement metal gate transistor with controlled threshold voltage
KR102055379B1 (ko) * 2013-08-08 2019-12-13 삼성전자 주식회사 트라이-게이트를 포함하는 반도체 소자 및 그 제조 방법
KR102212267B1 (ko) * 2014-03-19 2021-02-04 삼성전자주식회사 반도체 장치 및 그 제조 방법
KR102218547B1 (ko) * 2014-06-26 2021-02-22 에스케이하이닉스 주식회사 반도체장치 및 그 제조 방법
KR102262887B1 (ko) * 2014-07-21 2021-06-08 삼성전자주식회사 반도체 장치 및 그 제조 방법

Also Published As

Publication number Publication date
US9449887B2 (en) 2016-09-20
US20160163814A1 (en) 2016-06-09
TWI671806B (zh) 2019-09-11
WO2016094126A1 (en) 2016-06-16

Similar Documents

Publication Publication Date Title
US8530974B2 (en) CMOS structure having multiple threshold voltage devices
US9252229B2 (en) Inversion thickness reduction in high-k gate stacks formed by replacement gate processes
US10217745B2 (en) High-K gate dielectric and metal gate conductor stack for fin-type field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material
US10930566B2 (en) Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments
US20160163603A1 (en) Pfet gate stack materials having improved threshold voltage, mobility and nbti performance
TWI476822B (zh) 金屬高介電常數場效電晶體之雙金屬與雙介電質整合
US6784101B1 (en) Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation
TWI671806B (zh) 電晶體裝置及其成型方法
US20080237663A1 (en) Fabrication of self-aligned gallium arsenide mosfets using damascene gate methods
US9343372B1 (en) Metal stack for reduced gate resistance
US8026539B2 (en) Metal oxide semiconductor devices having doped silicon-compromising capping layers and methods for fabricating the same
US9443771B1 (en) Methods to thin down RMG sidewall layers for scalability of gate-last planar CMOS and FinFET technology
US8685817B1 (en) Metal gate structures for CMOS transistor devices having reduced parasitic capacitance
US9362282B1 (en) High-K gate dielectric and metal gate conductor stack for planar field effect transistors formed on type III-V semiconductor material and silicon germanium semiconductor material
US20170309723A1 (en) Structures and methods for equivalent oxide thickness scaling on silicon germanium channel or iii-v channel of semiconductor device
JP2004247341A (ja) 半導体装置
JP2011044576A (ja) 半導体装置および半導体装置の製造方法
KR20220016788A (ko) 게이트 올 어라운드 나노시트 i/o 디바이스에 대한 등각 산화
US20230162983A1 (en) Semiconductor devices with metal intercalated high-k capping
US20130328135A1 (en) Preventing fully silicided formation in high-k metal gate processing
US9337296B2 (en) Integrated circuits having a metal gate structure and methods for fabricating the same