TW201629504A - Detection circuit - Google Patents

Detection circuit Download PDF

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TW201629504A
TW201629504A TW105101970A TW105101970A TW201629504A TW 201629504 A TW201629504 A TW 201629504A TW 105101970 A TW105101970 A TW 105101970A TW 105101970 A TW105101970 A TW 105101970A TW 201629504 A TW201629504 A TW 201629504A
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transistor
circuit
voltage
output
load
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TW105101970A
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Chinese (zh)
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TWI666457B (en
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Masakazu Sugiura
Atsushi Igarashi
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Sii Semiconductor Corp
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections

Abstract

Provided is a detection circuit configured to avoid erroneous detection that may occur immediately after a detection circuit is powered on. The detection circuit includes: an output transistor connected between a voltage input terminal and a voltage output terminal; and a load open-circuit detection circuit configured to detect an open circuit of a load connected to the voltage output terminal, in which an output circuit of the load open-circuit detection circuit includes a first transistor and a second transistor connected in series, the first transistor having a gate connected to the output transistor in common, the second transistor having a gate to which a signal indicating that the open-circuit of the load is detected, and in which the first transistor is in an off state when the output transistor is in an off state.

Description

檢測電路Detection circuit

本發明是有關於一種對所連接的負載的開路(open)進行檢測的檢測電路。The present invention relates to a detection circuit for detecting an open of a connected load.

圖6是以往的檢測電路。以往的檢測電路包括:電壓輸入端子401、電壓輸出端子402、輸出電晶體(transistor)403、控制電路404、對連接於電壓輸出端子402的負載的開路進行檢測的負載開路檢測電路405、及負載開路檢測電路405的輸出端子406。Fig. 6 is a conventional detection circuit. The conventional detection circuit includes a voltage input terminal 401, a voltage output terminal 402, an output transistor 403, a control circuit 404, a load open circuit detecting circuit 405 that detects an open circuit of a load connected to the voltage output terminal 402, and a load. The output terminal 406 of the open circuit detection circuit 405.

控制電路404對輸出電晶體403進行通斷(ON OFF)控制。負載開路檢測電路405在對連接於電壓輸出端子402的負載的開路進行檢測時,將檢測信號輸出至輸出端子406。The control circuit 404 performs ON/OFF control of the output transistor 403. The load open circuit detecting circuit 405 outputs a detection signal to the output terminal 406 when detecting an open circuit of the load connected to the voltage output terminal 402.

在負載開路檢測電路405中,為了對連接於電壓輸出端子402的負載的開路進行檢測,常使用對輸出電晶體403的電流進行監控的方法。例如,在電壓輸入端子401與輸出電晶體403之間設置電阻410,利用在其兩端產生的電壓來進行判定。在連接於電壓輸出端子402的負載的開路狀態下,應無電流流經輸出電晶體403,因此如上所述般對連接於電壓輸出端子402的負載的開路進行檢測。 現有技術文獻 專利文獻In the load open circuit detecting circuit 405, in order to detect an open circuit of a load connected to the voltage output terminal 402, a method of monitoring the current of the output transistor 403 is often used. For example, a resistor 410 is provided between the voltage input terminal 401 and the output transistor 403, and the voltage generated at both ends thereof is used for determination. In the open state of the load connected to the voltage output terminal 402, no current flows through the output transistor 403, so the open circuit of the load connected to the voltage output terminal 402 is detected as described above. Prior art literature

專利文獻1:日本專利特開平6-289087號公報 [發明所欲解決之課題]Patent Document 1: Japanese Patent Laid-Open No. Hei 6-289087 [Problem to be Solved by the Invention]

輸出電晶體403的元件尺寸大,輸入容量亦大,以便對應於連接至電壓輸出端子402的負載來使大的電流流過。要對輸出電晶體403的大的輸入容量進行充放電以進行通斷控制,在物理上需要時間,因此在檢測電路的電源啟動時,輸出電晶體403難以立即成為導通狀態。因而,在檢測電路的電源剛剛啟動之後,輸出電晶體403呈斷開狀態,儘管實際上並未成為負載的開路狀態,但電阻410中卻未產生電壓。The output transistor 403 has a large component size and a large input capacity to allow a large current to flow corresponding to the load connected to the voltage output terminal 402. It is necessary to charge and discharge the large input capacity of the output transistor 403 for on-off control, and physical time is required. Therefore, when the power supply of the detection circuit is activated, the output transistor 403 is difficult to be immediately turned on. Therefore, after the power supply of the detecting circuit has just started, the output transistor 403 is in an off state, and although it is not actually in an open state of the load, no voltage is generated in the resistor 410.

因而,圖6所示的以往的檢測電路存在下述問題:在檢測電路的電源剛剛啟動之後,在電阻410上產生的電壓小,負載開路檢測電路405會產生誤判定。Therefore, the conventional detection circuit shown in FIG. 6 has a problem that the voltage generated in the resistor 410 is small after the power supply of the detection circuit is started, and the load open circuit detection circuit 405 generates an erroneous determination.

本發明是為了消除以上所述的問題而創作,提供一種檢測電路,其避免了檢測電路的電源剛剛啟動之後的誤檢測。 [解決課題之手段]The present invention has been made in order to eliminate the above-mentioned problems, and provides a detecting circuit which avoids erroneous detection immediately after the power of the detecting circuit is started. [Means for solving the problem]

為了解決以往的課題,本發明的檢測電路採用了如下所述的結構。 檢測電路構成為:包括設置於電壓輸入端子與電壓輸出端子之間的輸出電晶體以及對連接於電壓輸出端子的負載的開路進行檢測的負載開路檢測電路,負載開路檢測電路的輸出電路具有第1電晶體與第2電晶體串聯連接的結構,所述第1電晶體的閘極共通地與輸出電晶體連接,所述第2電晶體的閘極輸入有對負載開路進行檢測的信號,在輸出電晶體斷開時,第1電晶體斷開。 (發明的效果)In order to solve the conventional problems, the detection circuit of the present invention adopts the configuration described below. The detection circuit is configured to include an output transistor provided between the voltage input terminal and the voltage output terminal, and a load open circuit detecting circuit for detecting an open circuit of the load connected to the voltage output terminal, and the output circuit of the load open circuit detecting circuit has the first a structure in which the transistor and the second transistor are connected in series, wherein a gate of the first transistor is connected in common to an output transistor, and a gate of the second transistor receives a signal for detecting an open load, and outputs When the transistor is turned off, the first transistor is turned off. (Effect of the invention)

根據本發明的檢測電路,可提供一種避免了電源剛剛啟動之後的誤檢測的檢測電路。According to the detecting circuit of the present invention, it is possible to provide a detecting circuit which avoids erroneous detection immediately after the power source is turned on.

以下,參照圖式來說明本實施形態。 圖1是表示本實施形態的檢測電路的說明圖。 本實施形態的檢測電路包括電壓輸入端子401、電壓輸出端子402、連接於電壓輸入端子401與電壓輸出端子402之間的輸出電晶體403、控制電路404、負載開路檢測電路405、負載開路檢測電路405的輸出端子406及電阻410。負載開路檢測電路405對連接於電壓輸出端子402的負載的開路進行檢測。為了對輸出電晶體403的電流進行監控,電阻410產生與該電流相應的電壓。Hereinafter, the present embodiment will be described with reference to the drawings. Fig. 1 is an explanatory view showing a detecting circuit of the embodiment. The detection circuit of the present embodiment includes a voltage input terminal 401, a voltage output terminal 402, an output transistor 403 connected between the voltage input terminal 401 and the voltage output terminal 402, a control circuit 404, a load open circuit detecting circuit 405, and a load open circuit detecting circuit. Output terminal 406 and resistor 410 of 405. The load open circuit detecting circuit 405 detects an open circuit of the load connected to the voltage output terminal 402. In order to monitor the current of the output transistor 403, the resistor 410 generates a voltage corresponding to the current.

負載開路檢測電路405包括電壓電路101、電壓源102、比較器103、電晶體104、電晶體105及電流源106。電壓電路101產生VSS基準的電壓VSIG,該VSS基準的電壓VSIG是基於在電阻410的兩端產生的電壓。電壓源102產生基準電壓VREF。比較器103對電壓VSIG與基準電壓VREF進行比較,並控制電晶體104的通斷。電晶體105的閘極共通地與輸出電晶體403連接,且電晶體105與電晶體104串聯連接。電流源106與串聯連接的電晶體104及電晶體105串聯連接,其連接點與輸出端子406連接。電晶體104及電晶體105與電流源106構成負載開路檢測電路405的輸出電路。The load open circuit detection circuit 405 includes a voltage circuit 101, a voltage source 102, a comparator 103, a transistor 104, a transistor 105, and a current source 106. The voltage circuit 101 generates a voltage VSIG of a VSS reference which is based on a voltage generated across the resistor 410. Voltage source 102 produces a reference voltage VREF. The comparator 103 compares the voltage VSIG with the reference voltage VREF and controls the on and off of the transistor 104. The gate of the transistor 105 is commonly connected to the output transistor 403, and the transistor 105 is connected in series with the transistor 104. The current source 106 is connected in series with the transistor 104 and the transistor 105 connected in series, and its connection point is connected to the output terminal 406. The transistor 104 and the transistor 105 and the current source 106 constitute an output circuit of the load open circuit detecting circuit 405.

圖5是表示電壓電路101的一例的電路圖。圖5所示的電壓電路101包括輸入端子300及輸入端子301、放大器302、電阻304及電阻305、電晶體303以及輸出端子306。輸入端子300連接電阻410的電壓輸入端子401側的端子。輸入端子301連接電阻410的另一個端子。FIG. 5 is a circuit diagram showing an example of the voltage circuit 101. The voltage circuit 101 shown in FIG. 5 includes an input terminal 300 and an input terminal 301, an amplifier 302, a resistor 304 and a resistor 305, a transistor 303, and an output terminal 306. The input terminal 300 is connected to the terminal of the voltage input terminal 401 of the resistor 410. The input terminal 301 is connected to the other terminal of the resistor 410.

電壓電路101將如下電壓作為VSS基準的電壓VSIG而輸出至端子306,所述電壓是以電阻比使以電壓輸入端子401的電壓為基準的電阻410兩端的電壓倍增而成的。 另外,電壓電路101只要為產生VSS基準的電壓VSIG的結構即可,並不限定於該電路,所述VSS基準的電壓VSIG是基於電阻410兩端所產生的電壓。The voltage circuit 101 outputs a voltage VSIG which is a VSS reference to the terminal 306 which multiplies the voltage across the resistor 410 based on the voltage of the voltage input terminal 401 by the resistance ratio. In addition, the voltage circuit 101 is not limited to this configuration as long as it is configured to generate the voltage VSIG of the VSS reference, and the voltage VSIG of the VSS reference is based on the voltage generated across the resistor 410.

接下來,對本實施形態的檢測電路的動作進行說明。控制電路404對輸出電晶體403進行通斷控制。負載開路檢測電路405在對連接於電壓輸出端子402的負載的開路進行檢測時,將檢測信號(高(H)位準(level))輸出至輸出端子406。由於電阻410中產生的電壓是基於輸出電晶體403的電流,因此在連接於電壓輸出端子402的負載的開路狀態下,應無電流流經輸出電晶體403,因此藉由判定電阻410中產生的電壓為某值以下,來檢測負載的開路。Next, the operation of the detection circuit of this embodiment will be described. The control circuit 404 performs on-off control of the output transistor 403. The load open circuit detecting circuit 405 outputs a detection signal (high (H) level) to the output terminal 406 when detecting an open circuit of the load connected to the voltage output terminal 402. Since the voltage generated in the resistor 410 is based on the current of the output transistor 403, no current should flow through the output transistor 403 in the open state of the load connected to the voltage output terminal 402, and thus by determining the resistance 410 The voltage is below a certain value to detect the open circuit of the load.

電壓VSIG是基於電阻410中產生的電壓,因此當電阻410中產生的電壓小時,該電壓VSIG小。因而,在連接於電壓輸出端子402的負載的開路狀態下,電壓VSIG變小。比較器103在判定為VSIG<VREF時,對電晶體104進行導通控制。The voltage VSIG is based on the voltage generated in the resistor 410, so when the voltage generated in the resistor 410 is small, the voltage VSIG is small. Therefore, in the open state of the load connected to the voltage output terminal 402, the voltage VSIG becomes small. When the comparator 103 determines that VSIG < VREF, it conducts conduction control of the transistor 104.

輸出電晶體403的元件尺寸大,輸入容量亦大,以便使大的電流流過,因此在檢測電路的電源啟動時不會立即導通。此處,電晶體105是與輸出電晶體403同樣地設定為在檢測電路的電源啟動時成為斷開狀態。即,在檢測電路的電源啟動時且輸出電晶體403為斷開狀態時,電晶體105亦斷開,因此即使電晶體104藉由比較器103的輸出而導通,檢測信號亦不會被輸出至負載開路檢測電路405的輸出端子406。 如以上所說明般,根據本實施形態的檢測電路,可提供一種避免了檢測電路的電源剛剛啟動之後的誤檢測的檢測電路。The output transistor 403 has a large component size and a large input capacity so that a large current flows, so that the power of the detecting circuit is not turned on immediately when the power is turned on. Here, the transistor 105 is set to be in an off state when the power of the detection circuit is activated, similarly to the output transistor 403. That is, when the power supply of the detection circuit is activated and the output transistor 403 is in the off state, the transistor 105 is also turned off, so even if the transistor 104 is turned on by the output of the comparator 103, the detection signal is not outputted to The output terminal 406 of the load open circuit detection circuit 405. As described above, according to the detecting circuit of the present embodiment, it is possible to provide a detecting circuit that avoids erroneous detection immediately after the power supply of the detecting circuit is started.

另外,應明確的是,電晶體105只要在檢測電路的電源剛剛啟動之後根據控制電路404的控制信號而進行與輸出電晶體403相同的動作即可,其結構或特性並不受限定。例如,電晶體105為與輸出電晶體403相同的種類,且具有相同的臨限值。In addition, it should be understood that the transistor 105 may perform the same operation as the output transistor 403 according to the control signal of the control circuit 404 immediately after the power supply of the detection circuit is started, and its configuration or characteristics are not limited. For example, transistor 105 is of the same type as output transistor 403 and has the same threshold.

而且,電晶體105是採用單個的電晶體,但亦可藉由向電晶體105的源極(source)插入進行了二極體(diode)連接的電晶體,或者採用達林頓(Darlington)連接的結構,而使電晶體105的臨限值高於輸出電晶體403。Moreover, the transistor 105 is a single transistor, but can also be inserted into a diode that is diode-connected to the source of the transistor 105, or a Darlington connection. The structure is such that the threshold of the transistor 105 is higher than that of the output transistor 403.

而且,電晶體105未必需要將閘極共通地與輸出電晶體403連接,亦可在兩者之間隔著電壓位準移位(level shift)段。電壓位準移位段例如只要包含源極隨耦(source follower)放大段即可。此時,可明確的是,比起輸出電晶體403,電晶體105的閘極/源極間電壓的大小更小,因此可更確實地避免誤檢測。Moreover, the transistor 105 does not necessarily need to connect the gates to the output transistor 403 in common, or may be spaced apart by a voltage level shift. The voltage level shifting section may be, for example, as long as it includes a source follower amplification section. At this time, it is clear that the magnitude of the gate/source voltage of the transistor 105 is smaller than that of the output transistor 403, so that erroneous detection can be more reliably avoided.

此處,圖1的檢測電路在控制電路404斷開輸出電晶體403時,無法輸出表示負載的開路狀態的信號。例如,當負載開路檢測電路405檢測到負載的開路時,有時周圍溫度會變高,而控制電路404對輸出電晶體403進行斷開控制。Here, the detection circuit of FIG. 1 cannot output a signal indicating the open state of the load when the control circuit 404 turns off the output transistor 403. For example, when the load open circuit detecting circuit 405 detects an open circuit of the load, the ambient temperature may become high, and the control circuit 404 performs off control of the output transistor 403.

圖2是表示本實施形態的檢測電路的另一例的說明圖。與圖1的不同之處在於,與電晶體105並聯地新包括由控制電路404所控制的電晶體110。控制電路404例如基於如上所述的狀態來使電晶體110導通,藉此可將電晶體105無效化,因此即使輸出電晶體403為斷開狀態,亦可向負載開路檢測電路405的輸出端子406輸出檢測信號。Fig. 2 is an explanatory view showing another example of the detecting circuit of the embodiment. The difference from FIG. 1 is that the transistor 110 controlled by the control circuit 404 is newly included in parallel with the transistor 105. The control circuit 404 turns on the transistor 110 based on, for example, the state described above, whereby the transistor 105 can be disabled, so that even if the output transistor 403 is in the off state, the output terminal 406 of the load open circuit detecting circuit 405 can be turned on. The detection signal is output.

圖3是表示本實施形態的檢測電路的另一例的說明圖。與圖1的檢測電路的不同之處在於,負載開路檢測電路405的輸出電路包含串聯連接的電晶體104及電流源106、串聯連接的電晶體105及電流源107、以及及閘電路(AND circuit)201。以此方式構成也可獲得與圖1的檢測電路同樣的效果。Fig. 3 is an explanatory view showing another example of the detecting circuit of the embodiment. The difference from the detection circuit of FIG. 1 is that the output circuit of the load open circuit detection circuit 405 includes a transistor 104 and a current source 106 connected in series, a transistor 105 and a current source 107 connected in series, and an AND circuit. ) 201. The same effect as the detection circuit of Fig. 1 can also be obtained by this configuration.

另外,可明確的是,只要與由輸出被強制固定的邏輯閘或由其組合構成電路的條件相關,例如即使由使用或閘電路(OR circuit)的適當電路構成,也具有同樣的效果。Further, it is clear that the same effect can be obtained as long as it is constituted by a suitable circuit that uses an OR circuit, as long as it is related to a condition that a circuit is forcedly fixed by an output or a combination thereof.

圖4是表示本實施形態的檢測電路的另一例的說明圖。與圖2的電路同樣,是與電晶體105並聯地包括電晶體202的電路,可獲得與圖2的電路同樣的效果。Fig. 4 is an explanatory view showing another example of the detecting circuit of the embodiment. Similarly to the circuit of Fig. 2, a circuit including the transistor 202 in parallel with the transistor 105 can obtain the same effects as the circuit of Fig. 2.

另外,以圖1至圖4所示的電路對負載開路檢測電路405進行了說明,但這只是一例,只要可獲得同樣的效果,實施形態便不受限定。 以上的說明中,為了方便,將各輸出的位準以H位準或低(L)位準來規定,但無須特別限定。Further, the load open circuit detecting circuit 405 has been described with reference to the circuits shown in Figs. 1 to 4, but this is only an example, and the embodiment is not limited as long as the same effect can be obtained. In the above description, the level of each output is defined by the H level or the low (L) level for convenience, but it is not particularly limited.

101、102、301‧‧‧電壓源
103‧‧‧比較器
104、105、110、202、303、403‧‧‧電晶體
106、107‧‧‧電流源
201‧‧‧及閘電路
300‧‧‧輸入端子
302‧‧‧放大器
304、305、410‧‧‧電阻
306、406‧‧‧輸出端子
401‧‧‧電壓輸入端子
402‧‧‧電壓輸出端子
404‧‧‧控制電路
405‧‧‧負載開路檢測電路
VSIG‧‧‧電壓
VREF‧‧‧基準電壓
101, 102, 301‧‧‧ voltage source
103‧‧‧ comparator
104, 105, 110, 202, 303, 403‧‧‧ transistors
106, 107‧‧‧ Current source
201‧‧‧ and gate circuit
300‧‧‧Input terminal
302‧‧‧Amplifier
304, 305, 410‧‧‧ resistance
306, 406‧‧‧ output terminals
401‧‧‧Voltage input terminal
402‧‧‧Voltage output terminal
404‧‧‧Control circuit
405‧‧‧Load open circuit detection circuit
VSIG‧‧‧ voltage
VREF‧‧‧ reference voltage

圖1是表示本實施形態的檢測電路的說明圖。 圖2是表示本實施形態的檢測電路的另一例的說明圖。 圖3是表示本實施形態的檢測電路的另一例的說明圖。 圖4是表示本實施形態的檢測電路的另一例的說明圖。 圖5是表示本實施形態的檢測電路的電壓電路的一例的說明圖。 圖6是表示以往的檢測電路的說明圖。Fig. 1 is an explanatory view showing a detecting circuit of the embodiment. Fig. 2 is an explanatory view showing another example of the detecting circuit of the embodiment. Fig. 3 is an explanatory view showing another example of the detecting circuit of the embodiment. Fig. 4 is an explanatory view showing another example of the detecting circuit of the embodiment. FIG. 5 is an explanatory diagram showing an example of a voltage circuit of the detection circuit of the embodiment. Fig. 6 is an explanatory view showing a conventional detecting circuit.

101‧‧‧電壓電路 101‧‧‧Voltage circuit

102‧‧‧電壓源 102‧‧‧voltage source

103‧‧‧比較器 103‧‧‧ comparator

104、105‧‧‧電晶體 104, 105‧‧‧Optoelectronics

106‧‧‧電流源 106‧‧‧current source

401‧‧‧電壓輸入端子 401‧‧‧Voltage input terminal

402‧‧‧電壓輸出端子 402‧‧‧Voltage output terminal

403‧‧‧輸出電晶體 403‧‧‧Output transistor

404‧‧‧控制電路 404‧‧‧Control circuit

405‧‧‧負載開路檢測電路 405‧‧‧Load open circuit detection circuit

406‧‧‧輸出端子 406‧‧‧Output terminal

410‧‧‧電阻 410‧‧‧resistance

VSIG‧‧‧電壓 VSIG‧‧‧ voltage

VREF‧‧‧基準電壓 VREF‧‧‧ reference voltage

Claims (5)

一種檢測電路,包括電壓輸入端子、電壓輸出端子、設置於所述電壓輸入端子與所述電壓輸出端子之間的輸出電晶體、控制所述輸出電晶體的控制電路以及對連接於所述電壓輸出端子的負載的開路進行檢測的負載開路檢測電路,所述檢測電路的特徵在於, 所述負載開路檢測電路的輸出電路具有第1電晶體與第2電晶體串聯連接的結構,所述第1電晶體的閘極共通地與所述輸出電晶體連接,所述第2電晶體的閘極輸入有對負載開路進行檢測的信號, 在所述輸出電晶體斷開時,所述第1電晶體斷開。A detection circuit includes a voltage input terminal, a voltage output terminal, an output transistor disposed between the voltage input terminal and the voltage output terminal, a control circuit for controlling the output transistor, and a pair connected to the voltage output A load open circuit detecting circuit for detecting an open circuit of a load of the terminal, wherein the output circuit of the load open circuit detecting circuit has a structure in which a first transistor and a second transistor are connected in series, and the first power a gate of the crystal is commonly connected to the output transistor, and a gate of the second transistor has a signal for detecting an open circuit of the load, and when the output transistor is disconnected, the first transistor is broken open. 如申請專利範圍第1項所述的檢測電路,其中 所述第1電晶體是與所述輸出電晶體為同一種類且為相同臨限值或更高臨限值的電晶體。The detecting circuit according to claim 1, wherein the first transistor is a transistor of the same type as the output transistor and having the same threshold or a higher threshold. 如申請專利範圍第1項所述的檢測電路,其中 所述輸出電晶體的閘極與所述第1電晶體的閘極經由電壓位準移位段而連接。The detecting circuit according to claim 1, wherein the gate of the output transistor and the gate of the first transistor are connected via a voltage level shifting section. 如申請專利範圍第3項所述的檢測電路,其中 所述電壓位準移位段為源極隨耦放大段。The detection circuit of claim 3, wherein the voltage level shifting segment is a source follower amplification segment. 如申請專利範圍第1項至第4項中任一項所述的檢測電路,包括: 第3電晶體,與所述第1電晶體並聯地由所述控制電路進行控制。The detection circuit according to any one of claims 1 to 4, further comprising: a third transistor controlled by the control circuit in parallel with the first transistor.
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