TW201624997A - Mixed format media transmission systems and methods - Google Patents

Abstract

Systems and methods for operating cameras are described. An image signal received from an image sensor can be processed as a plurality of video signals representative of the image signal. An encoder may combine baseband and digital video signals in an output signal for transmission over a cable. The video signals may include substantially isochronous baseband and digital video signals. The baseband video signal can comprise a standard definition analog video signal and the digital video signal may be modulated before combining with the baseband video signal and/or transmitting wirelessly. The digital video signal may be a compressed high definition digital video signal. A decoder demodulates an upstream signal to obtain a control signal for controlling the position and orientation of the camera and content of the baseband and digital video signals.

Description

System and method for mixed format media transmission

The present invention is generally directed to multimedia transmission systems and, more particularly, to systems and methods for transmitting high quality digital video and standard picture quality analog video over a single cable.

The present invention claims priority from US Patent Application Serial No. 12/363,669, entitled "Mixed Format Media Transmission Systems and Methods", issued on January 30, 2009, and claims the name of "SLOC Analog Equalizer For" on June 17, 2009. Priority of US Provisional Patent Application No. 61/187,970 to Baseband Video Signal, and claiming a US Provisional Patent Application entitled "A Method For Constellation Detection In A Multi-Mode QAM Communications System" on June 17, 2009 Priority to 61/187,977, and claims priority to US Provisional Patent Application No. 61/187,980, entitled "Novel Carrier Phase Offset Correction For A QAM System", June 17, 2009, and claims June 2009 Apply for the US Provisional Patent Application No. 61/187,986 entitled "Novel Frame Structure For A QAM System" on the 17th </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

With the advent of digital broadcast television and streaming video technology, various video cameras, monitors and video recorders with high resolution and advanced functions have become available. Today's closed circuit television (CCTV) systems can provide high quality video output and compressed digital video signals for applications such as business location monitoring, access control and remote monitoring of facilities. However, legacy systems are still in use, and standard picture quality analog video signals have been widely used and continue to be used during the transition to full digital, high quality systems. In particular, a coaxial cable (coax) has been deployed to carry signals from a CCTV camera to a monitoring station. Some deployed CCTV cameras transmit compressed video signals over a local area network (or wide area network), and such cameras can use the Internet Protocol (IP) as a communication method to transmit compressed video signals.

Figure 1 illustrates a conventional system that uses coax to carry standard picture quality analog video. A basic analog camera 10 typically produces a composite video baseband signal (CVBS) that can be transmitted up to 300 meters using coax 11. A video recording system is generally provided for a CVBS signal to a digital video recorder (DVR) 12 that often includes a CVBS that records a digital format. A conventional monitor 14 can be connected to the DVR 12 to simultaneously display the standard Quasi-picture quality analog video, which has roughly one resolution of 720x480 pixels.

The digital camera 16 can replace the analog camera 10 in some applications. The digital camera 16 can support a Serial Digital Interface (SDI), which is used to transmit uncompressed standard quality digital video to the DVR 12 via coax 17 at approximately 270 Mbps.

Figure 2 illustrates a conventional method of transmitting high quality video (1920 x 1080 pixels) in current development systems. First, a digital camera 20 can support a high quality serial digital interface (HD-SDI) that can be used to transmit uncompressed high quality digital video to the DVR 22 over a coax 21 at a rate of 1.5 Gbps. The cable distance supported at this high transmission rate is up to 100 meters. Second, an IP-based, high-definition (HD) camera 24 can generate a compressed digital HD video signal over a 100 Mbps Ethernet network using a standard Category 5 (CAT5) twisted pair cable 25 to a distance of 100 meters. The signal is received and recorded by a DVR 22 for non-immediate playback. The existing coax 26 can be used to transmit video from camera 24 to a DVR 22 using CAT5 to coax bridging modems 27 and 29 or other switching devices. The use of the network to cause the camera to transmit digital video allows these systems to add some upstream communications, typically control and audio signals 28.

Certain embodiments of the present invention provide cameras and systems and methods of operating the cameras. A processor can receive an image signal from an image sensor and generate a plurality of video signals representative of the image signal. One decoding The device is configured to combine the baseband video signal and the digital video signal into an output signal for transmission through a cable. The video signals may include a baseband video signal and a digital video signal and are substantially isochronous. The camera operates as a closed-circuit high-definition TV camera.

In accordance with certain aspects of the present invention, the baseband video signal can include a standard picture quality analog video signal and the digital video signal can be modulated prior to combining with the baseband video signal. The digital video signal can include a compressed high quality digital video signal. The frame rate of a digital video signal may be less than the frame rate of the image signal, especially when a video signal is modulated by a video recorder.

In some embodiments, a decoder is configured to demodulate an uplink signal from a transmission cable used to carry downlink video or received from a wireless communication network. The demodulated uplink signal may include a control signal including a signal for controlling the position and orientation of the camera to control the generation of the baseband video signal and the digital video signal by the processor and select a portion of the image signal for encoding as a fundamental frequency. Video signal. The control signals may also include a signal to select a portion of the image signal to encode as a digital video signal and an audio signal for driving the audio output of a camera such as a speaker.

Certain embodiments of the present invention provide methods of transmitting video images. The method may include dividing a video signal from a high-definition imaging device into a frequency division multiplexing process to obtain a modulated digital signal, and combining the modulated digital signal with a fundamental frequency analog signal representing the video signal to generate An output signal and simultaneously transmitting the output signal to a monitor and Digital video storage device. In some such embodiments, the monitor displays a baseband analog representation representative of the video signal and/or the digital video memory uses a digital video recorder to record a high quality frame sequence captured from the modulated digital signal. . The digital video signal can be compressed.

In some embodiments, transmitting the output signal includes providing an output signal to a coaxial cable and/or to a wireless transmitter. One of the input signals received from the coaxial cable or a wireless network can be demodulated to obtain a control signal. The baseband analog signal can be generated by encoding a portion of the video signal in a composite video signal, and the portion of the video signal to be encoded in the composite video signal can be controlled using the control signal. This control signal controls the position of the camera. Demodulating the input signal can additionally generate an audio signal from the input signal.

Certain embodiments of the present invention provide systems and methods for operating a camera. A processor can receive an image signal from an image sensor and generate a plurality of video signals, the control logic can be configured to respond to a control signal received by the camera and a modulator can be configured to modulate the digits The video signal is used to obtain a modulated signal. The complex video signal can include a baseband video signal and a digital video signal. Each of the plurality of video signals represents at least a portion of the field of view of the camera and the control signal controls the content of the baseband and digital video signals. The modulated signal and the baseband video signal are typically transmitted simultaneously by the camera.

The fundamental and digital video signals can be substantially synchronized. An encoder can combine the baseband video signal and the modulated signal as an output signal for transmission over a cable. Control signals such as from a wireless network Received wirelessly. The modulated signal can be transmitted at least partially wirelessly. The digital video signal can be a high quality digital video signal and can be a compressed digital video signal. The control signal moves a portion of the field of view represented by one of the video signals.

10‧‧‧ analog camera

11‧‧‧coax/coaxial cable

12‧‧‧Digital Video Recorder/DVR

14‧‧‧Monitor

16‧‧‧ digital camera

17‧‧‧Coaxial cable

20‧‧‧ digital camera

21‧‧‧Coaxial cable

22‧‧‧DVR/MII Agreement Interface

24‧‧‧High quality camera

25‧‧‧Twisted pair cable

26‧‧‧Coaxial cable

27‧‧‧Data machine

28‧‧‧Control and audio signals

29‧‧‧Data machine

30‧‧‧ camera

31‧‧‧Data Machine/SLOC-T

32‧‧‧DVR/Data Machine

33‧‧‧Coaxial cable

34‧‧‧SD display

35‧‧‧SLOC-R data machine

36‧‧‧Information

38‧‧‧Monitor side main system

40‧‧‧Digital cameras

41‧‧‧IP output

42‧‧‧Control signal

43‧‧‧Display/SD display

44‧‧‧Network Switch/Uplink Passband

45‧‧‧Monitor side SLOC data machine

49‧‧‧SLOC camera side data machine

50‧‧‧ fundamental frequency analog signal

52‧‧‧Single frequency band

53‧‧‧ Carrier

54‧‧‧Channel/uplink

60‧‧‧ camera

70‧‧‧ system

72‧‧‧Coaxial cable

74‧‧‧Standard quality monitor

80‧‧‧Networking security device

82‧‧‧Coaxial cable/input signal

84‧‧‧Standard quality monitor

85‧‧‧High quality display

86‧‧‧IP Video Server

92‧‧‧Segment sync symbol

94‧‧‧ Frame sync segment

96‧‧‧Information fragment

98‧‧‧Information fragment

100‧‧‧Segment synchronization

101‧‧‧ symbol pseudorandom noise sequence

102‧‧‧symbol pseudorandom noise

104‧‧‧ Third PN63 sequence

105‧‧‧Mode symbol

106‧‧‧Reserved symbol

107‧‧‧Pre-coded symbols

140‧‧‧Package

142‧‧‧Parity bytes

150‧‧‧Input commutator

151‧‧‧Output commutator

152‧‧‧ Path

154‧‧‧ Path

156‧‧‧Path/Shift Register

158‧‧‧Path/Shift Register

180‧‧‧Part 1

182‧‧‧Part II

190‧‧‧ ‧

203‧‧‧Second PN63 sequence

207‧‧‧ frame

210‧‧‧Media Independent Interface (MII) Module

212‧‧‧QAM modulator

214‧‧‧QAM demodulator

216‧‧‧ symbol

218‧‧‧Duplexer

220‧‧‧Duplexer

222‧‧‧QAM demodulator

224‧‧‧QAM modulator

226‧‧‧MII interface module

248‧‧‧Digital equalizer and carrier phase/frequency loop

250‧‧‧Digital equalizer

252‧‧2D splitter

254‧‧‧Voltage Controlled Oscillator/VCO

256‧‧‧ low pass filter

258‧‧‧ phase error detector module

302‧‧‧CVBS analog equalizer

304‧‧‧QAM demodulator

305‧‧‧Filter selection signal

330‧‧‧ analog CVBS signal / auxiliary camera output

332‧‧‧High quality signal/passband downlink IP signal

334‧‧‧Uplink communication

340‧‧‧ signal

341‧‧‧ Equalizer

342‧‧2D splitter

344‧‧‧Voltage Controlled Oscillator/VCO

345‧‧‧IP filter

346‧‧‧ phase error detector module

400‧‧‧LUT

402‧‧‧Operation

404‧‧‧ components

420‧‧‧ Equalizer

422‧‧‧Error Calculator Module

423‧‧‧ Stage Manager

424‧‧‧ Lookup Table/LUT

426‧‧‧IP filter

427‧‧‧Splitter and Phase Error Detector Module

428‧‧‧ Equalizer and carrier phase/frequency loop

430‧‧‧ switch

432‧‧‧second switch

434‧‧‧Three stages

436‧‧2D Divider

440‧‧‧SLOC-R

444‧‧‧LUT

445‧‧‧ phase correction factor

446‧‧‧ Output

480‧‧‧ round

482‧‧‧ Round

510‧‧‧ camera

511‧‧‧SLOC camera side data machine

512‧‧‧ cable segment

513‧‧‧Filter step

514‧‧‧ cable segment

515‧‧‧Data machine

516‧‧‧SD display

519‧‧‧Filter step

530‧‧‧ Camera Side QAM Demodulator

531‧‧‧Coaxial cable connection signal

532‧‧‧ Camera Side QAM Modulator

533‧‧‧Down passband signal

534‧‧‧Input signal

540‧‧‧AGC circuit

543‧‧‧Predetermined reference level

544‧‧‧Low Pass Filter/LPF

545‧‧‧Adder

546‧‧‧ Delay element

547‧‧‧gain control signal

548‧‧‧ Gain block

549‧‧‧System input

600‧‧‧ camera optics

602‧‧‧Image Sensor

603‧‧‧ scan signal

604‧‧‧ processor

605‧‧‧ signal

606‧‧‧SLOC-T

606‧‧‧Data Machine/SLOC-T

610‧‧‧Storage

612‧‧‧Optical output system/speaker

614‧‧‧Microphone

616‧‧‧ sensor

618‧‧‧Control interface

700‧‧‧SLOC-R

701‧‧‧ analog baseband video signal

702‧‧‧DVR processor

703‧‧‧Digital video signal

704‧‧‧ analog video decoder

705‧‧‧Digital standard picture quality video signal

706‧‧‧HD digital display processor

707‧‧‧ signal

708‧‧‧Digital Video Decoder

710‧‧‧ Peripheral device/network interface

712‧‧‧ Peripheral device / local bus

714‧‧‧ Peripheral device / local hard disk drive

800‧‧‧SLOC-R

801‧‧‧CVBS signal

802‧‧‧Network Switch Processor

803‧‧‧Digital video signal

804‧‧‧ components

806‧‧‧ components

1300‧‧‧RS encoder

1301‧‧ ‧ Byte data

1302‧‧‧ gyrotron tuple interleaver

1303‧‧‧ Frame synchronization signal

1306‧‧‧ Random generator

1308‧‧‧PT CM Module

1312‧‧‧Module

1313‧‧‧QAM Mapper

1314‧‧‧Through band modulation/PB Mod

1322‧‧‧ Packet/Forward Error Correction (FEC) Data Frame

1324‧‧‧FEC Information Frame

1328‧‧‧Enter

1332‧‧‧ Output bit/encoder output

1334‧‧‧FEC Information Frame

1336‧‧‧ frame structure

1500‧‧‧ top

1506‧‧‧ parallel path

1508‧‧‧parallel path/bottom

2000‧‧‧ module

2001‧‧‧Base frequency QAM symbol

2002‧‧‧ Phase Offset Corrector

2004‧‧‧Module

2006‧‧‧Soft Demapper

2008‧‧‧Viterbi decoder

2014‧‧‧Bit deinterleaver

2016‧‧‧RS decoder

2018‧‧‧Two quasi-splitters

2019‧‧‧Divided QAM symbols

2020‧‧‧ Frame Synchronization Module

2021‧‧‧ Frame synchronization signal

2023‧‧‧Solution random generator

2100‧‧‧ Camera/Baseband IP Data Stream

2120‧‧‧With QAM symbol

2160‧‧‧ fundamental frequency CVBS signal

2162‧‧‧passband down signal

2140‧‧‧High pass with up signal

2200‧‧‧Low pass with IP protocol signal

2201‧‧‧CVBS signal

2202‧‧‧low pass signal

2203‧‧‧High pass signal

2300‧‧‧ Mapper/Encoder/Stream

2302‧‧‧ flow

5000‧‧‧Additional connection

5100‧‧‧ fundamental frequency CVBS signal

5102‧‧‧ signal

5130‧‧‧ Camera side SD display

5131‧‧‧Test data machine

5170‧‧‧ signal

Figure 1 illustrates a prior art system that uses coaxial to carry standard picture quality analog video.

Figure 2 illustrates the prior art method of transmitting high quality digital video.

Figure 3 depicts a system for transmitting analog and digital video in accordance with certain aspects of the present invention.

Figure 4 depicts a network system for analog analog and digital video transmission in accordance with certain aspects of the present invention.

Figure 5 shows the bandwidth allocation for analog and digital video transmission over a coaxial cable in accordance with certain aspects of the present invention.

Figure 6 illustrates an example of a CCTV camera device constructed in accordance with certain aspects of the present invention.

Figure 7 illustrates an example of a data machine for a DVR device constructed in accordance with certain aspects of the present invention.

Figure 8 illustrates an example of a data machine for a network switch device constructed in accordance with certain aspects of the present invention.

Figure 9 is an example of a frame structure for ATSC digital television.

Figure 10 is an example of a conventional frame synchronization packet.

Figure 11 is an example of a data fragment in a conventional data frame.

Figure 12 provides a simplified diagram of a frame configuration.

Figure 13 is a block diagram of a modulator in accordance with some aspects of the present invention.

Figure 14 is a block diagram of a frame structure used in some embodiments of the present invention.

Figure 15 illustrates the operation of one of the whirling byte interleavers in some embodiments of the present invention.

Figure 16 is a block diagram of a selectable rate puncturing interleaved modulation used in one of the specific embodiments of the invention.

Figure 17 illustrates an example of QAM mapping.

Figure 18 shows a frame sync/modal packet.

Figure 19 is a simplified frame structure for use with certain embodiments of the present invention.

Figure 20 is a block diagram of a demodulator in accordance with some aspects of the present invention.

Figure 21 is a block diagram of a camera side data machine in accordance with some aspects of the present invention.

Figure 22 is a block diagram of one of the data units on the monitor side in accordance with some aspects of the present invention.

Figure 23 illustrates a camera side fundamental to passband QAM modulator in accordance with certain aspects of the present invention.

24A and 24B illustrate a monitor side passband pair baseband QAM demodulator in accordance with certain aspects of the present invention.

Figure 25 illustrates a monitor side digital equalizer and carrier phase/frequency loop in accordance with certain aspects of the present invention.

Figure 26 shows a function describing the attenuation as a frequency in a coaxial cable.

Figure 27A depicts the power spectral density (PSD) of the equalizer input.

Figure 27B depicts the amplitude response of the convergence equalizer stage.

Figures 28A, 28B, 29A, and 29B show the loss versus tilt in a passband digital video signal at different frequencies.

Figure 30 shows a monitor side data machine having a digital equalizer in a QAM demodulator in accordance with certain aspects of the present invention.

Figure 31 depicts an analogous active filter suitable for equalizing a fundamental frequency CVBS in accordance with certain aspects of the present invention.

Figure 32 shows an example of a filter response in some embodiments of the invention.

Figures 33A and 33B illustrate a rotating QPSK cluster in a complex plane.

Figure 34 is a block diagram showing one of the phase correction procedures in accordance with certain aspects of the present invention.

Figure 35 depicts an integral ratio (IP) filter in accordance with certain aspects of the present invention.

Figure 36 illustrates a transmitted symbol.

The 37A, 37B, 37C, and 37D diagrams illustrate possible recovery symbols based on the transmission symbols of Figure 36.

Figure 38 shows an example of the phase offset in a received symbol.

Figure 39 shows an example of a transport cluster based on the real and imaginary parts of the frame sync symbol.

Figure 40 is a block diagram of phase shifting used in one of the specific embodiments of the present invention.

Figure 41 illustrates one of the procedures for determining the reliability of frame synchronization.

Figure 42 depicts certain aspects of an equalizer and carrier phase/frequency loop for use with certain embodiments of the present invention.

Figure 43 shows a splitter and phase error detector module for use with certain embodiments of the present invention.

Figure 44 illustrates a complex index LUT module for use with certain embodiments of the present invention.

Figures 45A and 45B plot the real part of the equalized output in a QPSK signal (Fig. 45A) and a 16-QAM signal (Fig. 45B).

46A, 46B, and 46C are clusters QPSK (FIG. 46A), 16-QAM (FIG. 46B), and 64-QAM (46C) generated when a uniformizer is used to converge at R=58. Figure) Histogram of the power of the equalized output.

Figure 47 illustrates an example of a cluster of equalizer outputs and carrier phase/frequency recovery loop module inputs.

Figure 48 shows an example of a QAM mapping with the described threshold.

Figure 49 shows the upper right quadrant of all three clusters that overlap on the same graph.

Figure 50 illustrates the operation of the method of determining a cluster.

Figures 51A and 51B depict systems for simultaneously transmitting standard picture quality and high picture quality video and having a signal order or interruption in accordance with certain aspects of the present invention.

Figures 52A and 52B illustrate a procedure for generating a frame sync pulse from a noisy signal in accordance with certain aspects of the present invention.

Figure 53 is a block diagram of a camera modem having a coaxial connection indicator in accordance with certain aspects of the present invention.

Figure 54 illustrates some aspects of an automatic gain control loop.

The present invention will be described in detail with reference to the accompanying drawings, in which It should be noted that the following figures and examples are not intended to limit the scope of the invention to a single embodiment, but other embodiments are possible by exchanging some or all of the described or illustrated elements. When appropriate, the same reference numbers in all figures will be used to refer to the same or similar parts. Minute. When some of the elements of the specific embodiments can be partially or fully executed using known components, only those portions of the known components that are necessary to understand the present invention are described, and other portions of such known components will be omitted. The detailed description is made so as not to affect the invention. In the present specification, a specific embodiment showing a specific component should not be construed as limiting; rather, the invention is intended to include other specific embodiments including the plural components, and vice versa, unless explicitly stated herein. Moreover, the Applicant does not intend to attribute the terms in the specification or the claims to the unusual or special meaning unless explicitly stated. In addition, the present invention includes equivalents to the present and future aspects of the components referred to herein.

Certain embodiments of the present invention provide systems and methods for enabling a camera to simultaneously transmit high quality digital video and standard picture quality analog video over coax. A high quality camera is adapted to generate a compressed digital video signal and a analog baseband signal. The digital signal is modulated and transmitted in a frequency band separated from the upper frequency of the fundamental video signal. Analog signals can be coded according to any desired standard, including APL, SECAM, and NTSC standards and variants thereof.

For the purposes of this description, an example of a system that uses a secure connection (SLOC) through coax will be described. In addition, SLOC will generally be considered to have uplink and downlink signals for one camera: the camera system is on the upstream. In the description, an example of a SLOC system provides a downlink high-definition (HD) video signal in a first passband, an uplink audio and control signal in a second passband, and a downlink composite video baseband signal. (CVBS). It should be understood that other passband signals and bandwidths can be used. Match. For example, the system can use two-bit video signals of standard or high quality resolution.

Figure 3 depicts a specific embodiment of the invention illustrating certain operational principles of the invention. This example describes the deployment of an HD camera 30 in a system in which live video generated by camera 30 needs to be viewed while simultaneously recording a high quality copy of the video on DVR 32. An example of such a system is a security or surveillance system. The functionality of HD camera 30 is remotely controllable and is described in more detail below. The HD camera 30 is adaptable to simultaneously generate a high quality signal 332 and an analog CVBS signal 330. In some embodiments, the high quality signal 332 and the analog CVBS signal 330 are equal, but may be substantially isochronous if, for example, the delays in processing different signals are not equal. In an example, the CVBS signal 330 may be delayed due to the digital to analog conversion load. In another example, the high quality signal 332 may be compressed based on a compression ratio or the like and subjected to a variable delay. In some embodiments, CVBS 330 and high quality signal 332 may be synchronized or maintained in a constant time relationship with one of the common audio signals generated by camera 30.

Camera 30 can be adapted by adding external components or by integrating hardware and software into camera 30. In the example, a secure connection data machine (SLOC-T) 31 via coax is provided within the camera 30. The SLOC-T 31 can be constructed as one that is integrated as a data machine added to one of the cameras 30 or using components that have been integrated into the camera 30. SLOC-T31 causes a multimedia feed to be transmitted to the downlink through a communication channel: as illustrated, the SLOC-T31 is consistent to make a bearer representative phase The signals of the different resolution signals of the video generated by the machine 30 can be transmitted through a coaxial cable 33. For clarity of description, a SLOC deployed in a transmission device such as camera 30 will be referred to as "SLOC-T", and a SLOC provided in a receiving device such as a DVR, network switch, etc. will be called It is a "SLOC-R". A description of the SLOC-T and SLOC-R devices will be provided in more detail below.

The SLOC-T 31 can cooperate with other components of the camera 30 and/or can increase the enhanced functionality that causes the camera 30 to operate in various modalities. In one example, camera 30 can generate an uncompressed HD digital video output and SLOC-T 31 can provide the ability to compress HD digital video signals. Therefore, the SLOC-T 31 can provide capabilities other than modulation and demodulation as needed to enhance the functionality of the main camera 30. Thus, several SLOC-T devices can operate in a variety of modalities, some of which are provided by way of example. In one mode, the SLOC-T 31 receives a compressed HD video signal from the camera 30 and a standard picture quality analog version of the signal and transmits both signals through the coax 33. In another modality, the SLOC-T 31 receives an uncompressed HD video signal from the camera 30 and a standard picture quality analog version of the signal and transmits a compressed HD digital version of the signal through the coax 33 along with a standard picture quality analog signal. transmission. The SLOC-T31 can transmit an HD digital signal and a standard image quality analog signal derived from an HD signal received from the camera 30.

In some embodiments, the SLOC-T 31 uses a frequency division multiplexing process to generate an output signal that is transmitted on the coax 33. In the example illustrated in Figure 5, the downstream digital signal is provided in a single frequency band 52 concentrated on one of the carriers 53 of the frequency f _cd . Band 52 begins at the highest frequency f ₀ of the fundamental analog signal 50. This different frequency band 52 can be referred to as a channel. Channel 52 can be selected based on the capabilities of SLOC-T31, available bandwidth, signal bandwidth, and other reasons. In some embodiments, channel 52 can be selected for compatibility with the receiving device. In one example, the signal can be provided directly to a standard picture quality television and channel 52 can be selected to ensure proper separation from the baseband signal. When encoding is defined using the standard of the signal, the frequency band in channel 52 can also be selected based on the standard of digital video transmission. It has been envisioned that a single digit signal can be transmitted on two or more different channels to carry portions of the digital signal.

Any translatable version of the digital signal can be generated using any suitable modulation scheme. For example, different types of wired and wireless connections can be used with modulation schemes such as phase shift keying (PSK), frequency shift keying (FSK), quadrature amplitude modulation (QAM), and quadrature frequency division multiplexing ( OFDM) and so on. Modulation schemes are typically selected based on factors including the characteristics of the medium used for transmission, the frame rate of the desired video signal, and other factors that affect the available bandwidth in channel 52.

A SLOC-R modem 35 can be provided in a video capture device such as the DVR 32. The SLOC-R modem 35 can receive and process digital video and CVBS signals. Typically, the CVBS signal is captured and passed directly to a display system 33 for field viewing of the video images captured by camera 30. Display system 33 can be a standard picture quality monitor, although the display system can also receive a digital version of the received analog signal. In one example, the SLOC-R modem 35 can generate a number of analog signals. The bit version is for use with a digital monitor or a properly equipped computer. The acquisition of the baseband signal typically can be effected using a low pass filter that can be implemented using analog components or by digital signal processing techniques. The digital HD signal can be separately captured and provided to the recording section of the DVR 32. In some embodiments, the digital HD video signal can be compressed in the DVR prior to recording. In many embodiments, the digital HD video signal is received as a compressed digital signal.

In some embodiments, SLOC-T 31 and SLOC-R 35 are configured to support bidirectional transmission of signals. In an example of a security installation (and as described in detail below with reference to Figure 6), camera 30 may include a microphone 614, speaker 612, sensor 616, control interface 618 for controlling the electromechanical actuator, and other features. (See Figure 6). In this example, SLOC-T31 and SLOC-R35 are typically configured to communicate control, audio, and other data 36 to camera 30.

Referring again to FIG. 5, in one embodiment, the upstream data can be transmitted to the camera in one or more of the channels 54 located at the upper end of the available bandwidth. Channels for transmitting digital multimedia signals 52, control and audio signals 54 and other data may be selected based on available bandwidth, signal detected in channels 52 and 54 for noise ratio, signaling standards, and/or application specific needs. . In some embodiments, the channel configuration, bandwidth, and signal-to-noise ratio are determined when a training sequence is used to connect the SLOC-T 31 and the SLOC-R35. Typically, the training sequence is used to determine the signaling capabilities of a predetermined or coordinated channel for digital video transmission selection. A channel 52 is used to determine the available bandwidth in the selected channel 52. The characteristics of the selected channel 52 can be used to set the degree of compression for the digital video signal.

In some embodiments, the upstream signal 54 includes a signal that can control the content of the downstream 52 and base frequency 50 signals. For example, camera optics 600 can provide a fisheye view of the location monitored by camera 60 and can control the camera processor to select a portion of the image for transmission as baseband signal 50. Typically, the downstream digital signal 52 can provide a full image for recording on a DVR or for additional processing. The baseband signal 50 can receive the baseband signal 50 for on-site monitoring of the area under surveillance. The baseband signal 50 can include an adjusted image for correction of the visual effect produced by the fisheye lens. One of the baseband signals 50 can cause the field of view to move within the field of view of the fisheye lens by selecting a new portion of the captured image for viewing. For example, the viewer can request "pan-right" to move the field of view to the right. The data transmitted in the upstream signal 54 then causes the camera processor to capture and process the desired portion of the field of view. In some embodiments, the request to move the field of view incorporated into the baseband signal 50 can cause physical movement of the camera 60. Therefore, the control data in the upstream signal 54 can affect the content of both the fundamental frequency 50 and the downstream digital 52 signal.

In some embodiments, the downstream audio can be transmitted as part of the HD digital video signal and/or as part of the CVBS signal. Certain downstream signals can be carried in a separate dedicated channel (not shown). In some embodiments, upstream communication to camera 30 may be handled using an out-of-band communication method, including, for example, using a wired or wireless network. It has been envisioned that certain embodiments may be used as an alternative or as an alternative Item) wirelessly transmits the downstream digital signal 52. Thus, baseband signal 50 can be transmitted through coax, while certain combinations of upstream 54 and downstream 52 are transmitted wirelessly. Typically, the upstream data 54 includes control signals for the downlink 52 and baseband 50 signals regardless of the method of transmission.

In some embodiments, cable 33 can be provided directly to display system 33 for analog display of standard picture quality video. A standard picture quality monitor or display 33 typically includes a filter circuit that is selectable between a baseband signal and a standard modulated television channel. Thus monitor 33 can discard the high frequency digitally encoded carrier signal. If the digital video signal is transmitted in a standard picture quality channel and uses standard picture quality digital coding, the DVR 32 can also receive digital video signals without additional processing. The SLOC-R35 decodes the signals generated by the SLOC-T31 and provides decoded HD digital video and other signals for the DVR32. The SLOC-R 35 can also encode control, audio and other information for transmission to the camera 30.

Referring now to Figure 4, there is shown a particular embodiment of the invention to illustrate certain operational principles of the invention. Figure 4 depicts an example based on a system in which live video generated by camera 40 needs to be viewed while simultaneously providing a high quality copy of the video over a network via network switch 44. In one example, the HD video feed is captured and streamed using an internal or external IP video server. HD camera 40 is typically adapted to simultaneously produce high quality signals and a class of analog video signals. Camera 40 can be adapted by adding external components or by integrating hardware and software such as SLOC-T 400 into camera 40. The SLOC-T 400 can operate in the same manner as the features of the SLOC-T 31 of Figure 3. however, The SLOC-T 400 can be configured to encode a digital video signal in a manner that facilitates the transfer of digital video signals over a network. For example, the SLOC-T 400 can be programmed or configured to provide digital video signals in accordance with a streaming format supported by an IP video server.

The multiplexed video signal transmitted by the digital camera 40 can be received by a network switch 44, optionally with a SLOC-R 440. The fundamental frequency standard image analog signal can be captured and provided to the display 43. In some embodiments, the SLOC-R 440 can capture digital high-definition video signals and forward them to a video server or other network using a suitable network with sufficient bandwidth to carry digital HD video signals. Road device. The digital HD video signal can include a compressed HD video signal. In some embodiments, the digital high quality signal captured by the SLOC-R 440 is compressed or further compressed for transmission to a video server or other network device. The SLOC-R 440 may include hardware and software for re-encoding and/or re-modulating digital high-quality signals for transmission over a network; for example, the SLOC-R 440 may generate encoding for use over an Ethernet network. An H-264 signal transmitted.

Referring now to Figure 6, certain embodiments of the present invention provide for lifting capabilities that can be applied to a security system. In the depicted example, camera 60 includes a data machine SLOC-T 606 and a processor that is configured and adapted to provide digitally encoded multimedia signals in accordance with certain aspects of the present invention. The sequence of images can be combined using one of optical component 600 and an image sensor 602, including combinations of lens systems and CCD sensors known to those skilled in the art. Processor 604 is typically self-provided according to one An image sensor 602 of the desired or predefined frame rate captured image sequence receives a scan signal 603.

In some embodiments, image sensor 602 can include hardware and logic to convert one of the images captured by one or more sensors to scan analog signals and to generate a digital video signal. For example, image sensor 602 can include RGB (red, green, blue) sensors and image sensor 602 can internally process the RGB sensor output to produce a digitally encoded color video signal as its output 603. In other embodiments, processor 604 can preprocess signal 603 from image sensor 602 to obtain an original digital video signal. Raw digital video (whether internally obtained or received from image sensor 602) may be further processed by processor 604 to obtain an initial HD digital video signal. A class of standard picture quality signals can be obtained by processing the raw digital video signal, the output 603 of the sensor 602, or the initial HD digital video signal. Processor 604 can then format the initial HD digital video signal to obtain one or more HD digital video signals in accordance with broadcast and other standards. For example, processor 604 can generate a signal that conforms to broadcast video standards such as the ATSC and DVB standards. Processor 604 can additionally compress the digital video signal.

Camera processor 604 can include a combination of commercially available components and custom hardware and software. In one example, the processor can include one or more of a microprocessor, a digital signal processor, a microcontroller, a sequencer, and other programmable devices, in combination with the memory and support logic to perform a sequence of steps, instructions, and / or program. The storage 610 can be used to store computer readable instructions that, when executed, perform some of the operations described in this application or All features. Camera processor 604 may include some built-in or "hard coded" programs that may be used in the construction of certain embodiments of the present invention. The storage 610 can also be used as a program temporary memory and/or to maintain configuration information. In some embodiments, the storage 610 can be used to store a record of the video captured by the camera 60. Thus, the storage 610 can be implemented using volatile and non-volatile memory, optical and magnetic disks, removable electrically erasable memory, USB memory drives, and other semiconductor, electromagnetic, and optical storage devices.

Signal 605 includes video signals provided by processor 604 to SLOC-T 606 and uplink control, audio and other upstream information transmitted from line 62 to processor 604 via line 62. The upstream audio information can be decoded, processed, and/or formatted by the processor 604 before the audio is relayed to a speaker, converter, or other audio output system 612. The processor can amplify the audio signal or can use a separate amplifier in the audio output component 612. Uplink control may include optical component control 601 and control signals for external devices, typically provided through control interface 618. The external device can include a motor or actuator for translating, rotating, or orienting the camera 60. Optical component control signal 601 and external control signal 618 can be generated by a remote control system in response to a predefined command. For example, the remote user can manipulate a joystick that produces a sequence of encoded instructions that are interpreted by camera processor 604 to mean "rotate the camera 90 degrees clockwise in the horizontal plane," and processor 604 can A sequence of pulses is transmitted in response to a stepper motor mounted axially relative to camera 60 such that the sequence of pulses causes the camera 60 to be rotated about its vertical axis. Rotate. Similar commands can adjust the focus, zoom, and aperture of optical component 600.

In another example, instructions and materials may be provided in uplink control information that may be used to control the functionality of processor 604 and/or sensor 602. Instructions and data may be used to select an area within the field of view of camera 60 for encoding in one or more of the downstream video signals. In some embodiments, the processor and the sensor cooperate to provide one or more virtual cameras that are remotely steerable to specify a field of view to be encoded, whereby the portions are determined by the optical components of the camera 60 It is selected by the virtual pan, zoom and tilt functions of the actual field of view. In some embodiments, processor 604 can additionally cause physical movement of the camera, thereby extending the range of pan, tilt, and zoom functions.

It is contemplated that in at least some embodiments, the CVBS and digital signals can each carry a portion of the image captured by image sensor 602. The image portions may overlap or may come from different regions within the field of view provided by lens 600. Moreover, in some embodiments, an additional camera 60 and/or additional image sensor 602 can be used to expand the available field of view. For example, it may be necessary to configure a complex camera to obtain a panoramic (360°) field of view of an area. One or more processors 604 can provide analog and digital signals representative of the field of view, or a portion of the field of view. In one example, the full panoramic field of view can be provided in a digital signal recorded on a DVR, and the CVBS signal can provide a selectable field of view within the panorama. Selectable field of view can be controlled using zoom, pan and other controls. In another example, The CVBS and digital signals can provide a common or different portion of the panoramic view and the portions can be independently controlled by a remote viewer.

Figure 7 depicts an example of the use of one of the SLOC-R 700 (similar to the SLOC-R 35 described in Figure 3) in a secure digital video recording system 70. System 70 includes a SLOC-R 700, a DVR processor 702 coupled to peripheral devices 710, 712, and 714, an analog video decoder 704, a digital video decoder 708, and an HD digital display processor 706. As described above, the SLOC-R 700 receives and decodes signals from the coax 72, which typically includes an analog image quality video signal and an HD digital video signal. The SLOC-R 700 also transmits upstream audio and control signals via the coax 72. The SLOC-R typically separates the analog CVBS signal from the HD digital video signal in the input signal 72, providing the digital video signal 703 to the processor 702 and the CVBS signal 701 to a standard picture quality monitor 74 as shown in FIG. Live feed of camera 60. The SLOC-R 700 can optionally provide an analog baseband video signal 701 to an analog video decoder 704 that processes the signal to produce a digital standard picture quality video signal 705. Display processor 706 multiplexes and/or selects between digital standard picture quality signal 705 and a signal 707 derived from playback of stored HD digital video. The display processor can provide the selected signal in a format that can be displayed by the HD television or monitor 76.

The DVR processor 702 receives the digital HD video signal 703 and optionally stores at least a portion of the signal as one of the video captured by the camera 60. The record can be in a local hard drive 714, through the network interface 710 and/or USB/Firewire or other local sink The bank 712 is connected to a network storage (not shown) or stored in other optical, electromagnetic or semiconductor storage. Recorded video can be further compressed to save storage space. The DVR processor can capture the recorded video and provide a playback signal 707 using the digital video decoder 708.

Figure 8 depicts an example of the use of one of the SLOC-R 800 (similar to the SLOC-R 35 described in Figure 3) in a networked security device 80. The device 80 includes a SLOC-R 800 and a network switch processor 802, which is typically connected to the IP video server 86 by a network. As described above, the SLOC-R 800 receives and decodes signals from the coax 82, which typically includes an analog image quality video signal and an HD digital video signal. The SLOC-R 800 transmits upstream audio and control signals via coax 82 as needed. The SLOC-R typically separates the analog CVBS signal from the HD digital video signal in the input signal 82, providing the digital video signal 803 to the processor 802 and the CVBS signal 801 to a standard picture quality monitor 84 as a picture from Figure 6. The live feed of the camera 60 is shown. In some embodiments, the SLOC-R 80 can include components 804, 806 or the like to digitize the CVBS signal 801 for use with a digital display, such as the high quality display 85, also as a sixth The picture shows the live feed of the camera 60. However, it should be understood that a suitably equipped display device or computing device can receive the CVBS signal 801 and digitize the execution signal. The network switch processor 802 receives the digital HD video signal 803 and optionally transmits the signal to a network video server 86 that can then maintain a recorded video captured by the camera 60. The digital HD video signal 803 can be further compressed before being transmitted to the video server 86.

Referring again to Figures 5 and 6, certain embodiments of the present invention permit selection of the contents of the baseband analog signal 50 and the downlink signal 52 as desired. In one example, both the baseband signal 50 and the downstream signal 52 contain the same image, the former being analogous and the latter being digitally encoded. Digital images can be compressed and uncompressed, with standard image quality and high image quality, and transmitted at full frame rate or frame rate as needed and selectively. In another example, the baseband signal 50 provides a portion of the full image captured by the image sensor and the downstream signal 52 carries the full image. In another example, the baseband signal 50 provides a full image provided by the image sensor, and the downstream contains a portion of the full image. Thus, it is envisioned that a user of a digital camera can select a highly configurable system for displaying, recording, and transmitting video images from a wide variety of options.

Analogous equalization of fundamental frequency signals

Certain embodiments of the present invention include systems and methods for improving the effects of high frequency ramp roll in cables that cause more high frequency attenuation as the cable length increases. This tilt introduced by the cable degrades the fundamental frequency analog video and passband digital video signals, which deteriorates as the cable length increases. However, some embodiments of the present invention provide an equalizer (typically in a digital receiver) that removes skew on the digital passband signal so that the transmitted symbol can be reliably decoded.

Certain embodiments of the present invention improve the performance of systems and devices, including the above-described systems, wherein the baseband video signal can be combined with a digital representation of the baseband video signal and with a control signal to enable transmission of A single cable such as a coaxial cable (coax). Figures 3 and 4 show examples of specific embodiments that provide a SLOC system and Figure 5 shows one possible modulation scheme for a SLOC system. Taking the example of FIG. 3, the HD camera 30 provides one of the outputs including the compressed digital HD video 332 and one of the analog standard image quality (SD) CVBS auxiliary camera outputs 330. The compressed HD video signal 332 is modulated to a passband 52 by a SLOC camera side modem 31. The modem 31 includes a QAM modulator that provides a modulated signal that can be combined with the baseband analog CVBS signal 330. The combined signal is transmitted downstream through coaxial cable 33, typically up to a distance of 300 meters or more. At the monitor side, a SLOC monitor side modem 35 separates a signal representative of one of the baseband CVBS signals 330 from a signal of the passband down video signal 332. A signal feed representing an CVBS, an SD display 34, is used for no-delay on-site inspection. The Qualcomm downlink signal is demodulated with a QAM demodulator, and its output is fed a main processor and DVR 32, which supports the live view on the monitor 34 (although possibly slightly delayed) HD viewing and non-instant HD playback for subsequent View.

In this example, upstream communications are provided by, for example, an IP protocol when needed. The upstream communication can additionally transmit audio and camera control signals 334 from the monitor side to camera 30. Typically, the bit rate of the upstream signal and thus the required bandwidth is typically much lower than that required for the downlink passband signal. The monitor side SLOC modem 35 includes a QAM modulator that modulates the IP signal to the upstream passband 54. As described in FIG. 5, the uplink passband 54 and the downlink passband 52 are located at different spectral positions. At the camera side, The SLOC modem 31 includes a QAM demodulator for receiving an upstream signal. This approach provides several advantages over previous systems and methods, including:

(1) Increase the operating range - increase the distance.

(2) The system can use the existing infrastructure and deploy it with coaxial cable.

(3) Low latency, instant (on-site) video availability.

(4) On-site CVBS video and HD video can be viewed in different locations.

Fig. 21 is a simplified schematic diagram showing an additional detail of the SLOC camera side data unit 49 of Fig. 4. The IP connection to the HD camera 2100 is established through the Media Independent Interface (MII) module 210 to the interface of the QAM modulator 212 and the QAM demodulator 214. In one example, the MII 210 is compliant with the IEEE 802.3 standard. The QAM modulator 212 operates using well known principles to convert the baseband IP data stream 2100 into a passband QAM symbol 2120. These symbols are added at 216 to the baseband CVBS signal 2160 and then to the duplexer 218. The duplexer 218 can be a 2-way analog device that passes the combined baseband and low passband downlink signal 2162 to the coax and high-passband uplink signal 2140 received from the coax and feeds it to the QAM demodulator 214. The QAM demodulator 214 typically operates using well known principles to demodulate and output the baseband data received from the monitor side to the MII interface 210.

Figure 22 is a simplified schematic diagram showing additional details of the SLOC monitor side modem 45 of Figure 4. The duplexer 220 receives the downlink combined baseband CVBS and the low passband IP signal 2200 from a coaxial cable, and divides the signal into components by low pass (LP) and high pass (HP) filtering. (component element) 2201 to 2203. The CVBS signal 2201 can be transmitted directly to a standard picture quality monitor or other display device. The low pass band signal 2202 can be fed to a QAM demodulator 222 that feeds the MII interface module 226. The duplexer can also receive a high passband signal 2203 from the QAM modulator 224 and can pass this upstream signal to the coaxial cable. The QAM modulator 222 typically takes its input from the MII interface 226 that can be connected to a master/DVR supporting the IP protocol.

Coaxial cables typically exhibit a significant high frequency ramp attenuation characteristic that causes more high frequency attenuation as the cable length increases. This "tilt" may be significant in the band of the passband signal and it can cause considerable inter-interference (ISI). The digitization of the digits may be required to cause the QAM demodulator 222 to properly recover the transmitted data.

Base frequency to passband modulation

Figure 23 shows the camera side fundamental frequency to passband QAM modulator 212 in more detail (Fig. 21). The data from the MII 210 is received by the FEC encoder/mapper 2300, which adds error protection data to the MII 210 using, for example, cascading Reed-Solomon coding, byte interleaving, and/or fence coding. In the data stream. The mapper/encoder 2300 demultiplexes the data into streams 2300 and 2302, wherein a given size group of the bytes of each data stream represents one of the QAM amplitude levels in the real and imaginary directions, respectively. An isolated transmission QAM pulse is given as: Where d _{R , m} and d _{I . m} are determined by two independent message flows and respectively represent the real and imaginary parts of a complex QAM, where m =1... M indicates one of the base two-dimensional QAM clusters, where M- modulation Carrier frequency, and q (t) is a raised cosine pulse function.

A continuous serial transmission of QAM pulse s (t) to F _S = 1 / T through a noisy rate _S one multi-path channel. Therefore, the signal received at the input to the QAM receiver is given by r ( t )= s ( t )* c ( t )+ v ( t ), where * indicates the convolution, c ( t ) is the channel pulse Response, and v ( t ) is additive white Gaussian noise. therefore: Where d [ n ] is a complex transmission, and f ₀ and θ ₀ are phase and frequency offsets respectively associated with the receiver passband of the transmitter to the local oscillator demodulator local oscillator such that f _LO = f _c -f ₀ .

Baseband to passband demodulator

Figure 24A shows the monitor side passband to the baseband QAM demodulator 222 in more detail (Fig. 22). A signal r (t) may be received from a coaxial cable, for example, one of the line rate higher than the sampling rate (see 240), resulting in sampled signal r (nT _samp). After sampling: Then, after down-conversion, re-sampling and matching filtering according to rate 1/ T _{s is} obtained: Where v' [ k ] is a sampling complex filtering noise, since the pulse shaping and matching filtering q is combined with the perfect rate sampling timing, it is assumed that any ISI is only due to the channel impulse response c .

Equalizer and carrier phase/frequency loop

The digital equalizer and carrier phase/frequency loop of Figure 24A are discussed in more detail with reference to Figure 25. A signal x [ k ] enters an adaptive digital equalizer 250, which may include a linear digital filter for compensating for the tilt resulting from the channel impulse response c. The order weight adjustment can be achieved using one or more known methods, including the LMS algorithm. The equalizer determines its output y [ k ] and a phase-rotated version of the two-dimensional (2D) splitter. [ k ], compare to generate an error signal, used to calculate an updated set of filter order weights. The LMS algorithm can operate as follows: if x [ k ] represents an N long equalizer input vector, and y [ k ] represents an equalizer output vector g ^H [ k ] x [ k ], where g ^H [ k ] The N long equalizer step weight vector and the H superscript indicate a conjugate shift term (Hermitian).

g [ k +1]= g [ k ]-2 μx [ k ] e ^* [ k ], where μ is a small step size parameter and * superscript indicates complex conjugate. In order to remove the effects of the slope of the passband cable, the LMS equalizer order can approximate the inversion of the channel impulse response c after convergence.

A 2D splitter 252 will z [ k ] and output The real and imaginary parts of [ k ] (which is an estimate of the initial transmission d [ k ]) are independently partitioned. Phase error detector module 258 receives z [ k ] and [ k ] and form a phase error signal . Low pass (LP) filter 256 can be an integral proportional filter that allows the loop to correct both phase and frequency offsets. The output of low pass filter 256 feeds a complex discrete voltage controlled oscillator (VCO) 254 which outputs a complex phase/frequency correction factor e ^{-j θ [k]} corrected for both θ ₀ and f ₀ . VCO 254 also provides "uncorrected" splitter output One of [ k ] outputs ( e ^{+ j θ [k]} ) such that it can be used to derive an error signal for the equalizer order update. This typical requirement is because the equalizer operates on x [ k ]. Referring also to Figure 24A, the equalizer output z [ k ] is fed to a demapper that detects that the real and virtual levels are a group of bits. The FEC decoder then performs Viterbi decoding, byte deinterleaving, and/or Reed-Solomon decoding to correct the received bit error and pass the resulting data to the MII interface.

Cable length

The received video signal can undergo attenuation as a function of the frequency attributable to certain characteristics of the cable. For the purposes of this discussion, an example of a coaxial cable is described. The severity of the attenuation, often referred to as tilt, typically depends on the cable type and length. Figures 26A and 26B show attenuation as a function of frequencies for various lengths of cable types RG6 and RG59. It can show that the tilt is equivalent to multipath distortion, where the extra path and the main path have a very small delay spread. As the tilt increases, the number of non-important multipath components (and their respective gains) also increases. Multipath distortion causes ISI in the received signal and thus can severely degrade transmission reliability. In a digital signal, an equalizer can be used for the receiver to remove this impairment. Figures 27A and 27B show equalizers, respectively The input power spectral density (PSD) and the amplitude response of the convergence equalizer stage. Specifically, Figure 27A shows the PSD input by the equalizer after transmission through a 2000 ft RG-6 cable with a carrier frequency of 15.98 MHz (both display passband and associated fundamental frequency) and Figure 27B shows Convergence amplitude response of the digitizer equalizer order.

Some embodiments of the present invention include a digital equalizer that cancels the tilt introduced by the cable, removes the ISI in the passband signal and enables reliable decoding of the transmitted data. As the cable length increases, the digital passband signal on the monitor side can be reliably received using digital equalizers for digital data and well-known forward error protection methods such as Reed-Solomon decoding and fence coding. However, cable tilt also negatively affects the high frequency of the fundamental frequency analog CVBS signal, which reduces image sharpness and chroma when viewed on the monitor side. Accordingly, some embodiments provide an adaptable filter (e.g., an analog equalizer) that can be applied to the CVBS signal at the monitor side to compensate for cable tilt at the fundamental frequency. Some embodiments utilize a passband digital equalizer to estimate the amount of tilt at the fundamental frequency to then select one of a set of fundamental frequency analog filters to apply to receive the CVBS signal.

Effective estimation of passband tilt

In estimating the tilt in the signal band, a frequency band can be selected, wherein when quantized in decibels, the tilt in the PSD of the input signal will be approximately linear. Therefore, the frequency of the baseband digital equalizer input - 2.67 MHz to 2.67 MHz (which will therefore correspond to 13.31 MHz and 18.65 MHz in the passband input signal) provides a suitable range. As shown in Figure 26A, the tilt from 13.31 MHz to 18.65 MHz is approximately 3.7 dB for the 2000 foot RG-6 system. In order to estimate the tilt in decibel self-converging digital equalizer filter order, the following calculations can be performed: Where G [ k ] is the time domain convergence equalizer DFT of the filter stage, and k ₁ and k ₂ correspond to the specific frequency band of the DFT. FIG 25 because the first digit of the available time domain equalization to swirl purposes, to estimate a given object k ₁ and k ₂ of inclined, typically requires a FFT (or N complex multiplication and addition may be used for two points). which is Where g ( n )= g _R ( n )+ ig _I ( n ), n =0,1... N -1 is the N time domain equalizer order (the dependence on the time index is omitted). It should be noted that the 1/ N scalar quantity is not necessary in this calculation. A similar calculation will be performed for G ( k ₂ ). However, this calculation can be significantly reduced by careful selection of the frequency band. By making k ₁ = N /4 (corresponding to a frequency of 2.67 MHz), the complex exponential in equation (2) is dramatically simplified: You can use addition to calculate the real and imaginary parts of the filter's frequency response:

Finally, the power at this band is: By allowing k ₁ = N / 4, the power calculation system is significantly simplified. Similarly, if k ₁ = 3 N /4 (corresponding to one of the frequencies of -2.67 MHz), the complex index will again be significantly simplified.

The real and imaginary departments are calculated as:

And the power | G [ k ₁ ]| ² is calculated as above. In Figure 2b, the upward tilt in the amplitude response (in decibels) of the convergence filter stage is approximately linear even with a moderate SNR for a 64-QAM. Also, when calculated in this way, It is very close to the actual tilt on this band of 3.7dB.

Use passband tilt estimation for fundamental frequency CVBS tilt correction

After estimating the passband tilt of the digital video signal, an appropriate fundamental frequency analog filter can be selected from one of the M different filters. This can indicate that the estimated passband tilt of the digital video signal band will indicate the severity of the tilt in the baseband CVBS signal, which can then be roughly corrected with a analog filter. In Figure 28A, the tilts in the digital video signal strips from 13.31 MHz to 18.65 MHz for RG-6, RG-11, RG-59, and RG-174 are shown and the possible lengths of the cables are shown. Figure 28A shows the loss at 3.58 MHz versus the tilt in the passband digital video signal for the RG-6, RG-11, RG-59, and RG-174 cable types. Figure 28B shows the loss at 6 MHz. It can be observed that the losses at 3.58 MHz and 6 MHz are roughly the same for all four cable types for a given tilt. Figure 29A shows the loss of tilt in the passband digital video signal at 3.58 MHz relative to the RG-6, RG-11, RG-59, and RG-174 cable types. Figure 29B shows the loss at 6 MHz. It will be observed that losses at 3.58 MHz and 6 MHz are roughly the same for all four cable types for a given tilt.

Since the estimated passband tilt is the only available information about the cable frequency response, the ideal situation is where the frequency response of the cable at the fundamental frequency (CVBS signal band) is associated with the tilt of the passband digital signal in a known manner, regardless of the cable. Type or length. Figures 28B, 29A, and 29B confirm this in the frequency response at DC, 3.58 MHz, and 6 MHz. For example, for all four cables, at a slope of 1.5 decibels in the passband digital video signal, the loss at DC, the loss at the color carrier (3.58 MHz), and the loss at 6 MHz are about 0.68 dB, 4.1 dB. And 5.3 decibels. Therefore, whether the 1.5 dB passband tilt is caused by 275-foot RG-174, 750-foot RG-59, 825-foot RG-6, or 1825-foot RG-11, the same analog filter will cancel CVBS The fundamental frequency of the signal is tilted.

An example of an algorithm for selecting an appropriate analog filter from a set of M filters is shown below:

It should be noted that α ₀ =1; other values of α _n are <1 and are selected such that the bit offset addition is sufficient to calculate R _n . Thus, the monitor side QAM demodulator of Figure 24A is typically modified such that the digital equalizer of the passband QAM demodulator provides a signal that selects one of the M-class CVBS filtered responses. Figure 24B shows a modified portion of the monitor side QAM demodulator, wherein the analog filter selects the output from the digital equalizer that operates according to the algorithm described above. Figure 30 shows the entire monitor side data machine in which a digital equalizer in QAM demodulator 304 provides a filter select signal 305 to CVBS analog equalizer 302.

Figure 31 shows an example of an analog active filter suitable for equalizing the fundamental frequency CVBS signal. In this example, M = 3, so there are 4 possible filtering choices. The desired filter response is selected by turning off one of the M +1 switches in switch module 310, which in turn connects the respective RC pair connected thereto to ground. The possible filter response is shown in Figure 32.

Those skilled in the art will appreciate that the present invention can be applied to digital communication systems that use other passband modulation and forward error correction methods. Those skilled in the art will also recognize that more than two points in the FFT of the passband digital equalizer order weight vector g [ n ] can be used to select an analog filter for the CVBS signal, and other types of digitization can be used. The device is designed for passband signals, including frequency domain equalizers, where the values of G ₁ [ k ] and G ₂ [ k ] will have been calculated as part of the equalization procedure. In addition, conventional equalizer order weight calculation methods other than LMS, such as RLS, may be used.

In some embodiments, a CVBS analog filter having a selectable response can take a form other than the above. In addition, the equalizer of the CVBS signal can take the form of a digital filter, in which case the CVBS is sampled and digitized prior to equalization. In this case, the number of bits of a weight-based weighting filters according to the order described by the same algorithm to select one of the M analog filter response selected from a predetermined set of weighting vector M in the right order.

Partitioning in a digital communication system

Digital data streams typically have some sort of box structure such that the data is organized into groups of uniform sizes of bits or bytes. Any system that uses block-based forward error correction (FEC) will have frames organized into approximately error correction codeword sizes. In addition, if the system uses interleaving to combat pulse noise, the frame structure will be configured in consideration of interleaver parameters. If the system uses data randomization to achieve a flat spectrum, the pseudo-random sequence used can be synchronized to the frame structure and restarted at the beginning of each frame.

For an RF digital communication system, a receiver typically must first achieve carrier-to-synchronization and equalization. It can then recover the transmission data. However, in order to understand this incoming data stream, the receiver must also synchronize to the frame structure. In other words, the receiver must know where the error correction code character begins and ends. It must also be able to synchronize the receiver module such as the deinterleaver to match the interleaver operation of the transmitter, resulting in The de-interleaved bits or bits are correctly sequenced, and the de-random generator is used to match the start of the pseudo-random sequence used in the transmitter to flatten the spectrum.

Conventional systems often provide receiver frame synchronization by appending a known pattern of fixed length symbols at the beginning or end of the frame. Each frame repeats this same pattern, and it often consists of a two-level (ie, binary) pseudo-random sequence with advantageous autocorrelation properties. This means that although the sequence has a large value at zero offset from its own autocorrelation, if the offset is non-zero, the correlation value (side lobe) is extremely small. In addition, the correlation of this frame synchronization sequence with random symbols will result in a small value. Therefore, if the receiver performs a correlation between the entry symbol and the stored version of one of the frame sync modes, it should expect to obtain a large value only at the exact beginning of each frame. The receiver can then easily determine the starting point of each frame.

Instance of the frame structure

Referring to Figure 9, the ATSC Digital Television (DTV) terrestrial transmission standard adopted in 1996 provides a system for transmitting data in a frame. Each frame 90 contains 313 segments, and each segment contains 832 symbols, with a total of 260,416 symbols per frame. The first four symbols in each segment contain a segment sync symbol 92 of the sequence [+5, -5, -5, +5]. The first segment of each frame is a frame sync segment 94 having 312 data segments 96,98. Referring now to Figure 10, the frame sync segment 94 has a segment sync 100, a 511 symbol pseudo random noise (PN511) sequence 101, a 63 symbol pseudo random noise (PN63) sequence 102, and a second PN 63 sequence. Column 203 and a third PN63 sequence 104. This is followed by a 24-modal symbol 105 indicating the modal system 8VSB. The pre-encoded symbol 107 and the reserved symbol 106 complete the frame sync segment 94. The segment sync 100 and PN511 101 symbols are known to the receiver in advance and can be used to obtain frame synchronization via the associated method. All of the preceding symbols come from the set {+5,-5}. The last 12 symbols of this fragment are from the set {-7-5-3-1+1+3+5+7} and are the copy of the last 12 symbols of the pre-data field. These are referred to as pre-encoded symbols (not discussed here).

Referring also to FIG. 11, for each of the subsequent 312 segments of the field (referred to as a data segment), the 828 symbol 32 following the four segment sync symbol 30 is from a single 207 bit by taking 2 bits at a time. A tuple (1656 bits) Reed-Solomon (RS) code character is generated, which encodes its fence into 3 bits, and then maps each unit of 3 bits from the set {-7-5-3-1 One of the +1+3+5+7} 8-bit quasi-symbols.

Another example of framing in a digital communication system is seen in the ISDB-T system. Unlike single-carrier ATSC systems, ISDB-T utilizes a multi-carrier system that encodes orthogonal frequency division multiplexing (COFDM). For example, Mode 1 of ISDB-T uses a 1404 carrier. The frame consists of 204 COFDM symbols and can be considered to be a combination of COFDM symbols 1404 independent QAM symbols, one for each carrier. Therefore, the frame consists of a combination of 204x1404=286416 QAM symbols. In this case, 254592 is the data, and 31824 contains the preamble information (which can be used for frame synchronization) and modal information, which spreads the frame in a known pattern.

Figure 12 shows a simplified diagram of this frame configuration. It can be seen that the map and modal information are scattered in the frame according to a known pattern. This system has a modality that utilizes three different QAM clusters - QPSK, 16QAM and 64QAM. It also supports five different fence coding rates (1/2, 2/3, 3/4, 5/6, 7/8) based on a single punctured mother code. This well-known technology makes it extremely economical to construct a single Viterbi decoder in the receiver that can be easily adjusted to decode all five specific codes.

Before the gate is encoded at the transmitter, the data is formed into a 204-byte (1632-bit) long RS block. When the number of COFDM symbols per frame is always constant, the number of RS blocks per frame varies with the selection modality, but most importantly, the number is always an integer. Once the frame synchronization has been established and the fence rate is known, this allows the RS block to be easily synchronized in the receiver. In order for this to be true, the number of data bits per frame before the fence encoding must be exactly divisible by 1632 for all modes.

Table 1 shows the number of data bits per frame for all modalities (a combination of QAM cluster and fence rate). In each case, the number of data bits per frame is exactly divisible by 1632 (the data bit means the bit before the fence encoding).

Certain embodiments of the present invention provide a sub-frame structure for a modulation system used in a digital communication system. In particular, signaling systems and methods are provided for use in security systems (including those described above). A whirling byte interleaver interleaves the frames of the data, wherein the interleaver is synchronized to a frame structure and a random generator is configurable to generate a randomized data frame from the interleaved data frame. In one example, a punctured fence code modulator operates at a selectable code rate to generate a fence-encoded data frame from the randomized data frame. A QAM mapper maps the grouped bits in the fence-encoded data frame to the modulation symbols to provide a mapping frame and a synchronizer adds a synchronization packet to the mapping frame. The punctured fence code modulator can be bypassed as needed to achieve an optimized net bit rate under various white noise conditions, thereby allowing system performance to be optimized.

In some embodiments, a novel frame structure is provided in a single carrier communication system. The autocorrelation of one of the fixed-length symbols at the beginning or end of a frame obtains a large value at the zero offset. If the offset is non-zero, the correlation value (side lobe) is extremely small. However, the correlation of this frame synchronization sequence with random symbols will result in a small value. Thus, a receiver can perform correlation of the incoming symbols with one of the stored versions of the frame sync mode to obtain a large value at the exact beginning of each frame so that the receiver can determine the start of each frame. The communication system can operate in any mode of the complex modality and can use various combinations of symbol clustering, fence coding, and interleaved modes. The receiver must recognize and understand the modality to successfully recover the transmitted data. For this purpose, additional modal symbols can be added to the frame sync mode. Corresponding methods can be used to reliably receive such modal symbols It is transmitted repeatedly for each frame. It can be encoded even more robustly by using a block code.

A frame structure in accordance with certain aspects of the present invention utilizes a combination of punctured fence coding and QAM clustering (similar to those used for ISDB-T). The number of symbols per frame may be a variable integer according to the modality and the number of RS packets per frame is a constant integer regardless of the modality. This configuration simplifies the design of the receiver of the processing block (eg, de-randomizer and de-interleaver) because the number of RS packets per frame is always fixed. In a conventional system such as ISDB-T, the number of symbols per frame is constant and the number of RS packets per frame is a variable integer according to the modality. The frame will be described with reference to an example of a transmitter structure in accordance with certain aspects of the present invention as described in FIG.

An RS encoder 1300 accepts the header generation data 1301 and an externally generated frame synchronization signal indicating the start of each group of the 315Reed-Solomon packet 1322. As shown in FIG. 14, each packet 140 contains 207 bytes, of which 20 bytes are parity bits 142. The 315 Reed-Solomon packet forms a forward error correction (FEC) data frame 1322 containing 65205 bytes.

A whirling byte interleaver 1302 is as follows. Figure 15 illustrates a modality of operation of the interleaver 1302 against pulse noise affecting the transmitted signal. The parameter B in the paths 156, 158 is set to 207, and the parameter M in the paths 152, 154, 156, and 158 is set to 1. The frame sync signal 1303 forces the input and output commutators 150 and 151 to the top position 1500 to synchronize the interleaving of the frame structure. The input and output commutators 150 and 151 are shifted downward by a position 1502 when a tuple enters the interleaver and a different byte leaves the interleaver. When the commutators 150 and 151 reach the bottom 1508, they move back to the top 1500. Each of the B parallel paths 1506, 1508 includes a shift register 156 and 158 having the length shown in Figure 15 (path 1506 has a length ( B-2 ) M and path 1508 has a length ( B-1) ) M ).

The random generator 1306 shortens a PN (pseudo-random noise) sequence of one length 219-1 by resetting the PN sequence generator at each frame synchronization time on the 65205x8=8521640 bits of the FEC data frame 1324. An operation (by performing a mutual exclusion or operation on the bits) produces a randomized FEC data frame 1328.

An example of a selectable code rate punctured fence coding modulation (PTCM) module 1308 is shown in more detail in FIG. PTCM1308 uses a method known to those skilled in the art. The method begins with a 64 state 1/2 rate encoder and performs puncturing to achieve any of 5 different code rates. In some embodiments, PTCM 1308 can also bypass completely (code rate = 1). This allows for a selective compromise between the net bit rate of the system and the white noise performance. Similar fence coding techniques are used for ISDB-T and DVB-T systems. The PTCM produces a two-bit 1332 at the output for each bit provided to input 1328. However, some output bits 1332 are discarded according to the selected code rate and the corresponding puncturing mode. The QAM mapper 1313 takes the bits of the group of 2, 4 or 6 from the encoder output 1332 and maps them to QPSK, 16QAM or 64QAM symbols, respectively. Examples of such mappings are provided in Figure 17.

Module 1312 adds a frame sync/modal symbol packet (all symbology QPSK) to the beginning of each FEC data frame 1334. Referring to Figure 18, the first portion 180 of the packet contains 127 symbols and includes both the same binary PN sequence for both the real and imaginary parts of the symbol. Other PN sequence lengths are also possible, and the real and imaginary parts may have opposite signs. The second portion 182 of the packet contains information indicating the transmission modality - the selected QAM cluster and the selected fence rate. This modal information can be encoded for increased reliability at the receiver using a block error correction code. Methods that can be used include BCH coding and other block codes. In one example, it is possible to include six possible fence codes around the line. In addition, three clusters can result in 18 modalities. Therefore, 5 bits are required to represent each of the possible modal choices. A 5-bit element can be encoded into a 16-bit code character using an extended BCH code. Since each QPSK symbol contains 2 bits, an 8 modal symbol is required.

Figure 19 illustrates a frame structure 1336 provided for passband modulation (PB Mod) 1314 (see Figure 13). Bearer 190 includes a 315 RS packet (521,640 bits). The number of QAM symbols mapped by the 315RS packet varies with modal selection. The PB Mod module 1314 then modulates the baseband QAM symbols to the passband using any suitable method known to those skilled in the art.

Frame structures in accordance with certain aspects of the present invention advantageously overcome some of the shortcomings and disadvantages of conventional frames. In particular, the frame structure provides for all modalities: - a constant integer RS packet for each frame of the modal, and - for all modalities, the QAM symbol number of each frame is a variable integer - For all modalities, the puncturing mode loop of an integer for each frame. Please note that it is not unimportant to provide an integer QAM symbol for each frame, because the FEC data frame must contain exactly the Ix207 data byte, where I selects an integer so that each frame has a fixed integer RS. Packet. Therefore, the number of data bits per frame before the fence encoding must not only be an integer, but the number must be exactly divisible by 207x8=1656 for all modalities. In addition, the number of fence encoder output bits per QAM symbol is 2, 4, and 6 bits for QPSK, 16QAM, and 64QAM, respectively (see Table 2, which shows a bit rate for the fence code bypass). =1). In addition, the fence coding adds bits. The number of data bits for each symbol before the fence encoding is shown in Table 2, where each item is calculated as: The fact that the number of data bits per symbol can be a fraction requires precise selection of the RS packet size and the number of RS packets for each frame. The RS packet size of each frame 207 and 315 packet can be used to reach one integer symbol of each frame. As shown in Table 3, each item can be calculated as:

This frame provides the additional advantage of a puncturing mode loop (pp/frame) for each frame with an integer for all modalities. In order to correctly decode the punctured fence encoded data, the decoder in the receiver must know how the puncturing pattern is aligned with the data. The ubiquitous puncturing mode applied at the output of the mother code fence encoder is indicated in the second column of the table of Figure 16. The number of 1 in each puncturing mode is the puncturing mode length. In the proposed system, the puncturing mode is always consistent with the beginning of the FEC data frame. This allows frame synchronization in the receiver to align the de-puncturing device in the receiver Viterbi decoder with the bit stream. The required alignment is indicated in Table 4, which shows the pp/frame for one of the integers of all modalities. The puncturing mode (pp/symbol) item for each symbol can be calculated as: The pp/frame project can be calculated as:

It should be appreciated that other combinations of RS packet size and number of packets per frame can be used to achieve the same desired result. The numbers provided herein are for illustrative purposes only.

As shown in Fig. 20, certain embodiments of the present invention provide a receiver constructed to handle a frame of certain aspects of construction in accordance with the present invention. Module 2000 receives the data transmitted in the passband signal and converts it into a baseband QAM symbol. The operations performed by module 2000 may include symbol clock synchronization, equalization (to remove inter-symbol interference), and carrier recovery, which typically employs sub-modules. Thus, module 2000 can include an equalizer whose output restores baseband QAM symbol 2001. The baseband QAM signal 2001 is provided to a two-bit quasi-splitter 2018 for segmentation in both real and imaginary directions to form a sequence a _R [ k ] [--1, +1] and a _I [ k ] [--1, +1] 2019, which is provided to the frame synchronization module 2020. The frame synchronization module 2020 synchronizes a stored copy of the PN sequence with the binary frame and performs a continuous cross-correlation operation on the divided QAM symbol 2019 for the real and imaginary parts. Each member of the stored copy has a value of -1 or +1. This operation is given as follows: Where s is a storage replica in the frame synchronization PN sequence of length 127. The maximum magnitude of b _R or b _I indicates the beginning of the FEC data frame.

Once the frame sync start position is found, the location of the code character containing the modal bit (cluster and fence rate) is known. The codeword can be reliably decoded by, for example, a BCH decoder or by a codeword that will receive the received codeword with all possible codewords and select the highest resulting value. Because this information is transmitted repeatedly, additional reliability can be obtained by requiring the same result to occur multiple times before accepting it.

This derived frame sync signal 2021 is used to indicate which symbols are to be removed in the "Remove Frame Synchronization/Mode Symbol" module 2004 before the symbols are fed to the soft demapper 2006. In an example, the 127-frame sync symbol and the 8-modal symbol are removed from the stream to ensure that only symbols corresponding to the RS packet are passed to the soft demapper 2006. The soft demapper 2006 calculates the soft bit comparison amount using algorithms known in the art including, for example, algorithms described by Akay and Tosato. For proper operation, the soft demapper 2006 must know which puncturing mode (which is the gate rate) for the transmitter and the alignment of the mode with the received bit. The information 2021 is provided by the frame synchronization module 2020, which decodes the modal information and also provides a repetitive frame synchronization signal to the punctured mode aligned regardless of the current mode. These soft bit comparison quantities are fed to a Viterbi decoder 2008 operating in a manner known in the art. To arrive at an estimate of the bit of the PTCM encoder that is input into the transmitter.

The de-random generator 2013, the byte deinterleaver 2014, and the RS decoder 2016, which are synchronized by the frame synchronization signal 2021, respectively de-randomize, de-interleave, and decode the byte data to obtain the original input transmitter. RS encoder information.

Carrier phase offset correction

Certain embodiments of the present invention use a carrier phase offset correction system and method. In some embodiments, a receiver includes a phase offset corrector that receives an equalized signal representative of a quadrature amplitude modulation signal and derives a phase correction signal from the equalized signal; a splitter that splits the equalized signal to obtain a real and a virtual sequence; a frame synchronizer that uses a corresponding portion of the stored frame synchronization pseudo-random sequence and a phase provided by the frame synchronizer to the phase offset corrector Correction symbol to perform a correlation between real and imaginary sequences. The phase correction signal is based on the associated maximum real and imaginary values. The frame synchronizer performs continuous cross-correlation on the incoming split quadrature amplitude modulation symbols. The continuous cross-correlation uses one of the binary frame sync pseudo-random noise sequences to store the replicas separately for real and virtual sequences.

Base frequency to passband modulation

Some wireless digital communication systems, including broadcast, wireless LAN, and wide area mobile systems, use certain forms of QAM. QAM is also used in both North American and European digital cable television standards. Its use causes the two-side band-suppressed carrier modulated wave to occupy the same channel bandwidth of orthogonal carrier multiplexing, where each wave is modulated by an independent message. As discussed above, Figure 23 depicts a simple QAM modulator that can be used as PB mod 1314 in the example of Figure 13. An isolated transmission pulse QAM is given as follows: Where d _{R , m} and d _{I , m} are respectively determined by two independent message flows and represent the real and imaginary parts of a complex QAM symbol (see, for example, Figure 17), where m _R = 1 ... M indicates a 2D The cardinality of the QAM cluster, where M is the modulation carrier frequency and q ( t ) is a raised cosine pulse function.

A continuous series of transmitted QAM pulses s ( t ) (at a rate of F _s = 1 / T _s ) through a noisy multipath channel. Therefore, the received signal at the input to the QAM receiver is given by r ( t )= s ( t )* c ( t )+ v ( t ), where * refers to convolution, c ( t ) is a channel pulse Response, and v ( t ) is added to white Gaussian noise. therefore, Where d [ n ] is a complex transmission symbol, f ₀ and θ ₀ are respectively related to the frequency and phase offset of the receiver passband of the transmitter to the local oscillator demodulator local oscillator, so f _LO = f _c -f ₀ .

Passband to baseband demodulator

Figure 35 shows an example of PB to BB, sym clock synchronization, equalizer/carrier recovery module 2000 of Figure 20 in more detail. Received signal r (t) based in one symbol rate higher than the sampling rate 350, leading to the sampled signal r (Nt _samp). After sampling: Then, after demodulation, it is obtained by resampling and matching filtering according to the symbol rate 1/ T _s : Where v '[ k ] is a sample complex filtering noise. This assumption is due to the pulse shaping and matched filtering q , combined with the perfect symbol rate sampling timing, and any ISI is only due to the channel impulse response c . After demodulation, assuming perfect equalization, the near-basic complex sequence z [ k ] at the output of the equalizer is given as follows: Thus, the recovery of nearly represents transmission baseband sequence clusters, having a rotation frequency f ₀ by a phase offset θ _0. In order to reliably recover the transmissions d _R and d _I using, for example, a two-dimensional splitter, the equalizer (combined with a phase and frequency offset recovery loop) must remove the frequency offset f ₀ that causes the cluster rotation, and the receiver must Removing the remaining static phase offset that would otherwise cause the cluster to θ ₀ within a static rotational position.

In order to understand phase/frequency recovery, it is necessary to understand the QAM cluster at the fundamental frequency. In a simple example of Figure 33A, 4QAM modulation (which is also referred to as QPSK), the cluster consists of four symbols. In the example, the real and imaginary parts of d [ k ] can each take 2 different values (eg, ±3). The effect of the phase offset θ ₀ on the recovered d [ k ] is shown in Figure 33B, which shows one of the rotations in the complex plane. The effect of f ₀ is understood by taking note of the advancement in a circle (counterclockwise or clockwise depending on the sign of f ₀ ).

Equalizer and carrier phase/frequency loop

In Fig. 34, a signal x [ k ] 340 is received by a digital equalizer and carrier phase/frequency loop 248 (see, for example, Fig. 24A). The equalizer 341 component typically includes a linear digital filter, and using a proprietary or well known method such as a Least Mean Square (LMS) algorithm, the equalizer 341 determines its output y [ k ] and the splitter. A phase rotated version of [ k ] 343 is compared to generate an error signal for an update set used to calculate the filter order weights. This filter removes the ISI resulting from the channel impulse response.

2D splitter 342 separates z [ k ] and output independently [K] of the real and imaginary parts of which the original transmission lines D [k] is an estimate. z [ k ] and [ k ] Both enter phase error detector module 346 and are formed by e _θ [ k ]=Im{ z [ k ] *[ k ]} A given phase error signal. An integral ratio (IP) filter 345 can include the filter of Figure 35 or any equivalent known to those skilled in the art. The IP filter 345 allows the loop to correct both phase and frequency offsets. An output of the IP filter 345 feeds a complex voltage controlled oscillator (VCO) 344 that outputs a complex phase/frequency correction factor e ^{- jθ [ k ] that} corrects both θ ₀ and f ₀ . VCO344 also outputs e ^{+ jθ [ k ]} to split the output with "uncorrected" [ k ] so that it can be used to derive an error signal for the equalizer order update. This method is indicated because the equalizer operates on both θ ₀ and f ₀ .

In some embodiments, the efficiency can be obtained by implementing the VCO 344 in a discrete form as a delay to feed an integrator of a complex index lookup table (LUT). However, the last correction for θ ₀ may have an ambiguity of π/2, which means that the recovery phase can be corrected (offset=0) or can have an offset of π/2, one of π Shift, or an offset of 3π/4. These results are illustrated in Figures 36 and 37: an actual transmission symbol is shown in Figure 36 and the possible recovery symbols with respective offsets are shown in Figures 37A through 37D. Typically, the receiver cannot know which of the four possible symbols is actually transmitted because the 2D splitter 342 performs a closest neighbor operation. Figure 38 illustrates an example in which a transmission symbol a is received at the equalizer input as a' having θ ₀ . Thus, the phase recovery loop can rotate the signal to compensate for θ ₀ such that a' is aligned with a . However, the decision of the 2D splitter 162 would be the correct symbol b because it is closer to a' . This allows the phase recovery loop to converge in a manner that rotates the cluster so that a' is aligned with b . In this case, the final phase is offset by -π/2 from its original position.

Certain embodiments of the present invention provide methods for minimizing and/or eliminating such problems in a fence coding system, including a population of punctured fence codes for some of the presently described embodiments. As described above, the output of the equalizer is divided into real and imaginary directions by a 2D level divider 342 to form a sequence a _R [ k ] [-1, +1] and a _I [ k ] [-1, +1], which is fed to a frame sync module 2020 (see Figure 20). The frame synchronization module 2020 stores the replica by one of the binary frame PN sequences, and performs a continuous cross-correlation operation on the divided QAM symbols for the real and imaginary parts, respectively. Each member of the stored copy has a value of -1 or +1. The characteristics of this operation are therefore: Where s is a stored copy of the 127 long frame sync PN sequence. The maximum magnitude of b _R or b _I indicates the beginning of the FEC data frame.

For frame sync symbols, the real and imaginary parts have the same sign and the 39th figure shows their cluster. Therefore, it can be understood that the sign of the maximum magnitude b _R or b _I is positive for both zero rotations. A -π/2 rotation obtains a negative maximum magnitude b _R and a positive maximum amount b _I . For one rotation of π, both b _R and b _I are negative, and for one rotation of π/2, the maximum magnitude b _R is positive and the maximum magnitude b _I is negative. This is summarized in Table 5 above. Thus, the respective symbols of the maximum magnitude b _R and b _{I in} the combination indicate the quadrant of the complex plane in which the last phase offset has converged. This allows an additional phase correction to be applied to the signal, as shown in Figure 20. The maximum b _R and b _I symbol autocorrelation is transmitted to the phase offset corrector for the main frame sync module. The operation of a phase offset corrector module is shown in Figure 40, and an LUT operation 404 is illustrated in the example. Given z [ k ]= z _R [ k ]+ jz _I [ k ], this operation can be simply performed as follows: 1. For the case of ψ=+ θ : z' [ k ]=- z _R [ k ]- Jz _I [ k ]2. For ψ=+π/2: z' [ k ]=- z _I [ k ]+ jz _R [ k ]3. For ψ=-π/2: z' [ k ]=+ z _I [ k ]- jz _R [ k ] Figure 40 represents a phase correction derived by indexing a lookup table with a correlation of maximum associated true and imaginary values according to certain aspects of the present invention. A block diagram of the phase offset corrector of the signal.

Multimodal QAM cluster detection

Certain embodiments provide systems and methods for determining an unknown QAM cluster from a set of possible QAM clusters. Method of use The inter-symbol interference (ISI) has been corrected by a modified constant modulus algorithm (CMA) equalizer, but the power of the signal before the carrier frequency and phase have fully recovered. The unknown cluster is then determined from the histogram. The equalization procedure is then restarted with the standard CAM based on the currently known cluster to minimize ISI. The equalizer output can be scaled correctly, after which a reduced phase of the cluster carrier recovery (RCCR) can be implemented and the associated carrier recovery can be determined, resulting in recovery of the carrier frequency and phase by combining the equalizer carrier frequency/phase loop. In another method for deciding an unknown QAM cluster, the equalizer initially uses modified CMA operations to minimize ISI. Although the equalizer output may not be properly scaled at this point in the program, the equalizer carrier frequency/phase loop can recover the carrier frequency and phase with the RCCR without knowing the cluster. The recovered phase can be noisy. The receiver can read the information embedded in the signal frame indicating which QAM cluster is transmitted. The equalizer operation is then restarted with a standard CMA based on the known cluster, followed by RCCR and decision related carrier recovery.

Certain embodiments of the present invention use a combination of punctured fence coding and QAM clustering, similar to those used for ISDB-T and the above. As used herein, a cluster is understood to mean one of the complex planes of a possible symbol within a modulation scheme. The number of symbols per frame depends on one of the modal variable integers and the number of RS packets per frame is a constant integer regardless of the modality. This configuration is described in more detail above and simplifies the design of a receiver.

Referring again to FIG. 20, the frame synchronization module 2020 stores a copy using one of the binary frame sync PN sequences, and performs a continuous cross-correlation operation on the divided split QAM symbols 1219 for the real and imaginary parts, respectively. Each member of the stored copy has a value of -1 or +1. This operation is given by Equation 10 (above) and is repeated here: Where s is a storage replica in the 127 long frame sync PN sequence. The maximum magnitude of b _R or b _I indicates the beginning of the FEC data frame.

As will be explained in more detail below, the recovery carrier phase has an uncertainty of π/2. This results in an arbitrary additional recovery phase offset of zero, ±π/2 or π. For frame sync symbols, the real and imaginary parts are the same symbol and Figure 39 shows their transport cluster. Therefore, it can be understood that for a zero phase offset, the sign of the maximum magnitude b _R or b _I is both positive. As outlined in Table 404 of Figure 40, a -π/2 offset will result in a negative maximum magnitude b _R and a positive maximum magnitude b _I ; for a shift of π, both b _R and b _I It will be negative, and for a shift of π/2, the maximum magnitude b _R will be positive and the maximum magnitude b _I will be negative. Thus, the respective symbols of the maximum magnitudes b _R and b _{I in} the combination may indicate the quadrant of the complex plane to which the final phase offset converges. This allows an additional phase correction to be applied to the signal in phase offset corrector module 2002. The symbolic auto-correlation of the maximum b _R and b _I is transmitted to the phase offset corrector 2002 by the main frame synchronization module 2020.

Referring additionally to Fig. 40, the operation of certain aspects of phase offset corrector 2002 in the example of Fig. 20 can be more appreciated. LUT 400 produces an output based on the symbols of the maximum magnitudes b _R and b _I (see element 404 of Figure 40). Given z [ k ]= z _R [ k ]+ jz _I [ k ], operation 402 can be performed as follows:

1. For the case of ψ=+π: z' [ k ]=- z _R [ k ]- jz _I [ k ]

2. For the case of ψ=+π/2: z' [ k ]=- z _I [ k ]+ jz _R [ k ]

3. For the case of ψ = -π/2: z' [ k ]=+ z _I [ k ]- jz _R [ k ]

Once the frame sync start position is found and the m π/2 phase offset is corrected, the location of the code character containing the modal bit (cluster and fence rate) is known. The codeword can be reliably decoded by, for example, a BCH decoder or by correlating the received codeword with all possible codewords and selecting the codeword that produces the highest resulting value. Because this information is transmitted repeatedly, additional reliability can be obtained by requiring the same result to occur multiple times before accepting it.

Figure 41 shows an example of such a procedure that can be performed by the frame synchronization module 2020. In response to the frame sync signal 2021, at step 4100, the received cluster code character is cross-correlated with all valid code characters. Cross-correlation generation can be used to select one of the most likely matches. In an example, the valid codeword that produces the largest correlation value is selected at step 4102. This selected code character can then be used to identify a current cluster. At step 4104, the current cluster's identification is compared to the recorded or stored identification of a previously identified cluster. At step 4104, if the current cluster and the previously identified cluster are the same cluster, a trust count may be added. If it is determined in step 4104 that the previously identified cluster is different from the current cluster, then the current cluster is recorded as a previously identified cluster in step 4107 and the trust count is decremented in step 4107 and another synchronization frame is waiting at step 4109. Step 4106 relies on After incrementing the count, the trust count is checked at step 4108, and if it is determined at step 4108 that a predetermined or configured threshold is exceeded, a decision to signal cluster can be made at step 4110. This procedure can be repeated until the confidence count exceeds the predetermined or configured threshold.

Equalizer and carrier phase/frequency loop

Referring to Figure 42, certain aspects of the equalizer and carrier phase/frequency loop 248 of Figure 24A will be described. A signal x [ k ] enters the digital equalizer and carrier phase/frequency loop 248, which may include an equalizer 420 (which includes a linear digital filter). An error calculator module 422 calculates an error signal e [ k ] that can be used to calculate an updated set of filter step weights using any suitable method known to those skilled in the art. In an example, an LMS algorithm can be used. The filter removes the ISI resulting from the channel impulse response c . One of the equalizers 420 outputs y [ k ] followed by a phase rotation at 421 to reduce any remaining carrier phase and frequency offset. The phase rotation output z [ k ] is then processed by a divider and phase error detector module 427 which computes a phase error value e _θ [ k ] fed to an integral ratio (IP) filter 426. The IP filter 426 outputs an integrator and a complex index lookup table (LUT) 424 that calculates a complex index value for the loop to correct the carrier phase and frequency offset. The splitter and phase error detector module 427 also outputs a two-dimensional split symbol decision closest to the neighbor, whose phase is multiplied by e ^{+ jθ [ k ]} at 425 and is "uncorrected" and then used for error. Calculator module 422. The error calculator module 422 uses the input and x [ k ] to calculate an error signal e [ k ]. As described, the internal operations of the error calculator module 422 and the splitter and phase error detector module 427 depend on a current phase of operation (1, 2, or 3) as determined by the phase manager 423.

In some embodiments, a least mean square (LMS) algorithm is used to calculate the equalizer filter order weights and operates as follows: if x [ k ] represents an L long equalizer output vector, y [ k ] An equalizer output vector is represented, where y [ k ]= g ^H [ k ] x [ k ], where g ^H [ k ] is an L long equalizer step weight vector and the H superscript indicates a conjugate shift term (Hermitian). Next, the update e [ k ] in the error calculator module 422 is calculated using, for example, the method described below: g [ k +1]= g [ k ]-2 μx [ k ] e ^* [ k ], (Equation 11 Where μ is a small step size parameter and * superscript indicates a complex conjugate.

In an example, the stage manager 423 employs an equalizer and carrier phase/frequency loop 428 throughout the three phases of operation, whereby the switching from phase 1 to phase 2 to phase 3 is based on the simplicity of the input data sample x [ k ] Counting threshold execution. It should be noted that complex phase switching based on an estimate of the error at the output of the equalizer is also possible. The three stages are summarized in Table 6.

A splitter and phase error detector module 427 is shown in more detail in FIG. Switch 430 is set according to one of the three stages of operation 434. During phase 1, switch 430 is in the highest position such that e _θ [ k ] = 0. This effectively turns off the carrier loop so there is no carrier phase correction during this phase. During phase 2, switch 430 is in the intermediate position and the loop uses a reduced cluster carrier recovery (RCCR) algorithm operation. If the power of the symbol z [ k ] given by | z [ k ]| ² exceeds a threshold value, then it is assumed that z [ k ] is one of the corner symbols of the cluster and the RCCR is set by the description. The second switch 432 is energized to the upper position, producing e _θ [ k ]=Im{ z [ k ] α [ sign ( z ^* [ k ])]}. Otherwise, if | z [ k ] ² That is, the second switch 432 deactivates the carrier loop by describing the position below. Only a subset of the symbols during phase 2 can act on carrier recovery. The threshold ξ can be reduced to include more symbols in the area near the corner of the cluster, but the resulting phase correction term e _θ [ k ] will be more noisy. During phase 3, switch 430 is at the lowest described position, producing e _θ [ k ]=Im{ z [ k ] ^* [ k ]}, its armor ^* [ k ] is the closest 2D separation symbol to the neighbor The complex conjugate of [ k ]. During phase 3, it is assumed that sufficient time has elapsed, so the equalizer order has converged and the carrier phase has been substantially corrected so that the split symbol decision is reliable. In particular, the relationship e _θ [ k ]=Im{ z [ k ] α [ sign ( z ^* [ k ])]} and e _θ [ k ]=Im{ z [ k ] ^* [ k ]} operates effectively in a single quadrant of the complex plane. This leads to the uncertainty discussed above in recovering the m π/2 in the carrier phase.

An example of an IP filter 426 (see Figure 42) is shown in more detail in Figure 35. The IP filter 426 allows the loop to correct both phase and frequency offset. The output of IP filter 426 feeds the integrator and complex exponent LUT module 424, which is shown in more detail in FIG. The input of integrator/LUT 424 is added to modulo 2π at 440 (Fig. 44) to the input portion of delay one step 442 to form a phase error signal θ [k] fed to a lookup table (LUT) 444, LUT 444 output The phase correction factor 445 ( e ^{- jθ [ k ]} ) of both θ ₀ and f ₀ is corrected. LUT 444 also provides an output 446 ( e ^{+ jθ [ k ]} ) with its "uncorrected" splitter output [ k ] so that it can be used to derive an error signal for the equalizer order update. This is required because the equalizer operates on x [ k ] containing both θ ₀ and f ₀ .

Error Calculator Module and Stage Operation Overview

The error calculator 422 can calculate e [ k ] using different methods depending on the stage. For stages 1 and 2, a program calculation based on a constant modulus algorithm (CMA) is typically used: e [ k ] = y [ k ](| y [ k ] ² - R ), where R is a predetermined constant , which is given by: And wherein E is a pre-expected operand and d [ k ] is a symbol (see Figure 17). Note that the order update derived from Equation 11 above is independent of the symbol decision and the phase of x [ k ] and depends only on the statistics of the equalizer output, the equalizer input, and the cluster. It can be shown during phases 1 and 2 that using CMA error for driving equation 11 is equivalent to minimizing ISI even if the cluster is rotated due to carrier frequency and phase offset.

Therefore, during Phase 1, the phase/frequency recovery loop is deactivated and the equalizer uses the CMA error function to minimize ISI. After ISI has been minimized, Phase 2 begins and the loop opens for the RCCR; carrier phase/frequency recovery begins with only the corner symbols of the cluster, as previously explained with respect to Figure 43. At the end of phase 2, the carrier phase and frequency have been fully recovered, so that the 2-dimensional splitter 436 of Fig. 43 begins to output a reliable symbol decision. [ k ].

The decision correlation (DD) error can be used in Phase 3. The DD error can be calculated as e [ k ]= e ^{jθ [ k ]} [ k ]- y [ k ]. For the purposes of this description, it is assumed here that the receiver has decided to transmit which of the clusters in Figure 17 of the three clusters, since R is different for each of these clusters. In addition, RCCR requires knowledge of the cluster, and in particular the power of the corner symbols of the cluster.

CMA with an unknown cluster

In the examples described herein, one of three different QAM clusters can be transmitted and the above-described equalization and phase/frequency recovery requires knowledge of the transmitted cluster. When the cluster chooses to encode in the modal symbol, the equalization and phase/frequency recovery precedes the frame synchronization (see Figure 20), where this information can be decoded directly as described above (see Figures 18, 20 and 41). Thus, in some embodiments, the cluster is determined within the equalizer and carrier recovery algorithm itself.

Note that this R (as provided in Equation 12) is cluster dependent. In some embodiments, and with continued reference to Figure 17, the real and imaginary parts of the symbols of 64-QAM are selected from the set ±{1,3,5,7}, the real and virtual of the symbols of 16-QAM. The ministry is selected from the set ±{2,6}, and the real and imaginary parts of the symbol of QPSK are selected from the set ±4. According to Equation 12, the value of R will be: For any of the three clusters in Figure 17, it can be shown that using a scaling value αR for CMA error calculation causes the equalizer filter order to converge to Scales the same set of values, where the equalizer output is scaled as such. However, it can show the least ISI. In one instance of the cluster unknown, R can be set to 58, and the ISI will be minimized during Phase 1 regardless of the cluster being transmitted. For the example, any R value in the range of 32 to 58 will be used. However, the selection of the maximum (i.e., 58) prevents compression of the densest cluster (here 64-QAM) at the output of the equalizer and reduces the burden on the equalizer performance.

The result of using the scaling parameter R results in an equalization of the output of the equalized output by the convergence filter stage, so the statistics of the equalizer output will be: E {| y [ k ]| ⁴ }/ E {| y [ k ]| ² }=58, which assumes perfect ISI removal and regardless of clustering. Therefore, for QPSK, the equalizer output will have the ISI minimized and scaled during Phase 1.

Figure 45A illustrates the real part for an equalized output with one of the QPSK systems where θ ₀ = f ₀ =0. It can be seen that the output is due to the value of R = 58 Scaling because the equalizer converges to remove one of the ISI solutions. Figure 45B illustrates the real part for an equalized output with one of the 16-QAM systems where θ ₀ = f ₀ =0. because Relatively close to 1, the real part of the equalizer output appears to be only slightly scaled. Therefore the actual scaling is evident during the equalizer convergence.

Cluster detection method

In some embodiments, the histogram method can be used to determine the cluster before entering phase 2. The cluster can be determined even if the carrier phase and frequency have not been recovered. Consider a histogram of the power of η [ k ] = y [ k ] y ^* [ k ] for the equalizers of QPSK, 16-QAM, and 64-QAM clusters, respectively, in Figures 46A, 46B, and 46. The histogram represents the power after the equalizer has converge with R = 58. Because the power of the equalizer output is independent of the phase and the histograms of the clusters are substantially different, the cluster of transmitted power can be determined by the equalizer output power histogram in the receiver.

Without additive or order noise, for a QPSK cluster, the power of each equalizer output sample is η [ k ]=58. For a 16-QAM cluster, the probability quality function for the equalizer output power: Similarly, for a 64-QAM cluster, the probability quality function for the equalizer output power is:

Due to the order update noise and the added noise v' on the input signal, even if for example one of the 30 decibels, the substantial SNR has some expansion in the histogram around this value. The noise on the output of the analog equalizer is added and independent of the symbols, and assuming that the output has no ISI, then: | y [ k ]| ² =| d [ k ]+ n [ k ]| ² = | d [ k ]+ n [ k ]| ² =| d [ k ]| ² +| n [ k ]| ² +2Re{ d [ k ] n ^* [ k ]} (Equation 16 is in a given symbol The upper adjustment relates to the change of the 2Re{ d [ k ] n *[ k ]} term with increasing symbol power. In the histogram diagram, this phenomenon appears as expansion (ie, variation), which surrounds the increment One of the given powers is increased by the given power. In the 16-QAM case, the expansion of the cluster power for the symbol ± 2.1 ± j 2.1 is less than the expansion of the cluster power for the symbol ± 6.3 ± j 6.3.

Some other relationships can be observed from the histogram of the output power of the equalizer:

In the QPSK histogram, the region T ₁ falls roughly between the second and third regions (R ₂ and R _{3 , respectively} ) in the histogram of 16-QAM. Therefore, for QPSK and 16-QAM clusters, the areas in which symbols are transmitted are not overlapped.

● QPSK histogram reveals Pr{ η [ k ] for one of the histograms of 64-QAM T ₁ }<Pr{ η [ k ] T ₁ } is used for 64-QAM. Therefore, for a comparison of η [ k ] to the region T ₁ , η [ k ] is more likely to be outside the region.

• When there is no noise in the 64-QAM instance, η [ k ] takes a value from the set {2, 18, 26, 34, 58, 98} at a probability of 9/16. Therefore, when the lower cluster is 64-QAM, the noise is ignored: Where U indicates an OR. Therefore, if the transport clusters 64-QAM and η [ k ] are compared with the regions R ₁ , R ₂ and R ₃ , η [ k ] is more likely to be outside of these regions.

Some specific embodiments use algorithms based on such observations: The algorithm may be initialized after the equalizer converges, and the QPSK counter λ ₄ [ k ] is incremented in the first portion if the equalizer output power passes through the N equalizer output sample in region T ₁ . If the equalizer output power is not in the region T ₁ , the counter is decremented. Similarly, if η [ k ] is in the regions R ₁ , R ₂ and R ₃ , the 16-QAM counter λ ₁₆ [ k ] is incremented, otherwise it is decremented.

After the N equalizer outputs a sample, it can assume that the histogram has been correctly described. If the cluster below is 64-QAM, the QPSK and 16-QAM counters will be extremely small, since the power estimate η [ k ] will be more likely to fall outside the QPSK and 16-QAM regions. If the transport cluster is QPSK or 16-QAM, the counter of the transport cluster will be significantly larger. therefore, The threshold M can be determined empirically, but should be smaller than N. The algorithm is extremely robust, and when transmitting QPSK, 16-QAM or 64-QAM, the correct cluster is reliably selected for low signal-to-noise ratio (SNR). After the cluster has been reliably determined, R can be set to correct Equation 13 values and Phase 1 can be performed to completion. The equalizer output will be scaled appropriately and Phase 2 can begin with the knowledge of the thresholds required by the RCCR.

Another method of determining the cluster before the equalizer enters phase 3 will now be described. In this method, Phase 1 is executed and allowed to be completed with R = 68. Thus, and as already explained, all three clusters will have been scaled at the equalizer output resulting in y [ k ] as shown in the three clusters of Figure 47, although such clusters will likely rotate. As discussed with respect to Figure 43, for a critical phase of the Phase II RCCR, only the symbols in which the power of the symbol z [ k ] given by | z [ k ]| ² exceeds a threshold value are considered. It then assumes that z [ k ] is one of the corner symbols of the cluster. Similarly, | z [ k ]|> A corner symbol can be indicated. It is relatively easy to select a value of ξ when the cluster is known, as illustrated in Figure 48(A) for a 64-QAM cluster. Figure 48 shows all three clusters at the equalizer output and the carrier phase/frequency recovery loop module input. It can be seen that for the corner point | z [ k ]|= 9.90. For example, a threshold indicated by dotted circle 484 Make sure to only select corner points. Similarly, one Round 482 and one Circle 480 can use the margins of the more abundant for 16-QAM and QPSK, respectively.

Figure 49 shows an overlay of the upper right quadrant of all three clusters. Visible Only for the corner points of QPSK and 16-QAM (falling outside the circle) will be used by the RCCR. However, if 64-QAM is received, the five cluster points (four non-corners) fall outside the circle and will be utilized by the RCCR. Because the recovery phase is less noisy, the RCCR typically works better if only corner cluster points are used. However, even with some extra points, the RCCR can successfully recover the phase, although phase noise increases. Therefore, Phase 2 is initially available Operation, allowing proper initial carrier recovery for all three clusters while the cluster remains unknown to the receiver.

As described above with respect to FIG. 20, the equalizer 2000 feeds a 2-bit quasi-divider 2018 which in turn feeds the frame sync 2020. The frame synchronization module 2020 can perform a continuous cross-correlation operation on the symbols of the incoming split QAM symbols using a stored copy of the binary frame PN sequence as described in Equation 10. Continuous cross-correlation operations can be performed separately for real and imaginary parts. Each member of the stored copy has a value of -1 or +1. The maximum magnitude of b _R and b _I indicates the beginning of the FEC data frame. The only difference is that for a 64-QAM cluster, the 2-bit quasi-divider 2018 operates on a signal with some additional phase noise. However, this extra phase noise has little negative impact on 2-bit quasi-segmentation and subsequent cross-correlation as main frame synchronization, which is robust even with phase noise. As previously described, the decoding of cluster codewords is also robust to phase noise.

Figure 50 illustrates the operation of determining this alternative to the cluster, which can be summarized as follows:

(1) The equalizer and phase/frequency loop complete phase 1 with R = 58 and then enter phase 2.

(2) Without waiting for phase 3, during phase 2, the associated master frame synchronization 2020 accepts input data, finds frame synchronization, and decodes cluster code characters.

(3) The decision cluster information 2021 is transmitted back to the equalizer 2000 and the phase/frequency loop, the appropriate use of which corresponds to determining one of the cluster R values back to phase 1.

(4) Then complete stages 1, 2 and 3 as before. It will be appreciated that the primary differences between the systems depicted in Figures 50 and 20 are the additional connections 5000 from the frame synchronization 2020 to the equalizer/carrier recovery 2000 carrying the cluster information.

SPOT monitoring in coaxial security links

The performance of the improved system and apparatus in some embodiments of the present invention includes the above description and wherein the baseband video signal can be combined with the digital representation of the baseband video signal and the control signal to achieve, for example, a coaxial cable (coax). Single cable transmission. Referring again to FIG. 4, an embodiment of the present invention provides a system through a Coax Secure Link (SLOC). Figure 5 shows one of the possible modulation schemes for the SLOC system. In this example, the HD camera 30 provides a compressed digital HD view. One of the video images 332 has an IP output 41 and an auxiliary camera signal comprising an analog SD CVBS 330. The compressed HD video IP signal 332 is modulated to a passband 52 by a SLOC camera side modem 49, and the SLOC camera side modem 49 includes a QAM modulator (see the modulator 212 in the modem 32 of Fig. 21). . Modulator 212 provides a modulated signal that can be combined with a baseband analog CVBS signal 330. The combined signal is transmitted "downstream" through coaxial cable 41, typically extending to a distance of 300 meters or more. On the monitor side, a SLOC monitor side modem 45 separates the baseband CVBS signal 330 from the passband downstream IP signal 332. The separated CVBS signal 330 is fed into an SD display 43 for on-site, no-delay viewing. The passband downstream IP signal 332 is demodulated with a QAM demodulator (see demodulator 222 in FIG. 22), which outputs a signal to the main network switch 44 or a processor/DVR (not shown in FIG. 4). ).

In this example, uplink communication is provided in accordance with IP requirements. Uplink communication 334 can additionally transmit audio and camera control signals 42 to camera 40 from the monitor side. Typically, the bit rate of the upstream signal and the corresponding required bandwidth will be much lower than required for the downlink passband signal. The monitor side SLOC modem 45 includes a QAM modulator (see modulator 224 in FIG. 22) that modulates the IP signal to the upstream passband 44. As depicted in Figure 5, the upstream passband 54 and the downstream passband 52 are located at different spectral locations. On the camera side, the SLOC modem includes a QAM demodulator 49 (see demodulator 214 in the data engine of Figure 21) for receiving the upstream signal. This approach offers several advantages over previous systems and methods, including increased operating range, ease of deployment with existing coax infrastructure, and low latency, ie Video. The simplified schematics of Figures 21 and 22 show additional details of the SLOC camera side data machine of Figure 4 and the SLOC monitoring side data machine 45 of Figure 4.

Figure 51A shows a SLOC system based on the system illustrated in Figure 4, wherein a filter stage 519 is provided between coaxial cable segments 512 and 514 to operate the stage 513 and cable segments 512 and 514 to interface with camera side equipment and monitoring. Side component. The filtered stage 513 is typically used to capture at least a portion of the baseband CVBS signal 5100 to the camera side SD display 5130. Display 5130 can be provided near camera 510 for testing, setting, and/or local monitoring. Filter stage 513 typically includes a low pass filter that blocks unwanted signals that may interfere with display function 5130, such as modulated digital, IP, and/or control signals. Stage 513 can also include a filter or switch that blocks signal transmission between data machines 511 and 515. For example, a test data machine 5131 can be connected through the stage 513 to enable fault diagnosis or to initially set the camera side data unit 511 and the display side data machine 515 can be turned off to avoid signal interference and/or degradation. As shown in FIG. 5, the SLOC camera side data unit 511 typically outputs a low pass QAM signal and a base frequency CVBS signal 5100 based on the portion of the signal 5102 generated by the camera, and the SLOC monitoring side data machine 515 is based on the signal 5170. The control signal outputs a high pass QAM signal. One or more filters may be provided by stage 513 to avoid undesirable interferences that may be seen on SD displays 5130 and/or 516, and to block IP and control signals. It should be appreciated that some displays and monitors lack the filtering required to block higher frequency signals in the passband signal (relative to the baseband CVBS signal 5100).

FIG. 51B shows a SLOC system based on the system illustrated in FIG. 3, in which the cable 514 between the camera side and the monitoring side has been temporarily disconnected on the camera side, and an SD display device or monitor 5130 has been transmitted. The cable segment 519 is directly connected to the SLOC camera side data unit 511. A test data machine 5131 can be connected for testing/setting purposes as needed. The SD display device 5130 displays the baseband CVBS signal and provides a capability to monitor video from the camera 510 near the physical location of the camera 510 and may require reconfiguration of the connection to facilitate setup and troubleshooting. In Fig. 51B, the low passband QAM signal 5102 can cause undesirable visible interference on the SD display 5130 lacking high frequency filtering.

In the example shown in Figures 51A and 51B, partial or complete disconnection of the signal between the data machines 511 and 515 may occur. Partial disconnection of the signal allows the QAM signal transmission path to remain intact. However, some reconfiguration of the connection causes the QAM signal transmission between the camera side data machine 511 and the monitoring side SLOC data machine 515 to be broken. Some embodiments of the present invention provide a mechanism for the camera side data unit 511 to stop the passband QAM transmission by the mechanism when the connection between the data machines 511 and 515 is disconnected, and output only the CVBS signal. It will be appreciated that temporarily replacing the display data machine with the test data machine 5131 typically includes a program that includes disconnecting between the data machines 511 and 515, establishing a connection between the data machines 511 and 5131, and disconnecting between the data machines 511 and 5131. And establishing a connection between the data machines 511 and 515. The disconnection of the QAM signal can be detected using various functional components of the modem 511. Therefore, the operation of the SLOC system is described in detail below.

QAM modulator structure for a SLOC system

As described above, FIG. 19 illustrates a frame structure 1336 provided to the passband modulation (PB) module 1314 (see FIG. 13). The fence coding of Figure 16 adds bits; the number of data bits per mapped QAM symbol before the fence is encoded (as shown in Table 2). The number of QAM symbols mapped by the 315RS packet (521640 bits) of Figure 14 varies with modal selection. Using the RS packet size of each frame 207 and 315 packet, an integer number of symbols are obtained for each frame, as shown in Table 3. The PB Mod module 1314 then modulates the baseband QAM symbols to the passband using any suitable method known to those skilled in the art. (See, for example, the description above with respect to Figure 24).

As described above, with reference to Fig. 20, the QAM demodulator of Figs. 21 and 22 will be further described. Module 2000 receives the transmitted data in a passband signal and converts it into a baseband QAM symbol. The operations performed by module 2000 may include symbol clock synchronization, equalization (to remove inter-symbol interference), and carrier recovery, which typically employs sub-modules. Thus, module 2000 can include an equalizer whose output restores the fundamental frequency QAM symbol 2001. The baseband QAM signal 2001 is provided to a two-bit quasi-splitter 2018 for segmentation in both real and imaginary directions to form a sequence a _R [ k ] [-1, +1] and a _I [ k ] [-1, +1] 2019, which is provided to the frame synchronization module 2020.

The frame synchronization module 2020 synchronizes a stored copy of the PN sequence with the binary frame and performs a continuous cross-correlation operation on the incoming split QAM symbols 2019 for the real and imaginary parts separately. Each member of the stored copy has a value of -1 or +1. This operation is given by Equation 1, repeated below: Where s is a storage replica in the 127 long frame sync PN sequence. The maximum magnitude of b _R or b _I indicates the beginning of the FEC data frame. A frame sync pulse or other synchronization signal is transmitted to one or more of the receiver modules when the start of the FEC data frame is detected in the stream.

Figures 52A and 52B show elements of a program that can reliably generate a frame sync pulse when a noise signal is received. Figure 52A shows a portion of the procedure for determining the frame length. The frame length can vary depending on the selected transmission mode (Table 3). A program starting at step 5200 is repeatedly executed when the symbol is received, and a symbol counter tracks some symbols between executions, which results in a value at a predetermined threshold. At step 5201, cross-correlation is performed for each arriving symbol and the symbol counter is incremented until it is determined at step 5202 that the predetermined threshold has been exceeded. The symbol counter increments 5203 for each symbol until the threshold is exceeded. When the threshold is exceeded at step 5202, the symbol counter 5204 is cleared and the steps of cross-correlation 5205, increment symbol counter 5207, and receipt of a new symbol 5208 are repeated until it determines that the threshold has been exceeded at step 5206. . An intermediate symbol count is recorded at step 5208 and the symbol counter is reset at step 5209. The cross-correlation 5210, the increment symbol counter 5212, and the step of receiving a new symbol 5213 are repeated until it determines at step 5211 that the threshold is exceeded. If the symbol is counted at step 5214 The device is the same as the intermediate symbol count recorded at step 5208, and the frame length is returned to the value of the symbol counter at 5215. It should be understood that in the above example, the frame length can be determined after two consecutive consistent counts. However, the number of consecutive identical counts required may be selected as desired.

Figure 52B illustrates a procedure by which the frame sync module 2020 can generate a correct timing frame sync pulse even when the received signal is extremely noisy. The program is also provided for capturing a new frame sync position when a temporary interruption of the signal occurs, or when the transmission mode change causes the frame_size to change. A free running symbol counter receives the symbols using the modulus frame_size arithmetic count, where frame_size has been determined by the steps described with respect to Figure 52A. It has been expected that when the result of the cross-correlation of Equation 10 exceeds the selected threshold, the symbol counter value will always have the same value. When the values are consistent, a trust counter is incremented until a selected maximum value (e.g., a maximum value of 16); otherwise, the trust counter is decremented to a minimum of zero.

Thus, when a symbol is received at 5250, cross-correlation is performed at 5251, and if the result at 5252 exceeds the threshold, the current maximum is set to a threshold at 5253 and a maximum point is set to The current value of the symbol counter. In the example, if the trust counter is set to at least 4 (5254) and the current symbol count indicates a frame sync point (5255), then the frame sync signal is output at 5256. Second, the symbol counter is incremented at 5257, where modulo 4 addition is used. The next symbol waits at step 5277 unless it is determined at step 5270 that the symbol counter is zero. If the symbol counter is zero, reset at 5271 The current maximum. Next, at 5272, if the current maximum point is equal to the frame sync point, the trust counter is incremented at 5273 and the next symbol is waited at step 5277; otherwise, the trust counter is decremented at 5274. In the presently illustrated example, if it is determined at step 5275 that the trust has fallen below 2, the frame sync point is set to the current maximum point at step 5276. In either case, the next symbol waits at step 5277.

In summary, according to the above procedure, it is determined that frame synchronization has been reliably obtained when the trust counter exceeds a predetermined value (4 in this example). The frame sync module can then be cleared to provide a frame sync pulse at the correct time. If the trust counter exceeds 4, the frame sync pulse will be output at the correct time (typically corresponding to the beginning of a frame), even if the noise occasionally causes Equation 10 to produce a low value.

If the transfer mode changes, the trust counter will eventually count back to zero. This can be used to trigger a recalculation of one of the frame lengths that determine the length of the new frame (eg, using the procedure in Figure 52A). As will be described below with respect to carrier recovery, there may be an π/2 uncertainty in the recovered carrier phase, which may result in an arbitrary additional recovered phase offset of zero, ±π/2 or π. For frame sync symbols, the real and imaginary parts are the same symbol and the transport cluster is shown in Figure 39.

Therefore, it should be understood that for a zero phase offset, both the symbols of the maximum magnitudes b _R and b _I are positive. As summarized in Table 5, the -π/2 offset will result in a negative maximum magnitude b _R and a positive maximum magnitude b _I ; for a shift of π, both b _R and b _I will be negative, and For a shift of π/2, the maximum magnitude b _R will be positive and the maximum magnitude b _I will be negative. Thus, the respective symbols of the maximum magnitudes b _R and b _{I in} the combination may indicate the quadrant of the complex plane in which the final phase offset has converged. This allows an additional phase correction to be applied to the signal in phase offset corrector module 2002 (Fig. 20). The symbol autocorrelation of the maximum b _R and b _I is transmitted to the phase offset corrector 2002 by the main frame synchronization module 2020.

Referring additionally to Fig. 40, some aspects of the phase shift corrector 2002 in the example of Fig. 20 can be better understood. The LUT 400 produces an output based on the symbols of the maximum magnitudes b _R and b _I (see Table 5). Given z [ k ]= z _R [ k ]+ jz _I [ k ], operation 402 can be performed as follows:

(1) For the case of ψ=+π: z' [ k ]=- z _R [ k ]- jz _I [ k ]

(2) For the case of ψ=+π/2: z' [ k ]=- z _I [ k ]+ jz _R [ k ]

(3) For the case of ψ=-π/2: z' [ k ]= +z _I [ k ]- jz _R [ k ]

Once the frame sync start position is found and the m π/2 phase offset is corrected, the location of the code character containing the modal bit (cluster and fence rate) is known. The codewords can then be reliably decoded by, for example, a BCH decoder or by a codeword that will receive the received codewords associated with all possible codewords and select the highest resulting value. Because this information is transmitted repeatedly, it can be required to generate multiple identical results before acceptance for additional reliability. Figure 41 shows an example of a program that can be implemented by the frame synchronization module 2020.

Continuing with the system of FIG. 20, the frame synchronization signal 2021 output by the frame synchronization module 2020 can be used to indicate which symbols are to be removed in the module 2004 before the symbols are fed to the soft demapper. In an example, the 127 frame sync symbol and the 8-modal symbol are removed from the stream. The symbols corresponding to only the RS packets are passed to the soft demapper 2006. The soft demapper 2006 uses this technique algorithm to calculate soft bit metrics, such as those described by Akay and Tosato. For proper operation, the soft demapper 2006 must know which puncturing mode (which is the gate rate) for the transmitter and the alignment of the mode with the received bit. The information 2021 is provided by the frame synchronization module 2020, which decodes the modal information and also provides a repetitive frame synchronization signal to the puncturing mode, regardless of the current mode. These soft bit comparison quantities are fed to a Viterbi decoder 2008 operating in a manner known in the art to arrive at an estimate of the bits of the PTCM encoder that are input to the transmitter. The de-random generator 2013, the byte deinterleaver 2014, and the RS decoder 2016, which are synchronized by the frame synchronization signal 2021, respectively de-randomize, de-interleave, and decode the byte data to obtain the original input transmitter. RS encoder information.

Stage switching

Some embodiments use phase switching based on an estimate of the mean square error at the output of the equalizer. An accurate estimate of the mean square error at the output of the equalizer can be obtained from a series of errors e [ k ] calculated by the error calculator module 422 of FIG. For example, an estimate can be obtained by using: MSE [ k ] = (1 - β ) e ² [ k ] + βMSE [ k -1], (Equation 18) where β <1 is a forgetting factor. Other methods for averaging e [ k ] are known and available for use. Equation 18 produces a result that can be compared to a predetermined threshold and is used by phase controller module 423 of Figure 42 to switch from phase 1 to phase 2 when MSE [ k ] falls below the threshold. . It can be compared to a second predetermined threshold to switch from phase 2 to phase 3 operation when MSE [ k ] falls below the second threshold.

Detect disconnection and reconnection

Certain embodiments provide systems and methods for detecting disconnection and reconnection events on the camera side of a communication link. Referring again to Figures 51A and 51B, partial or complete disconnection of signals between data machines 511 and 515 can occur during normal operation. Some disconnection affects the QAM signal between the camera side modem 511 and the monitoring side SLOC modem 515. In particular, the signals carrying the images captured by the HD camera 510 are encoded and/or modulated by the data machine 511 for transmission to the display side data unit 515 via the cable 514. A plurality of methods for detecting disconnection and reconnection events with respect to the coaxial 514 can be performed by the camera side SLOC modem 511. In response to a disconnect or reconnect event, data modem 511 may suspend, start or resume downlink passband QAM transmission. In some embodiments, a "coaxial connection" signal transmitted from a QAM demodulator to a QAM modulator can be used to control the transmission for connecting related events.

Referring to Figure 53, for example, a camera side QAM demodulator 530 can be configured to transmit a line passband signal 533 only when a coaxial connection signal 531 is verified by a camera side QAM modulator 532. Camera side QAM demodulator 532 can use various methods to determine the presence of input signal 534 transmitted by a monitor side QAM modulator (not shown). Typically, when verifying the cluster identification and/or verifying that a frame synchronization has been obtained At the time, when the reception of the input signal 534 is reliably confirmed, the coaxial connection signal 531 is confirmed by the camera side QAM demodulator 532.

One method of detecting the presence of input signal 534 includes a method based on an automatic gain control (AGC) loop. AGCs are commonly found in communication receivers (including QAM demodulators) to control signal levels at various levels and points in the receiver. An example is shown in Fig. 27, which shows an AGC loop 540 applied to the front end of the receiver of Fig. 24. In AGC loop 540, the magnitude of a complex signal is determined at 541 and subtracted from a predetermined reference level 543 at 542. The result is filtered by a low pass filter (LPF) 544 to suppress noise and short range variations. The LPF 544 provides an output feed to an accumulator including an adder 545 and a delay element 546. The accumulator output is used as a gain control signal 547 that is fed back to gain block 548 at system input 549. In one example, gain control signal 547 is used as a gain factor or multiplier that determines the gain provided by gain block 548 such that as gain control 547 increases, the gain provided by gain block 548 increases within predetermined limits. When input 549 is off (e.g., the coaxial is off), the output of magnitude block 541 tends to be extremely low. Typically, the coaxially coupled signal 531 can be asserted only when the equivalent value block output is on a predetermined threshold. Moreover, when input 549 is off, gain control signal 547 is typically extremely high. Therefore, the coaxial connection signal 531 can be verified only when the gain control signal is below a predetermined threshold. Even if the loop is found elsewhere in the QAM demodulator 532, the AGC loop 540 can be used to monitor the connection status of the input 549.

Another method of detecting the presence of input signal 534 is based on the equalizer and carrier phase/frequency loop stages shown in Figure 43 (see also Equation 18). In particular, when the QAM modulator stage controller 434 of the QAM demodulator 532 (initially at stage 1) switches to phase 2 based on the result of equation 18, the coaxial connection signal 531 can be verified. The Phase 1 to Phase 2 transition occurs only during the coaxial connection and the QAM demodulator 532 actively receives an upstream signal from the monitor side QAM modulator. Any subsequent disconnection of this coaxial will result in a loss of signal, and an increase in the MSE calculated by Equation 18 will result in a reversal to Phase 1. When the QAM demodulator 532 is in phase 1, the coaxial connection signal 531 can be reset or de-asserted. In some embodiments, camera side QAM demodulator 532 may require phase 3 to be reached prior to confirming coaxial connection signal 531.

Another method for detecting the presence of input signal 534 is based on the demodulator frame synchronization trust counter discussed in connection with FIG. 52B. In particular, the coaxial connection signal 531 can be verified by the camera side QAM demodulator 532 only when the trust counter displays a value greater than a predetermined threshold. In an example, the threshold can be four. Therefore, the coaxial connection signal 531 will be confirmed only when the coaxial connection and the monitor side data machine transmit the SLOC frame to the camera to the camera. If the frame synchronization procedure continues to run freely even if no symbols are received, the disconnection will cause the trust counter to count backwards and eventually fall below 4 and the coaxial connection signal 531 will resolve.

Another method for detecting the presence of input signal 534 is based on a higher layer protocol. Referring again to Figure 51A, HD camera 30 and monitor side host system 38 can communicate using a network protocol. For purposes of discussion, the ubiquitous Internet Protocol (IP) is used as an example of a network protocol. Some modalities of IP are inherently two-way and cause data to go up and down. Both are transmitted. If the cable is disconnected, a network controller or processor in HD camera 30 and/or data machine 32 recognizes that no return IP packet arrives from the monitor side and can notify camera side SLOC modem 32 to stop the passband transmission. In an example, the notification can include transmitting a particular predetermined data packet from the HD camera 30 to the data processor 32 via, for example, the MII interface 536 shown in FIG.

Additional description of certain aspects of the invention

The previous description of the invention is intended to be illustrative rather than limiting. For example, those skilled in the art will appreciate that the present invention may be practiced in various combinations of the functions and capabilities described above, and may include fewer or additional components than those described above. Some additional aspects and features of the present invention are further set forth below, and may be obtained using the functions and components described in more detail above, as will be appreciated by those skilled in the art.

Certain embodiments of the present invention provide systems and methods related to a camera. Some of the specific embodiments include a processor that receives an image signal from an image sensor and generates a plurality of video signals representing the image signal, and an encoder that combines the baseband video signal and the digital video signal The signal is output as one of transmission through a cable. In some such embodiments, the video signals include a baseband video signal and a digital video signal. In some such embodiments, the combined baseband and digital video signals are substantially synchronized. In some such embodiments, the camera is a closed high definition television camera. In some such embodiments, the baseband video signal includes a standard picture quality analog video signal. In some such embodiments, the digital video signal Modulated before being combined with the baseband video signal. In some such embodiments, the digital video signal comprises a compressed video signal. In some such embodiments, the digital video signal is a high quality digital video signal. In some such embodiments, the frame rate of the digital video signal is less than the frame rate of the video signal. In some such embodiments, the modulated digital signal is provided to a video recorder.

Some such embodiments include a decoder configured to demodulate one of the upstream signals received from the cable. In some such embodiments, the demodulated uplink signal includes a control signal. In some such embodiments, the control signals include signals to control the position and orientation of the camera. In some such embodiments, the control signals include signals for controlling the generation of the baseband video signal and the digital video signal by the processor. In some such embodiments, the control signals include a portion for selecting a portion of the image signal for encoding as the baseband video signal. In some such embodiments, the control signals include a portion for selecting a portion of the image signal for encoding as the digital video signal. In some such embodiments, the demodulated uplink signal includes an audio signal for driving an audio output of the camera.

Certain embodiments of the present invention provide methods for transmitting video images. Some such embodiments include frequency division multiplexing processing of a video signal received from a high definition image device to obtain a modulated digital signal by combining the modulated digital signal with a fundamental frequency representative of the video signal Analog signal to generate an output signal and simultaneously output the signal The number is transmitted to a display system and a digital video capture and/or storage device. In some such embodiments, the display system displays an image derived from the fundamental analog representation representing the video signal. In some such embodiments, the digital video storage uses a digital video recorder to record a sequence of high quality video frames captured from the modulated digital signal.

Some such embodiments include compressing the video signal. In some such embodiments, the step of frequency division multiplexing processing the digital video signal includes compressing the video signal prior to modulation. In some such embodiments, transmitting the output signal includes providing the output signal to a coaxial cable. Some such embodiments include demodulating an input signal received from the coaxial cable to obtain a control signal. Some such embodiments include generating the fundamental analog signal by encoding a portion of the video signal in a composite video signal. Some such embodiments include using the control signal to select the portion of the video signal to be encoded in the composite video signal. Some such embodiments include using the control signal to control a position of the camera. In some such embodiments, demodulating the input signal includes extracting an audio signal from the input signal.

Certain embodiments of the present invention provide systems and methods for operating a camera. Some such embodiments include a processor that receives an image signal from an image sensor and generates a plurality of video signals; control logic configured to respond to a control signal received by the camera; and A modulator configured to modulate the digital video signal as a modulated signal. In some such embodiments, the complex video signal includes a baseband video signal and a digital video signal. In some of this In a specific embodiment, each of the plurality of video signals represents at least a portion of a field of view of the camera. In some such embodiments, the control signal controls the content of the base and digital video signals. In some such embodiments, the modulated signal and the baseband video signal are simultaneously transmitted by the camera.

In some such embodiments, the fundamental and digital video signals are substantially synchronized. Some such embodiments include an encoder that combines the baseband video signal and the modulated signal as an output signal for transmission over a cable. In some such embodiments, the control signal is received as a wireless signal. In some such embodiments, the modulated signal is transmitted wirelessly. In some such embodiments, the digital video signal is a high quality digital video signal. In some such embodiments, the digital video signal includes compressed digital video. In some such embodiments, the control signal moves a portion of the field of view represented by one of the video signals.

Certain embodiments of the present invention provide an equalizer for cooperating with a frequency separation and a digital signal carried by a cable and a fundamental analog signal. Some such embodiments include a digital equalizer that removes distortion from the digital signal received at the receiver. Some such embodiments include an analog equalizer that compensates for attenuation of analog signals due to the cable. In some such embodiments, the analog equalizer applies one of a set of fundamental frequency analog filters to compensate for the attenuation. In some such embodiments, based on the difference in attenuation by different frequencies The estimate calculated by the other digital equalizer selects the applied fundamental frequency analog filter.

In some such embodiments, the digital signal and the analog signal are transmitted between a transmitter and a receiver embodied in a camera, and wherein the receiver provides an equalization signal representative of the analog signal to a monitoring Device. In some such embodiments, the cable includes a coaxial cable. In some such embodiments, the distortion increases with the length of the cable. In some such embodiments, the distortion includes multipath distortion. In some such embodiments, the attenuation is estimated from a frequency band having a power spectral density in which the tilt system is approximately linear. In some such embodiments, the tilt is calculated for a complex filter order using a fast Fourier transform. In some such embodiments, the frequency band in the frequency band is selected to allow calculation of the frequency response of one of the digital equalizer filters using the following addition:

Where G [ k ] is a discrete Fourier transform of the time domain convergence equalizer filter stage, and k ₁ corresponds to a particular frequency band of the DFT. In some such embodiments, the digital signal comprises a high quality representation of the video signal captured by a camera, and wherein the analog signal comprises a standard picture quality representation of the video signals.

Certain embodiments of the present invention provide methods for equalizing an analog signal that is also carried by frequency from the analogy The signal is separated from the cable of one of the digital signals. In some such embodiments, the method is performed by a data machine that receives the analog and digital signals and outputs a baseband video signal. Some such embodiments include calculating the tilt in the digital signal. In some such embodiments, the tilt describes the attenuation as a function attributable to the frequency of the cable. Some such embodiments include equalizing the digital signal based on the calculated tilt. Some such embodiments include configuring an analog equalizer by using the computational tilt to select one of a set of fundamental frequency analog filters. Some such embodiments include equalizing the analog signal using the selected fundamental frequency analog filter.

In some such embodiments, the analog signal includes a baseband video signal and the digital signal includes a high quality version of the baseband video signal. In some such embodiments, the cable includes a coaxial cable and wherein the tilt varies with the length of the cable. In some such embodiments, the tilt is derived from multipath distortion. In some such embodiments, calculating the tilt includes estimating an attenuation in a frequency band having a power spectral density in which the tilt system is approximately linear. In some such embodiments, estimating the attenuation includes using a fast Fourier transform for the complex filter stages. In some such embodiments, estimating the attenuation comprises selecting a frequency band in the frequency band. In some such embodiments, the selected frequency band optimizes the efficiency of the step of calculating the tilt.

Certain embodiments of the present invention provide a digital communication system that uses a novel sub-frame structure. Some such embodiments include a whirling byte interleaver that interleaves a data frame, wherein the interleaver is identical Step to a frame structure. Some such embodiments include a random generator configured to generate a randomized data frame from the interleaved data frame. Some such embodiments include a punctured fence code modulator that operates at a selectable rate from a randomized data frame to generate a fence-encoded data frame. Some such embodiments include a QAM mapper. It maps the bits in the fence encoded data frame into groups of modulated symbols to provide a mapping frame. Some such embodiments include a synchronizer that adds a synchronization packet to the mapping frame.

In some such embodiments, the punctured fence code modulator bypasses to obtain an optimized net bit rate based on measuring white noise performance of one of the systems. In some such embodiments, the same synchronization packet is added to each of a subsequent sequence of mapping frames. In some such embodiments, the same synchronization packet is added to each mapping frame. In some such embodiments, one portion of the synchronization packet contains 127 symbols. In some such embodiments, one portion of the synchronization packet contains different binary sequences for the real and imaginary parts of the modulation symbols. In some such embodiments, one portion of the synchronization packet includes an identical binary sequence for the real and imaginary parts of the modulation symbols. In some such embodiments, the synchronization packet includes data indicative of a transmission modality of the mapping frame. In some such embodiments, the indication of the transmission modality includes a selected QAM cluster and a selected fence rate. In some such embodiments, the system generates a constant integer Reed-Solomon packet for each frame of data regardless of the transmission modality. In some such embodiments, regardless of the transmission modality, The system generates a variable integer modulation symbol for each frame of the data. In some such embodiments, the system generates an integer puncturing mode loop for each frame of data regardless of the transmission modality.

Certain embodiments of the present invention provide a framing method for a variable net bit rate digital communication system. Some such embodiments include providing a set of different quadrature amplitude modulation (QAM) clusters. Some such embodiments include frames for generating data packets using a combination of punctured fence codes, each combination corresponding to a correlated modality. Some such embodiments include providing a frame with a variable integer of one of the QAM symbols. In some such embodiments, the number of QAM symbols corresponds to a selected modality. In some such embodiments, the associated number of bytes and each frame Reed-Solomon packet is constant. In some such embodiments, regardless of the associated modality, the use of a punctured fence combination to generate a data packet includes generating an integer puncturing pattern loop for each frame of data. In some such embodiments, the number of data bits for each QAM symbol of one or more modalities is a fraction. In some such embodiments, the number of one of the fence encoder puncturing mode loops for each frame is an integer for all modalities.

Certain embodiments of the present invention provide a system for correcting phase offset. Some such embodiments include a phase offset corrector that receives an equalized signal representative of a quadrature amplitude modulation signal and derives a phase correction signal from the equalized signal. Some such embodiments include a two-bit quasi-splitter that splits the equalized signal to obtain real and imaginary sequences. Some such embodiments include a frame synchronizer that uses a stored message A corresponding portion of the block sync pseudo-random sequence performs a correlation of the real and imaginary sequences. Some such embodiments include a phase correction signal provided by the frame synchronizer to the phase offset corrector. In some such embodiments, the phase correction signal is based on the maximum real and imaginary values of the correlation. In some such embodiments, the frame synchronizer performs continuous cross-correlation on the incoming split quadrature amplitude modulation symbols.

In some such embodiments, the continuous cross-correlation relationship is performed separately for the real and imaginary sequences using a stored copy of the binary frame sync pseudo-random noise sequence. In some such embodiments, the quadrature amplitude modulation signal is modulated using a punctured fence code. In some such embodiments, quadrature phase shift keying modulation is used to modulate the quadrature amplitude modulation signal. In some such embodiments, the quadrature amplitude modulation (QAM) signal is modulated using 16-QAM. In some such embodiments, the quadrature amplitude modulated (QAM) signal is modulated using 64-QAM. In some such embodiments, the frame sync symbols of the quadrature amplitude modulation signal have the same sign and the associated maximum true and imaginary symbols indicate the phase rotation in the equalized signal. In some such embodiments, the phase correction signal provided by the frame synchronizer includes the associated maximum real and imaginary sign. In some such embodiments, the phase offset corrector derives the phase correction signal by indexing a lookup table with the associated maximum real and imaginary symbol to determine a phase correction value.

Certain embodiments of the present invention provide for correcting a carrier phase offset in a quadrature amplitude modulation signal in a receiver law. Some such embodiments include equalizing the signal. Some such embodiments include segmenting the equalized signals to obtain real and imaginary sequences from the equalized signals. Some such embodiments include identifying a frame synchronization sequence in the real and imaginary sequences. In some such embodiments, identifying the frame synchronization sequence includes correlating a stored pseudo-random sequence with the real and imaginary sequences. In some such embodiments, identifying the frame synchronization sequence includes determining from a correlation of the maximum correlation value of the true and imaginary sequences to determine one of the frames. Some such embodiments include correcting one of the phased errors in the equalized signal based on the maximum correlation values.

In some such embodiments, the correlating step includes performing a continuous cross-correlation on a series of split quadrature amplitude modulation symbols with a stored copy of a binary frame sync pseudo-random noise sequence. In some such embodiments, the correlating step includes separately performing a continuous cross-correlation on the frame synchronization sequence of the stored replicas using the real and imaginary sequences. In some such embodiments, the frame sync symbols of the frame synchronization sequence have the same symbols. In some such embodiments, correcting a phase error includes determining a phase rotation in the equalized signal based on the symbols of the maximum correlation values. In some such embodiments, correcting a phase error in the equalized signal includes indexing a lookup table with the symbols of the real and imaginary maximum correlation values.

Certain embodiments of the present invention provide methods for correcting carrier phase offset in a quadrature amplitude modulated signal. In some such embodiments, the method can be implemented in a system including one or more processors configured to execute instructions. Some of these specific embodiment packages An instruction configured to equalize the signal is executed on one or more processors. Some such embodiments include instructions executed on one or more processors configured to split the equalized signal to obtain a real and a virtual sequence from the equalized signal. Some such embodiments include instructions executed on one or more processors to configure a frame synchronization sequence in the real and imaginary sequences. In some such embodiments, identifying the frame synchronization sequence includes separately performing a continuous cross-correlation on the frame synchronization sequence of the stored replicas using the real and imaginary sequences. In some such embodiments, identifying the frame synchronization sequence packet begins with associating one of the maximum correlation values of the real and imaginary sequences. Some such embodiments include instructions executed on one or more processors to configure a phase error in the equalized signal based on the maximum correlation values. In some such embodiments, the frame sync symbols of the frame sync sequence have the same symbols. In some such embodiments, correcting a phase error includes determining a phase rotation in the equalized signal based on a sign of the maximum correlation values.

Certain embodiments of the present invention provide methods for identifying a cluster of one of the symbols. In some such embodiments, the method is performed by one or a plurality of processors of a multi-modal quadrature amplitude modulation communication system. Some such embodiments include instructions that cause one or more processors to describe a power distribution in a signal. In some such embodiments, the power distribution statistically tracks the occurrence of detected power levels in the signal. Some such embodiments include performing instructions that cause one or more processors to determine one of the power levels or a majority of peaks within the power distribution. make. Some such embodiments include executing instructions that cause one or more processors to determine the cluster based on the distribution of the spikes.

In some such embodiments, one or more processors also determine the cluster based on the expansion of one or more spikes. In some such embodiments, the signal is equalized signal and one or more of the processors determine the cluster by examining the complex segments in a histogram of the power distribution. In some such embodiments, each of the segments corresponds to a range of power levels that are associated with one but not all of the complex cluster candidates. In some such embodiments, the complex cluster candidate includes a quadrature phase shift keying cluster and a quadrature amplitude modulation (QAM) cluster. In some such embodiments, the complex cluster candidate includes a 16-QAM and a 64-QAM cluster. In some such embodiments, the complex cluster candidate includes a 256-QAM cluster.

Some such embodiments include executing instructions that cause one or more processors to establish a cluster identification reliability by performing steps for each of a series of cluster decisions. In some such embodiments, when a subsequent decision confirms the identification of the cluster, the steps include incrementing a counter. In some such embodiments, when a subsequent decision identifies a different cluster, the steps include decrementing a counter. In some such embodiments, the steps include providing one of the reliability measurements based on the value of the counter. In some such embodiments, the cluster is identified when the counter exceeds a threshold. In some such embodiments, a counter provides for each of the plurality of cluster candidates and wherein the cluster is recognized when its corresponding counter exceeds a threshold do not. In some such embodiments, a spike in power level occurs corresponding to a corner symbol of the cluster. In some such embodiments, the cluster is identified prior to the signal being equalized.

Certain embodiments of the present invention provide a method of identifying a cluster of one of the symbols in a multi-modal quadrature amplitude modulation communication system. In some such embodiments, the methods are performed by a processor in one of the data systems of the communication system. Some such embodiments include instructions for causing the processor to retrieve modal information from the frame of the data in response to the detection of the beginning of the frame of data received by the data machine. Some such embodiments include executing instructions that cause the processor to determine a current cluster by selecting a code from one of the possible possible clusters that most closely matches one of the modal bits. Some such embodiments include executing an instruction to cause the processor to add a trust metric to one of the previously identified clusters if the current cluster matches a previously determined cluster. Some such embodiments include performing an instruction to cause the processor to reduce the trust meter if the current cluster is different from the previously identified cluster and to record the current cluster as the previously identified cluster. Some such embodiments include the steps of repeatedly causing the processor to retrieve modal information, selecting a current cluster and adjusting the trusted metering for subsequent frames of the data until the trusted metering exceeds a predetermined threshold. In some such embodiments, the cluster is identified when the confidence measure exceeds the predetermined threshold.

In some such embodiments, selecting a cluster code includes causing the processor to perform cross-correlation for each of the plurality of possible cluster codes having corresponding code bits. In some such embodiments, the group The collection is identified in an unequalized signal of the frame carrying the data and the subsequent frame of the data. In some such embodiments, the cluster is identified and the processor recovers a carrier from the signal. Some such embodiments include executing instructions that cause the processor to use a constant modulus algorithm (CMA) to calculate an error signal to converge the equalizer filter stage to allow for equalization of the signal. In some such embodiments, the error signal is calculated using a scaled CMA parameter to improve equalization performance. In some such embodiments, performing equalization of the signal includes analyzing the histograms of the power of the equalized signal. In some such embodiments, analyzing the histograms includes using a probability mass function. In some such embodiments, performing equalization of the signal includes executing an instruction that causes the processor to calculate the power associated with the complex symbols in the equalized signal. In some such embodiments, performing equalization of the signal includes executing instructions that cause the processor to identify the corner symbols of the cluster by using a threshold power level. In some such embodiments, the threshold power level indicates the identification of the cluster.

Certain embodiments of the present invention provide a system for transmitting a video signal, the system including a camera side data machine configured to receive two signals from a video camera, each signal representing an image captured by the camera The sequence is further configured to transmit one of the two signals as a composite baseband video signal and to modulate and transmit the other signal as a passband video signal that does not overlap the baseband signal. In some such embodiments, the camera-side data unit includes a mixer that combines the baseband and passband video signals to provide a transmission signal. In some of these specific implementations In one example, the camera side data machine includes a duplexer configured to transmit the transmission signal through a transmission line and to receive a passband signal from the transmission line. In some such embodiments, the camera-side data machine includes a detector that monitors the camera-side data machine and generates a consistent energy signal when the received passband signal is recognized. In some such embodiments, the enable signal controls transmission of at least one of the baseband video signal and the passband video signal.

In some such embodiments, the passband video signal is transmitted only when the enable signal is generated. In some such embodiments, the received passband signal is quadrature amplitude modulated. In some such embodiments, the detector monitors an estimate of the mean square error in a quadrature amplitude modulation demodulator, and wherein the enable signal is generated when the estimate exceeds a threshold. In some such embodiments, the detector monitors a cluster detector. In some such embodiments, the enable signal is generated based on a measurement of the reliability provided by the cluster detector. In some such embodiments, the reliability measure is based on a frame synchronization sequence. In some such embodiments, the detector monitors an estimate of the mean square error in the equalizer. In some such embodiments, the enable signal is generated when the estimate exceeds a threshold. In some such embodiments, the detector monitors one of the gain factors of an automatic gain control module of the camera-side data processor. In some such embodiments, the enable signal is generated when the gain factor has a value less than a threshold. In some such embodiments, the detector monitors a magnitude of the received passband signal. In some such embodiments, when The enable signal is generated when the magnitude has a value above one threshold. In some such embodiments, the received passband signal includes data encoded in accordance with an internet protocol.

Certain embodiments of the present invention provide methods for controlling signaling in a security system. Some such embodiments include the determination of the presence of an uplink QAM signal in a composite signal transmitted on a coaxial cable at an upstream modem. Some such embodiments include causing the uplink data unit to transmit a composite baseband video signal and a passband video signal on the coaxial cable when it is determined that the uplink QAM signal is present. In some such embodiments, the composite baseband video signal and the passband video signal are represented in parallel by an image sequence captured by a video camera. Some such embodiments include causing the uplink data unit to transmit the composite baseband video signal on the coaxial cable and prevent transmission of the passband video signal when it is determined that the uplink QAM signal is not present.

In some such embodiments, when a gain value in an automatic gain control signal exceeds a threshold, the uplink QAM signal is determined to be present. In some such embodiments, when one of the uplink QAM signal magnitudes is less than a threshold, the uplink QAM signal is determined to be present. In some such embodiments, when an estimate of the mean square error in the equalizer exceeds a threshold, the uplink QAM signal is determined to be absent. In some such embodiments, when an internet protocol data packet is identified in the uplink QAM signal, it is determined that the uplink QAM signal does not exist.

Certain embodiments of the present invention provide an automatic reconfiguration system for transmitting video signals. Some such embodiments include an upstream data machine configured to receive two signals from a video camera. In some such embodiments, each signal represents a sequence of images captured by the camera. In some such embodiments, the uplink data machine is configured to transmit one of the two signals as a composite baseband video signal and to modulate and transmit the other signal as a passband video signal that does not overlap the baseband. signal. Some such embodiments include a downlink data machine configured to receive a composite baseband video signal and a passband video signal from the uplink data machine, and further configured to transmit an uplink passband signal to the uplink data machine. In some such embodiments, the uplink data machine stops transmission of at least one of the two signals when one of the uplink passband signals is detected to be degraded.

While the invention has been described with respect to the specific embodiments of the present invention, it will be understood that various modifications and changes of the embodiments may be made without departing from the scope of the invention. For example, the system has been described to provide compressed digital HD video and a baseband analog video signal in parallel. Other embodiments of the present invention provide both standard image quality and analog delivery. Other embodiments provide full frame rate digital HD video along with the baseband analog video. Accordingly, the specification and drawings are to be regarded as illustrative rather

30‧‧‧ camera

31‧‧‧Data Machine/SLOC-T

32‧‧‧DVR/Data Machine

33‧‧‧Coaxial cable

34‧‧‧SD display

35‧‧‧SLOC-R data machine

36‧‧‧Information

330‧‧‧ analog CVBS signal / auxiliary camera output

332‧‧‧High quality signal/passband downlink IP signal

Claims (19)

A method comprising the steps of: receiving, at a first data machine, one or more video signals derived from an imaging device; modulating at least one of the one or more video signals to obtain a modulated digital signal The modulated digital signal represents a video image generated by the imaging device; an analog video signal is transmitted in a fundamental frequency of a coaxial cable, the analog video signal representing the video image; and the video signal is transmitted simultaneously with the analog video signal The modulated digital signal is transmitted in a frequency band separated from the fundamental frequency of the coaxial cable. The method of claim 1, wherein the analog video signal and the modulated digital signal are isochronous. The method of claim 1, further comprising the step of compressing a digital signal received from the imaging device to obtain a compressed digital signal, wherein the step of modulating the at least one of the one or more video signals Including: modulating the compressed digital signal. The method of claim 3, further comprising the following steps Step: Formatting the digital signal received from the imaging device to obtain one or more high quality digital video signals, at least one high quality digital video signal conforming to a broadcast standard. The method of claim 4, further comprising the step of deriving the analog video signal from the one or more high quality digital video signals. The method of claim 3, further comprising the step of deriving the analog video signal from the digital signal received from the imaging device. The method of claim 3, wherein the digital signal and the compressed digital signal have different frame rates. An apparatus comprising: a data machine configured to couple the device to a coaxial cable; and a processing system coupled to the data machine, and the The system is configured to: receive one or more video signals from an imaging device; cause the data machine to transmit an analog video signal in a fundamental frequency of the coaxial cable; and cause the data machine to be in the coaxial cable Transmitting, by a frequency band of the coaxial cable, a modulated digital video signal, wherein the analog video signal is transmitted simultaneously with the modulated digital video signal, and represents a video image generated by the imaging device, and The modulated digital video signal is transmitted to one or more of a digital video recorder, a video server, and a digital display. A system comprising: a first data machine configured to receive one or more video signals derived from an imaging device, the first data machine being further configured to transmit in a fundamental frequency of a coaxial cable a class of modulated video signals transmitted in a frequency band separated from the fundamental frequency of the coaxial cable in the coaxial cable, wherein the analog video signal and the modulated digital video signal are generated by the imaging device And a second data machine configured to receive the modulated digital video signal from the coaxial cable and the second data machine demodulates the modulated digital video signal to obtain a high quality video signal Signal, where the high quality view The signal is transmitted by the second data machine to one or more of a digital video recorder, a video server, and a digital display. The system of claim 9, further comprising: a filter that separates the analog video signal from the modulated digital video signal, wherein the analog video signal is provided to a standard picture quality monitor. The system of claim 9, wherein the first data machine modulates a compressed video signal to obtain the modulated digital video signal, the compressed video signal being derived from the imaging device. The system of claim 9, wherein at least one of the one or more video signals derived from the imaging device is compressed by the first data machine. The system of claim 9, wherein the second data machine modulates an upstream control signal and transmits the modulation control signal to a channel of the coaxial cable, wherein the modulation control signal is The first data machine receives and demodulates, and wherein the uplink control signal controls content of one or more of the analog video signal and the modulated digital video signal. The system of claim 13, wherein the uplink control signal determines that a portion of a video image carried by the one or more of the analog video signal and the modulated digital video signal is captured by the imaging device. The system of claim 14, wherein the modulated digital video signal carries a panoramic field of view of an area, and wherein the analog video signal carries a portion of the panoramic view. The system of claim 15, wherein the uplink control signal determines the panoramic view of the panoramic video signal carried by the analog video signal by controlling one or more of a zoom and a pan section. The system of claim 14, wherein the modulated digital video signal carries a fisheye field of view at a location monitored by a camera, and wherein the analog video signal carries a portion of the fisheye field of view. The system of claim 17, wherein the uplink control signal causes the portion of the fisheye field of view to move virtually. The system of claim 17, wherein the uplink control signal causes the fisheye field of view to change by initiating a physical movement of the camera.