TW201616931A - Circuit structure and manufacturing method for circuit structure - Google Patents

Abstract

A manufacturing method for a circuit structure includes the following steps. A substrate including a first metal layer, a second metal layer and an etching-stop layer is provided. The etching-stop layer is disposed between the first and the second metal layers. A thickness of the second metal layer is greater than that of the first metal layer. A first patterning process is performed on the second metal layer by taking the etching-stop layer as a shield to form a second patterned metal layer including a plurality of metal blocks. A second patterning process is performed on the etching-stop layer to remove part of the etching-stop layer exposed by the second patterned metal layer. A first dielectric layer is formed on the second patterned metal layer. The first metal layer is patterned to form a first patterned metal layer including a plurality of circuit patterns corresponding to the metal blocks respectively.

Description

Line structure and circuit structure manufacturing method

The present invention relates to a method for fabricating a line structure and a line structure, and more particularly to a method for fabricating a line structure and a line structure applied to a circuit board.

With the advancement of technology, electronic products have become widespread in modern society. In the necessary parts of these electronic products, in addition to electronic components such as chips and passive components, circuit boards carrying and arranging these chips and passive components are also indispensable important parts.

Conventional wiring boards can be composed, for example, of a wiring layer, a ground layer, a power supply layer, and a dielectric layer. The electronic component can be disposed on the circuit layer and electrically connected thereto. In addition, the power supply layer can externally connect a power supply for supplying power to the circuit board to drive electronic components mounted on the circuit board, and the input/output lines of the electronic components can be transmitted through the circuit layer. The ground layer can be disposed between the circuit layer and the power layer. In addition, the dielectric layers are respectively disposed between the circuit layer, the ground layer, and the power supply layer for insulation.

In the heat dissipation problem, the circuit board used to transfer the waste heat generated by the electronic components in the circuit layer, so that the electronic components are kept at the normal working temperature. However, since the waste heat generated by the electronic components is constantly increasing, the general circuit layer The thickness has been unable to meet the high electrical performance and high heat dissipation efficiency of the current circuit board. In order to meet the processing demands of today's high current and high heat dissipation efficiency, it is necessary to increase the thickness of the circuit layer, thus increasing the difficulty of manufacturing the circuit and the soldering prevention, thereby reducing the yield of production and improving the production. the cost of.

The invention provides a method for manufacturing a line structure and a line structure, which has a simple process and a high yield.

A method of fabricating a wiring structure of the present invention includes the following steps. First, a substrate is provided. The substrate includes a first metal layer, a second metal layer, and an etch stop layer. The etch stop layer is disposed between the first metal layer and the second metal layer, and a thickness of the second metal layer is greater than a thickness of the first metal layer. Next, a patterned photoresist layer is formed on the second metal layer. Then, the patterned photoresist layer is used as an etch mask, and the etch stop layer is used as an etch barrier, and the second metal layer is subjected to a first patterning process to form a second patterned metal layer, wherein the second pattern The metal layer includes a plurality of metal bumps. Next, the etch stop layer is subjected to a second patterning process by using the patterned photoresist layer as an etch mask to remove a portion of the etch stop layer exposed by the second patterned metal layer. Next, the patterned photoresist layer is removed. Thereafter, a first dielectric layer is formed on the second patterned metal layer. The first dielectric layer covers the second pattern Metal layer. Next, the first metal layer is patterned to form a first patterned metal layer. The first patterned metal layer includes a plurality of line patterns respectively corresponding to the metal bumps.

A circuit structure of the present invention includes a first metal layer, a first dielectric layer, a plurality of metal bumps, a second dielectric layer, and a plurality of vias. The first dielectric layer is disposed on the first metal layer. The metal bumps are disposed on a surface of the first dielectric layer, wherein a thickness of each of the metal bumps is substantially greater than or equal to 100 micrometers. The second dielectric layer is disposed on the surface of the first dielectric layer and covers the metal bumps. The via holes are respectively connected between the metal bumps and the first metal layer.

A method of fabricating a wiring structure of the present invention includes the following steps. First, a substrate is provided. The substrate includes a core layer, a two release film, and two first metal layers. The release films are respectively disposed on opposite surfaces of the core layer. The first metal layers are respectively disposed on the release film. Then, two first dielectric layers are respectively formed on the two first metal layers. Then, two patterned metal layers are respectively formed on the two first dielectric layers, wherein each of the patterned metal layers includes a plurality of metal bumps, and a thickness of each of the metal bumps is substantially greater than or equal to 100 micrometers. Next, two second dielectric layers are formed on the two patterned metal layers, respectively. Two second dielectric layers respectively cover the two patterned metal layers. The two release films are separated from the corresponding first metal layers to form separate two-wire structures.

Based on the above, the present invention utilizes a three-layer composite metal foil having a first metal layer, a second metal layer, and an etch stop layer as a substrate of a wiring structure, the first metal layer having a thin thickness for forming a plurality of wiring patterns And the second metal layer is thicker to form a plurality of metal bumps as a power layer or a ground layer of the line pattern, In order to achieve the function of carrying high current and heat dissipation. The etch stop layer in the middle can serve as an etch barrier for the patterning process of forming the metal bumps to prevent damage to the first metal layer when etching the second metal layer. Since the substrate can be used to fabricate a double-sided wiring layer, the number of build-ups is reduced, and the manufacturing process is simplified, thereby improving the yield of the process.

In addition, the present invention can also utilize a composite substrate formed by laminating two release films and two first metal layers on opposite surfaces of the core layer, and simultaneously performing the circuit on both sides of the substrate in a symmetrical manner. The stacking process of the structure is to form a thick metal bump and electrically connected to the first metal layer as a power layer or a ground layer of the first metal layer to achieve high current carrying and heat dissipation. Since the stacking is formed on the substrate in a symmetrical manner, the number of times of layering can be reduced, and after the board is removed, two separate line structures can be obtained at the same time, which can effectively save the processing time and improve the production efficiency.

The above described features and advantages of the invention will be apparent from the following description.

100, 200‧‧‧ line structure

110, 210‧‧‧ substrate

112, 216‧‧‧ first metal layer

114, 242‧‧‧ second metal layer

114a‧‧‧Second patterned metal layer

114b, 232‧‧‧metal bumps

116‧‧‧etch stop layer

120‧‧‧ photoresist layer

122‧‧‧ patterned photoresist layer

122a‧‧‧ openings

130, 220‧‧‧ first dielectric layer

132‧‧‧ Third metal layer

132a‧‧‧ Third patterned metal layer

140, 240‧‧‧second dielectric layer

142‧‧‧Fourth metal layer

212‧‧‧ core layer

214‧‧‧ release film

216a‧‧‧Smooth surface

216b‧‧‧Rough surface

230‧‧‧ patterned metal layer

250‧‧‧vias

D1‧‧‧ thickness

1A-1H are schematic cross-sectional views showing a process of fabricating a circuit structure in accordance with an embodiment of the invention.

2A-2F are schematic cross-sectional views showing a process of fabricating a circuit structure in accordance with an embodiment of the invention.

1A-1H are schematic cross-sectional views showing a process of fabricating a circuit structure in accordance with an embodiment of the invention. The manufacturing method of the line structure of this embodiment includes the following steps: First, referring to FIG. 1A, a substrate 110 is provided. The substrate 110 includes a first metal layer 112, a second metal layer 114, and an etch stop layer 116. The etch stop layer 116 is disposed between the first metal layer 112 and the second metal layer 114, and as shown in FIG. 1A, the thickness of the second metal layer 114 is greater than the thickness of the first metal layer 112. In the present embodiment, the thickness of the first metal layer 112 may be, for example, between 18 micrometers (μm) and 70 micrometers, and the thickness of the second metal layer 114 may be between 65 micrometers and 500 micrometers. Preferably, the thickness of the second metal layer 114 can be substantially greater than or equal to 100 microns. Additionally, the thickness of the etch stop layer 116 can be, for example, between 0.8 microns and 1.2 microns. Specifically, the first metal layer 112 may be an electrolytic deposit (ED) copper foil formed by a sputtering or electroplating process, and the second metal layer 114 may be a laminated pressure formed by a heating and a rolling process. (Rolled and Annealed, RA) copper foil. The first metal layer 112 and the second metal layer 114 collectively coat the etch stop layer 116 to form the substrate 110.

Next, referring to FIG. 1B and FIG. 1C, a photoresist layer 120 is formed on the first metal layer 112 and the second metal layer 114, so that the photoresist layer 120 covers the first metal layer 112 and the second metal layer 114, respectively. The outer surface. Thereafter, the photoresist layer 120 overlying the second metal layer 114 is patterned to form a patterned photoresist layer 122 on the second metal layer 114. The patterned photoresist layer 122 has a plurality of openings 122a. Then, the patterned photoresist layer 122 is used as an etch mask, and the etch stop layer 116 is used as an etch barrier to perform a first patterning process on the second metal layer 114 as shown in FIG. 1B to form a pattern as shown in FIG. 1C. A second patterned metal layer 114a is shown, wherein the second patterned metal layer 114a includes a plurality of metal bumps 114b. In this embodiment, since the thickness of the second patterned metal layer 114a may be substantially greater than or equal to 100 micrometers, the thickness of each of the metal bumps 114b may naturally be greater than or equal to 100 micrometers.

In this embodiment, the foregoing first patterning process may be an alkaline etching process, that is, the etching liquid used in the first patterning process is an alkaline etching liquid, and the etching stop layer 116 may be An anti-alkaline etch layer, that is, the etch stop layer 116 is not eroded by the alkaline etchant during the first patterning process, thereby providing an etch barrier to the first metal layer 112 for the first patterning process The termination of the etch stop layer 116 can be terminated without continuing to etch the first metal layer 112. In the present embodiment, the material of the etch stop layer 116 includes a group of tin, lead, chromium, nickel, indium, zinc, tungsten, molybdenum or any combination thereof. Of course, the invention is not limited thereto.

Next, as shown in FIG. 1D, the etch stop layer 116 is subjected to a second patterning process by using the patterned photoresist layer 122 as an etch mask to remove portions of the etched portion of the second patterned metal layer 114a. The layer 116 is terminated. In this embodiment, the second patterning process may be an acid etching process, that is, the etching liquid used in the second patterning process is an acidic etching solution to expose the second patterned metal layer 114a. A portion of the etch stop layer 116 is etched. In addition, the second patterning process may also be a process such as dilute etching, flash etching, or exposure development. For example, the dilute etch can etch the etch stop layer 116 using, for example, a diluted etchant to reduce damage to the first metal layer 112, while the fast etch can utilize the difference in etch rate between electroless plating and electroplating. An effect of differential etching is formed to remove the etch stop layer 116 formed, for example, by electroless plating. Of course, those skilled in the art should understand that the present embodiment is only for illustration, and the present invention is not limited thereto.

Next, referring to FIG. 1D to FIG. 1F simultaneously, the patterned photoresist layer 122 and the photoresist layer 120 as shown in FIG. 1D are removed to form the structure of FIG. 1E. Thereafter, a first dielectric layer 130 is further formed on the second patterned metal layer 114a, wherein the first dielectric layer 130 covers the second patterned metal layer 114a. In this embodiment, the outer surface of the first dielectric layer 130 has a third metal layer 132 as shown in FIG. 1F, and the method of forming the first dielectric layer 130 on the second patterned metal layer 114a may include pressing. The first dielectric layer 130 and the third metal layer 132 are combined on the second patterned metal layer 114a. In addition, in this embodiment, the browning or roughening process of the structure of FIG. 1E is further selectively performed before the first dielectric layer 130 is pressed to increase the second patterned metal layer 114a and the first The bonding force between a dielectric layer 130.

Next, referring to FIG. 1F and FIG. 1G, the first metal layer 112 shown in FIG. 1F is patterned to form a first patterned metal layer 112a as shown in FIG. 1G, wherein the first pattern The metallization layer 112a includes a plurality of wiring patterns 112b corresponding to the metal bumps 114b, respectively. Moreover, the third metal layer 132 as shown in FIG. 1F is patterned to form a third patterned metal layer 132a as shown in FIG. 1G. In this way, the fabrication of the line structure 100 can be initially completed.

Thereafter, as shown in FIG. 1H, two second dielectric layers 140 are formed on the first patterned metal layer 112a and the third patterned metal layer 132a, respectively. In this embodiment, the outer surface of each of the second dielectric layers 140 may have a fourth metal layer 142 as shown in FIG. 1H. Of course, the present embodiment is only used for exemplification, and any one of ordinary skill in the art can delete or continue stacking the required stack according to the product design. The present invention does not limit the number of layers of the line structure. .

As such, the present embodiment utilizes a three-layer composite metal foil having a first metal layer 112, a second metal layer 114, and an etch stop layer 116 as a substrate of a wiring structure, wherein the first metal layer 112 is thin and permeable. The patterning process forms a plurality of line patterns 112b, and the second metal layer 114 has a thicker thickness, and a plurality of metal bumps 114b can be formed through the patterning process as a power layer or a ground layer of the line pattern 112b to achieve the load. High current and heat dissipation. Moreover, the composite metal foil can be used to fabricate a double-sided wiring layer, thereby reducing the number of times of layering, and the process is relatively simple, thereby improving the yield of the process.

2A-2F are schematic cross-sectional views showing a process of fabricating a circuit structure in accordance with an embodiment of the invention. This embodiment further provides a method for fabricating another circuit structure, which includes the following steps: First, referring to FIG. 2A, a substrate 210 is provided. The substrate 210 includes a core layer 212, two release films 214, and two first metal layers 216. The release films 214 are respectively disposed on opposite surfaces of the core layer 212 as shown in FIG. 2A, and the first metal layers 216 are respectively disposed on the release film 214. In the present embodiment, the first metal layer 216 includes a smooth surface 216a and a rough surface 216b with respect to the smooth surface 216a, and the release film 214 is disposed on Smooth on surface 216a. That is, each release film 214 is disposed between the core layer 212 and the corresponding first metal layer 216. In general, the release film 214 is a film having a surface separation which does not have a tackiness or only a slight viscosity after contact with a specific material under specific conditions.

Next, referring to FIG. 2B, two first dielectric layers 220 are formed on the two first metal layers 216, respectively. In this embodiment, the first dielectric layer 220 is disposed on the rough surface 216b of the first metal layer 216, and the material of the first dielectric layer 220 includes ceramic or semi-curable resin (prepreg, PP) and the like. Good material. Then, two patterned metal layers 230 are respectively formed on the two first dielectric layers 220 as shown in FIG. 2C, wherein each patterned metal layer 230 includes a plurality of metal bumps 232 as shown in FIG. 2C. In the present embodiment, the thickness of the first metal layer 216 may be substantially 5 microns to 70 microns. A thickness D1 of each of the metal bumps 232 is substantially greater than or equal to 100 microns.

Next, referring to FIG. 2D, two second dielectric layers 240 are formed on the two patterned metal layers 230, respectively. Two second dielectric layers 240 respectively cover the two patterned metal layers 230. In this embodiment, the material of the second dielectric layer 240 includes a material having better thermal conductivity such as ceramic or semi-cured resin, and the outer surface of each of the second dielectric layers 240 may have a second metal layer 242 to form The method of the second dielectric layer 240 on the patterned metal layer 230 includes pressing the second dielectric layer 240 and the second metal layer 242 onto the patterned metal layer 230.

then. Referring to FIG. 2E, the release film 214 is separately separated from the corresponding first metal layer 216 by the easy peeling property of the release film 214 to expose The smooth surface 216a of the first metal layer 216 forms a separate two-wire structure as shown in Figure 2E. Then, as shown in FIG. 2F , a plurality of via holes 250 are formed on each of the first dielectric layers 220 , wherein the via holes 250 are respectively connected between the metal bumps 232 and the corresponding first metal layer 216 to The metal bumps 232 and the corresponding first metal layer 216 are electrically connected. Thus, the fabrication of the line structure 200 is initially completed. Of course, the present embodiment is only used for exemplification, and any one of ordinary skill in the art can delete or continue stacking the required stack according to the product design. The present invention does not limit the number of layers of the line structure. .

The circuit structure 200 according to the above manufacturing method can be as shown in FIG. 2F, and includes a first metal layer 216, a first dielectric layer 220, a plurality of metal bumps 232, a second dielectric layer 240, and more. One via hole 250. The first dielectric layer 220 is disposed on the first metal layer 216, wherein the first metal layer 216 includes a smooth surface 216a and a rough surface 216b opposite to the smooth surface 216a, and the first dielectric layer 220 is disposed on the first dielectric layer 220. On the rough surface 216b. The metal bumps 232 are disposed on the surface of the first dielectric layer 220, wherein a thickness D1 of each of the metal bumps 232 is substantially greater than or equal to 100 micrometers. The second dielectric layer 240 is disposed on the surface of the first dielectric layer 220 and covers the metal bumps 232 . The via holes 250 are respectively connected between the metal bumps 232 and the first metal layer 250. The material of the first dielectric layer 220 and the second dielectric layer 240 includes a material having better thermal conductivity such as ceramic or semi-cured resin.

As such, the circuit structure 200 utilizes a composite substrate 210 having a core layer 212, a two release film 214, and two first metal layers 216 to simultaneously perform the line structure 200 on both sides of the substrate 210 in a symmetrical manner. Stacking process, therefore, After the board is removed, two separate line structures 200 can be obtained at the same time, which saves process time and improves production efficiency. Moreover, the line structure 200 further utilizes a metal bump 232 having a thickness greater than or equal to 100 microns as a power layer or a ground layer of the first metal layer 216 to carry a high current and dissipate heat.

In summary, the present invention utilizes a three-layer composite metal foil having a first metal layer, a second metal layer, and an etch stop layer as a substrate of a wiring structure, wherein the first metal layer has a thin thickness and is permeable to patterning. a plurality of circuit patterns are formed by the process, and the second metal layer has a thick thickness, and a plurality of metal bumps can be formed through the patterning process as a power layer or a ground layer of the circuit pattern to achieve high current and heat dissipation. function. The etch stop layer in the middle can serve as an etch barrier for the patterning process to prevent damage to the first metal layer when etching the second metal layer. In this way, the substrate can be used to fabricate a double-sided wiring layer, thereby reducing the number of layers, and the process is relatively simple, thereby improving the yield of the process.

In addition, the present invention can also utilize a composite substrate having a core layer, a two release film, and two first metal layers to simultaneously perform a stacking process of the line structure on both sides of the substrate in a symmetrical manner. A thick metal bump is formed and electrically connected to the first metal layer to serve as a power layer or a ground layer of the first metal layer to carry a high current and dissipate heat. Since the stacking is formed on the substrate in a symmetrical manner, the number of times of layering can be reduced, and after the board is removed, two separate line structures can be obtained at the same time, which effectively saves process time and improves production efficiency.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art without departing from the invention. In the spirit and scope, the scope of protection of the present invention is subject to the definition of the appended patent application.

112‧‧‧First metal layer

114a‧‧‧Second patterned metal layer

114b‧‧‧Metal bumps

116‧‧‧etch stop layer

120‧‧‧ photoresist layer

122‧‧‧ patterned photoresist layer

122a‧‧‧ openings

Claims (18)

A method for fabricating a circuit structure, comprising: providing a substrate, the substrate comprising a first metal layer, a second metal layer, and an etch stop layer, the etch stop layer being disposed on the first metal layer and the second Between the metal layers, and a thickness of the second metal layer is greater than a thickness of the first metal layer; forming a patterned photoresist layer on the second metal layer; using the patterned photoresist layer as an etching mask And using the etch stop layer as an etch barrier, performing a first patterning process on the second metal layer to form a second patterned metal layer, the second patterned metal layer comprising a plurality of metal bumps; The patterned photoresist layer is an etching mask to perform a second patterning process on the etch stop layer to remove a portion of the etch stop layer exposed by the second patterned metal layer; removing the patterned light a resist layer; forming a first dielectric layer on the second patterned metal layer; and patterning the first metal layer to form a first patterned metal layer, the first patterned metal layer comprising a plurality of lines Pattern, corresponding to some metal bumps The method for fabricating a line structure according to claim 1, wherein the first patterning process comprises an alkaline etching process. The method of fabricating a wiring structure according to claim 2, wherein the etch stop layer comprises an anti-alkaline etching layer. The method for fabricating a line structure according to claim 2, wherein the material of the etch stop layer comprises tin, lead, chromium, nickel, indium, zinc, tungsten, molybdenum or The group formed by the combination. The method for fabricating a line structure according to claim 2, wherein the second patterning process comprises an acid etching, a dilute etching, a flash etching or an exposure developing process. The method for fabricating a line structure according to claim 1, wherein a thickness of each of the metal bumps is substantially greater than or equal to 100 micrometers (μm). The method for fabricating a circuit structure according to claim 1, further comprising: covering a photoresist layer on the first metal layer before performing the first patterning process; and performing the second patterning process Thereafter, the photoresist layer is removed. The method of fabricating the circuit structure of claim 1, wherein an outer surface of the first dielectric layer has a third metal layer, and the method for fabricating the circuit structure further comprises: patterning the third a metal layer to form a third patterned metal layer; and two second dielectric layers respectively formed on the first patterned metal layer and the third patterned metal layer. A circuit structure includes: a first metal layer; a first dielectric layer disposed on the first metal layer; and a plurality of metal bumps disposed on a surface of the first dielectric layer, wherein each a thickness of the metal bump is substantially greater than or equal to 100 microns; a second dielectric layer is disposed on the surface of the first dielectric layer and covers the metal bumps; and a plurality of via holes are respectively connected between the metal bumps and the first metal layer. The circuit structure of claim 1, further comprising a second metal layer disposed on an outer surface of the second dielectric layer. The circuit structure of claim 1, wherein the first metal layer comprises a smooth surface and a rough surface, the smooth surface is opposite to the rough surface, and the first dielectric layer is disposed on the rough surface . The circuit structure of claim 1, wherein the material of the first dielectric layer and each of the second dielectric layers comprises a ceramic or a prepreg (PP). A method for fabricating a circuit structure, comprising: providing a substrate, the substrate comprising a core layer, two release films, and two first metal layers, wherein the two release films are respectively disposed on opposite surfaces of the core layer, The two first metal layers are respectively disposed on the two release films; two first dielectric layers are respectively formed on the two first metal layers; and two patterned metal layers are respectively formed on the two first dielectric layers. Each of the patterned metal layers includes a plurality of metal bumps, and each of the metal bumps has a thickness substantially greater than or equal to 100 micrometers; and two second dielectric layers are respectively formed on the two patterned metal layers, the two a second dielectric layer respectively covering the two patterned metal layers; and separating the two release films from the corresponding first metal layers to form respective independent layers The two-line structure. The method for fabricating the circuit structure of claim 13, further comprising: separating the core layer from the two release films, forming a plurality of via holes on each of the first dielectric layers, and the conducting The holes are respectively connected between the metal bumps and the corresponding first metal layers. The method for fabricating a line structure according to claim 1, wherein an outer surface of each of the second dielectric layers has a second metal layer. The method for fabricating a line structure according to claim 1, wherein each of the first metal layers comprises a smooth surface and a rough surface, the smooth surface is opposite to the rough surface, and the first dielectric layer is disposed on On the rough surface. The method for fabricating a line structure according to claim 1, wherein the material of each of the first dielectric layer and each of the second dielectric layers comprises a ceramic or a prepreg (PP). The method for fabricating a wiring structure according to claim 1, wherein a thickness of the first metal layer is substantially 5 micrometers to 70 micrometers.