TW201616629A - Method for manufacturing a carrier having a cavity - Google Patents

Abstract

A method for manufacturing a carrier having a cavity includes the following steps. a film is provided. A metal lump is fixed to the film. A prepreg is laminated on the film and the metal lump so that the metal lump is embedded in the prepreg. The prepreg is cured so that the prepreg constructs a dielectric layer. The dielectric has a first surface and a second surface opposite to the second surface. The metal lump is embedded in the dielectric layer through the second surface. The film is removed to expose the metal lump and the second surface of the dielectric layer. A plurality of conductive through via, a first build-up circuit structure, and a second build-up circuit structure are formed. Each conductive through via passes the dielectric layer, the first build-up circuit structure is on the first surface of the dielectric layer, and a second build-up circuit structure is on the second surface of the dielectric layer. The metal lump is removed from the second surface of the dielectric layer to form a cavity thereat.

Description

Groove carrier plate manufacturing method

The present invention relates to a chip packaging technique, and more particularly to a method of fabricating a grooved carrier using a three-dimensional chip packaging technique.

Stereo chip packaging technology (or 3D IC packaging technology) is a very popular and emerging technology field in recent years, mainly using a three-dimensional stacking method to package wafers. In one common three-dimensional chip packaging technique, after mounting a wafer to a package carrier, the package carriers are stacked one on another such that the wafer is present between the two package carriers. Since the wafers located between the two package carriers inevitably have a certain thickness, the length of the joints between the package carriers must be greater than the thickness of the wafer, which increases manufacturing difficulty. Therefore, the corresponding method is to add an interposer between the package carriers to transmit signals, and to form a groove at the bottom of the interposer to accommodate the underlying wafer. Alternatively, a recess may be formed in the bottom of the package carrier to accommodate the underlying wafer.

The present invention provides a method of manufacturing a grooved carrier for manufacturing a grooved carrier.

A method of manufacturing a grooved carrier according to the present invention comprises the following steps. A film is provided. A metal block is fixed to the film. A fiber prepreg is laminated to the film and the metal block such that the metal block is embedded in the fiber prepreg. The fiber prepreg is cured such that the fiber prepreg forms a dielectric layer. The dielectric layer has a first side and a second side opposite the first side. The metal block is embedded in the dielectric layer from the second side. The film is removed to expose the metal block and the second side of the dielectric layer. A plurality of conductive vias, a first build-up line structure and a second build-up line structure are formed. Each of the conductive vias passes through the dielectric layer, the first build-up line structure is on the first side of the dielectric layer, and the second build-up line structure is on the second side of the dielectric layer and exposes the metal block. The metal block is removed from the second side of the dielectric layer to form a recess in the second side of the dielectric layer.

Based on the above, in the present invention, since the metal block is fixed to the film after being prepared in advance, the coplanarity of the metal block is good and the production rate can be improved. In addition, since the stress of the film itself is small, the stress generated by removing the film is small, thereby reducing the bending of the plate.

The above described features and advantages of the invention will be apparent from the following description.

102‧‧‧film

104‧‧‧metal block

106‧‧‧Fiber prepreg

107‧‧‧Dielectric layer

107a‧‧‧ first side

107b‧‧‧ second side

107c‧‧‧through hole

107d‧‧‧ Groove

108‧‧‧First metal layer

109‧‧‧First patterned metal layer

110‧‧‧Second metal layer

111‧‧‧Second patterned metal layer

112‧‧‧First patterned mask

114‧‧‧Second patterned mask

116‧‧‧First patterned conductive layer

118‧‧‧Second patterned conductive layer

120‧‧‧First line layer

122‧‧‧Second circuit layer

124‧‧‧ conductive vias

126‧‧‧First solder mask

128‧‧‧Second solder mask

130‧‧‧First build-up line structure

132‧‧‧Second layered line structure

134‧‧‧ Grooved carrier board

200, 200a‧‧‧Three-dimensional chip package structure

210‧‧‧ wafer

220‧‧‧Package carrier

1A to 1J illustrate a method of manufacturing a groove type carrier according to an embodiment of the present invention.

2A is a schematic view of the grooved carrier of FIG. 1J applied to a three-dimensional wafer package structure.

2B is a schematic view of the grooved carrier of FIG. 1J applied to another three-dimensional chip package structure.

Referring to FIG. 1A, in accordance with a method of manufacturing a grooved carrier in accordance with the present embodiment, a film 102 is first provided. The material of the film 102 may include polyimide (PI). Next, referring to FIG. 1B, a metal block 104 (eg, a copper block) is fixed to the film 102. In the present embodiment, the metal block 104 can be fixed to the film 102 in an adhesive manner. For example, the film 102 itself is viscous for adhering the metal block 104. In addition, the metal block 104 can be fabricated by a wide range of plating methods or mechanically stretched, thereby contributing to the improvement of the coplanarity of the metal block 104.

Referring to FIG. 1B, a fiber prepreg 106 is laminated on the film 102 and the metal block 104 such that the metal block 104 is embedded in the fiber prepreg 104. The fiber prepreg 104 is an adhesive sheet impregnated with resin using insulating paper, glass cloth or other fibrous material.

Referring to FIG. 1C, the fiber prepreg 106 is cured such that the fiber prepreg 106 forms a dielectric layer 107. Specifically, the fiber prepreg 106 can be cured by heating to form the dielectric layer 107. The dielectric layer 107 has a first surface 107a and is opposite to the first A second face 107b of the face 107a, and the metal block 104 is embedded in the dielectric layer 107 from the second face 107b. In the present embodiment, a first metal layer 108 and a fiber prepreg 106 are laminated on the film 102 and the metal block 104 at the same time. After the cured fiber prepreg 106 becomes the dielectric layer 107, the first metal layer 108 is disposed on the first surface 107a of the dielectric layer 107.

Referring to FIG. 1D, the film 102 of FIG. 1C is removed to expose the metal block 104 and the second side 107b of the dielectric layer 107.

Referring to FIG. 1E to FIG. 1I, after removing the film 102, a plurality of conductive vias 124 passing through the dielectric layer 107 may be formed, and a first build-up line structure 130 on the first side 107a of the dielectric layer 107. And a second build-up line structure 132 on the first side 107b of the dielectric layer 107. Finally, as shown in FIG. 1J, the metal block 104 is removed from the second side 107b of the dielectric layer 107 to form a recess in the second side 107b of the dielectric layer 107, thereby completing a recessed carrier 134.

How to form the conductive vias 124, the first build-up line structure 130, and the second build-up line structure 132 will be described in detail below.

Referring to FIG. 1E, after the film 102 is removed, a second metal layer 110 is laminated on the second side 107b of the dielectric layer 107. Next, referring to FIG. 1F , a plurality of through holes 107 c are formed through the first dielectric layer 107 , the first metal layer 108 , and the second metal layer 110 . These through holes 107c can be formed using laser drilling.

Referring to FIG. 1G, a first patterned mask 112 and a second patterned mask 114 are formed on the first metal layer 108 and the second metal layer 110, respectively. Then, the first patterned mask 112 and the second patterned mask 114 are plated for the plating mask to be on the first metal layer 108, on the second metal layer 110, and in the through holes. A first patterned conductive layer 116, a second patterned conductive layer 118 and the conductive vias 124 are formed in 107c.

Referring to FIG. 1H, the first patterned mask 112 and the second patterned mask 114 are removed. Next, the first metal layer 108 and the second metal layer 110 are patterned to form a first patterned metal layer 109 and a second patterned metal layer 111, respectively. The first patterned conductive layer 116 and the first patterned metal layer 109 form a first circuit layer 120, and the second patterned conductive layer 118 and the second patterned metal layer 111 form a second circuit layer 122.

In one embodiment, a metal layer (eg, a 2-3 micron nickel layer) may be formed on the first metal layer 108 and the second metal layer 110 as an etching mask to etch the first metal layer 108. And the second metal layer 110 to constitute the first patterned metal layer 109 and the second patterned metal layer 111, respectively. Thereafter, the aforementioned metal layer (i.e., the nickel layer) is removed by etching. In another embodiment, the first metal layer 108 and the second metal layer 110 are themselves a very thin metal layer (for example, a copper layer of 2 to 4 micrometers), and the first patterned conductive layer 116 and the second patterned layer. The metal layer 118 is a thicker metal layer (for example, a 16-22 micron copper layer) with respect to the first metal layer 108 and the second metal layer 110, so the first metal layer 108 can be removed by flash etching. The second metal layer 110 is respectively exposed by the first patterned conductive layer 116 and the second patterned metal layer 118, thereby patterning the first metal layer 108 and the second metal layer 110 to respectively form the first patterned metal Layer 109 and second patterned metal layer 111.

Referring to FIG. 1I, a first solder resist layer 126 and a second solder resist layer 128 are formed. The first solder resist layer 126 covers the first surface 107a of the dielectric layer 107 and the first line The road layer 120 is over and exposes a portion of the first circuit layer 120. The second solder mask layer 128 covers the second surface 107b and the second wiring layer 122 of the dielectric layer 107, and exposes the partial second wiring layer 122 and the metal block 104. In the present embodiment, the first build-up line structure 130 includes a first circuit layer 120 and a first solder resist layer 126 , and the second build-up line structure 132 includes a second circuit layer 122 and a second solder resist layer 128 .

However, in other embodiments not shown, the first build-up line structure or the second build-up line structure may further include a plurality of patterned conductive layers, at least one dielectric layer, and a plurality of conductive holes. The patterned conductive layers are interleaved with the dielectric layers, and the conductive holes are connected to the two patterned conductive layers through the dielectric layer.

Referring to FIG. 2A, the recessed carrier 134 of the embodiment of FIG. 1J can be applied to a three-dimensional chip package structure 200. In the three-dimensional chip package structure 200, two wafers 210 are mounted on the two package carriers 220, respectively, and the groove carrier 134 is disposed as an interposer between the two package carriers 220. The lower wafer 210 can be located within the recess 107d of the recessed carrier 134, thereby reducing the overall thickness of the three-dimensional wafer package structure 200.

Referring to FIG. 2B, the recessed carrier 134 of the embodiment of FIG. 1J can also be applied to a three-dimensional chip package structure 200a. In the three-dimensional chip package structure 200a, the groove type carrier 134 can also serve as a loading board on which the wafer 210 can be mounted and directly connected to the lower package carrier 220. Similarly, the underlying wafer 210 can be located within the recess 107d of the recessed carrier 134, thereby reducing the overall thickness of the three-dimensional wafer package structure 200a.

In summary, in the present invention, since the metal block is pre-made, It is fixed to the film, so the coplanarity of the metal block is good and the production rate can be increased. In addition, since the stress of the film itself is small, the stress generated by removing the film is small, thereby reducing the bending of the plate.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

107‧‧‧Dielectric layer

107a‧‧‧ first side

107b‧‧‧ second side

107d‧‧‧ Groove

120‧‧‧First line layer

122‧‧‧Second circuit layer

124‧‧‧ conductive vias

126‧‧‧First solder mask

128‧‧‧Second solder mask

130‧‧‧First build-up line structure

132‧‧‧Second layered line structure

134‧‧‧ Grooved carrier board

Claims (9)

A method for manufacturing a grooved carrier, comprising: providing a film; fixing a metal block to the film; laminating a fiber prepreg on the film and the metal block, so that the metal block is embedded in the fiber prepreg Forming the fiber prepreg such that the fiber prepreg forms a dielectric layer, wherein the dielectric layer has a first face and a second face opposite the first face, and the metal block is from the sheet The second surface is embedded in the dielectric layer; the film is removed to expose the metal block and the second surface of the dielectric layer; forming a plurality of conductive vias, a first build-up line structure, and a second increase a layer wiring structure, wherein each conductive via passes through the dielectric layer, the first build-up trace structure is on the first side of the dielectric layer, and the second build-up trace structure is on the dielectric layer And exposing the metal block; and removing the metal block from the second side of the dielectric layer to form a recess on the second side of the dielectric layer. The method for manufacturing a grooved carrier according to claim 1, wherein the material of the film comprises polyimine. The method of manufacturing a grooved carrier according to claim 1, wherein in the step of fixing the metal block to the film, the metal block is fixed to the film in an adhesive manner. The method for manufacturing a groove type carrier according to claim 3, wherein The film is viscous to adhere to the metal block. The method for manufacturing a grooved carrier according to claim 1, wherein in the step of fixing the metal block to the film, the material of the metal block comprises copper. The method of manufacturing a grooved carrier according to claim 1, wherein in the step of removing the metal block, etching is used to remove the metal block. The method for manufacturing a grooved carrier according to claim 1, wherein in the step of laminating the fiber prepreg on the film and the metal block, a first metal layer and the fiber are simultaneously A prepreg is laminated on the film and the metal block, and after curing the fiber prepreg, the first metal layer is disposed on the first side of the dielectric layer. The method for manufacturing a grooved carrier according to claim 7, further comprising: after removing the film, pressing a second metal layer on the second side of the dielectric layer; forming a plurality of a hole passing through the first dielectric layer, the first metal layer and the second metal layer; forming a first patterned mask and a second pattern on the first metal layer and the second metal layer a masking layer; the first patterned mask and the second patterned mask are plated for plating, respectively, on the first metal layer, on the second metal layer, and in the through holes respectively Forming a first patterned conductive layer, a second patterned conductive layer, and the conductive vias; removing the first patterned mask and the second patterned mask; The first metal layer and the second metal layer are patterned to form a first patterned metal layer and a second patterned metal layer, wherein the first patterned conductive layer and the first patterned metal layer are formed a first circuit layer, the second patterned conductive layer and the second patterned metal layer form a second circuit layer, the first build-up line structure includes the first circuit layer, and the second build-up line structure The second circuit layer is included. The method for manufacturing a grooved carrier according to claim 8 , further comprising: forming a first solder resist layer and a second solder resist layer, wherein the first solder resist layer covers the dielectric layer And the first circuit layer is exposed on the first surface and the first circuit layer, and the second solder resist layer covers the second surface of the dielectric layer and the second circuit layer, and Exposing a portion of the second circuit layer and the metal block, wherein the first build-up line structure includes the first circuit layer and the first solder resist layer, and the second build-up line structure includes the second circuit layer And the second solder mask.