TWI741370B - Method for making circuit structure having interlayer via hole - Google Patents

Abstract

A circuit structure having interlayer via hole includes a base circuit board, a photocurable insulating layer and a second circuit layer. The base circuit board has a first circuit layer located at a topmost layer of the base circuit board. The insulating layer covers the first circuit layer and has multiple via holes from which a part of the first circuit layer is exposed. The second circuit layer is formed on the top surface of the insulating layer. The second circuit layer has multiple openings corresponding to the via holes respectively. Each via hole has the same contour with its corresponding opening.

Description

Method for manufacturing circuit structure with interlayer vias

The invention relates to a circuit board structure, in particular to a circuit structure of interlayer vias and a manufacturing method thereof.

As the circuit design of 3C equipment becomes more refined, the requirements for the fineness of its carrier board circuits are also increasing. In the structure of the existing circuit carrier board involving the electrical connection between layers, a via hole is drilled in the insulating layer between the two layers of circuits, and then a copper layer (namely build-up layer) is added to the insulating layer by electroless plating and electroplating. Processing), and then graphically process the copper layer.

That is to say, in the prior art, it is stereotyped that the insulating layer is the inner layer. Therefore, before the build-up process, it is necessary to pre-form the via holes needed in the inner layer in the insulating layer, and then form a copper layer on it. . However, the existing process has its shortcomings in that the electroplating and subsequent brushing process will make the copper thickness of the surface circuit layer uneven, resulting in extremely difficult production of small-pitch surface circuit layers, and the yield rate is too low to be mass-produced. The electroplating process will also increase the thickness of the copper layer of the surface circuit layer, and once the thickness of the copper layer cannot be reduced, it is difficult to form a fine circuit structure, and the circuit density is difficult to increase.

The main purpose of the present invention is to provide a circuit structure that is easy to manufacture interlayer vias and a manufacturing method thereof.

In order to achieve the above and other objectives, the present invention provides a circuit structure with interlayer vias, which includes a base circuit board, a photocurable insulating layer, and a second circuit layer. The base circuit The board has a first circuit layer, the first circuit layer is located on the top surface of the base circuit board, the insulating layer covers the first circuit layer, the insulating layer has a plurality of via holes, and a part of the first circuit layer is exposed from the via holes The second circuit layer is formed on the top surface of the insulating layer, and the second circuit layer has a plurality of window areas corresponding to the via holes, and the contours of the corresponding via holes and the window area are the same.

In order to achieve the above and other objectives, the present invention also provides a method for manufacturing a circuit structure with interlayer vias, including providing a base circuit board, the base circuit board has a first circuit layer, and the first circuit layer is located on the topmost layer of the base circuit board Laminate a light-curable insulating layer with copper foil on the top surface of the first circuit layer; form a plurality of window areas on the copper foil; remove the insulating layer in the contour of the window area to form the insulating layer Forming a plurality of via holes respectively corresponding to the window opening areas, so that a part of the first circuit layer is exposed from the via holes; wherein, before forming the via holes, the entire insulating layer is subjected to light curing treatment; And after forming the via hole, the copper foil is patterned into a second circuit layer.

The invention utilizes the characteristic that the photo-curable resin can be directly removed by the etching solution before the photo-curing treatment, directly laminating a photo-curable insulating layer with copper foil on the top surface of the first circuit layer, and then only At the position where the guide hole needs to be provided, the window area is formed in the copper foil first, and the position where the guide hole needs to be provided is exposed, and the incompletely cured insulating layer can be removed directly by etching liquid or other methods. The method provided by the present invention not only facilitates the formation of interlayer vias, but also eliminates the steps of electroless plating and circuit build-up treatment on the insulating layer, thereby solving many problems in the prior art due to the build-up treatment.

10: base circuit board

11: Substrate

12: The first circuit layer

20: Insulation layer

21: Pilot hole

30: The second circuit layer

30A: Copper foil

31: window area

40: conductive layer

Fig. 1 is a schematic cross-sectional view of one embodiment of the micro-interlayer circuit structure of the present invention.

Figures 2 to 6 are schematic diagrams of the manufacturing process of one embodiment of the micro-interlayer circuit structure of the present invention.

Please refer to FIG. 1, which is an embodiment of the fine interlayer circuit structure of the present invention, which has a base circuit board 10, an insulating layer 20, a second circuit layer 30 and a conductive layer 40.

In this embodiment, the base circuit board 10 has a single-layer board structure, which has a substrate 11 and a first circuit layer 12 on the topmost layer. The first circuit layer 12 is, for example, a copper layer. In other possible embodiments, the base circuit board may also be a multilayer board with multiple circuit layers.

The insulating layer 20 covers the first circuit layer 12, and the insulating layer 20 has a plurality of via holes 21, a part of the first circuit layer 12 is exposed from the via holes 21; in this embodiment, the via holes 21 No copper plating layer is formed on the hole wall, that is, the vias 21 are not subjected to electroless plating or electroplating treatment. The insulating layer 20 is made of a photoimageable resin (such as PI) and has photocurable properties, which can be directly removed by the etching solution before the photocuring process.

The second circuit layer 30 is formed on the top surface of the insulating layer 20. The second circuit layer 30 is a copper layer, and its thickness is preferably less than 5 μm to form fine circuits.

The conductive layer 40 is formed in the vias 21, so that the first and second circuit layers 12, 30 are electrically connected through the conductive layer 40. For example, the conductive layer 40 is selected to have a conductivity lower than 1.0×10 ^-4 Ω·cm Conductive paste, such as conductive silver paste or conductive copper paste.

In a possible implementation, the second circuit layer 30 can be used to mount surface mounted devices. At this time, the top surface of the second circuit layer 30 can also form an electroplated nickel/gold layer commonly known as "soft gold" , But not shown in the figure.

Hereinafter, the manufacturing process of the foregoing embodiment will be described through FIGS. 2-6.

As shown in Figure 2, first, a base circuit board 10 is provided. In this embodiment, the base circuit board 10 is exemplarily shown as a single-layer board structure with a base material 11 and a first circuit layer on the topmost layer. 12, such as a copper layer, the first circuit layer 12 can be made by performing conventional patterning processing on the copper layer according to the required circuit design. In addition, an insulating layer 20 with a copper foil 30A preset on the top surface is also provided.

As shown in Figure 3, a vacuum laminating machine (not shown) is used to laminate an insulating layer 20 preset with a copper foil 30A on the top surface of the first circuit layer 12. The thickness of the copper foil 30A is less than 5 μm, and the insulating layer 20 It is a photoimageable resin, and the insulating layer 20 has not yet been cured by light during lamination.

As shown in Figure 4, a plurality of windowed areas 31 are formed on the copper foil 30A. The specific method can be to attach a thin photolithography layer on the copper foil 30A, expose and develop the photolithography layer, and etch it. The copper covered by the layer is finally removed from the photolithography layer, so that the partial insulating layer 20 is exposed from the window area 31.

As shown in Figure 5, the insulating layer 20 is etched to remove the exposed part of the windowed area 31, so that a plurality of conductive layers corresponding to the windowed areas 31 and having the same outline are formed in the insulating layer 20. The holes 21 further expose a part of the first circuit layer 12 from the via holes 21. The insulating layer 20 after the via 21 is formed can be subjected to necessary post curing treatment.

As shown in FIG. 6, the copper foil 30A is patterned into a second circuit layer 30, and the second circuit layer 30 can be made by conventional patterning according to the required circuit design.

Finally, a dispenser is used to fill the vias 21 with conductive paste, such as conductive silver paste or conductive copper paste, to form a conductive layer 40, so that the first circuit layer 12 and the second circuit layer 30 form an electrical connection. It becomes the structure shown in Figure 1.

In the foregoing manufacturing process, the copper foil 30A is patterned into the second circuit layer before the conductive paste is filled in the via 21. However, in other possible embodiments, the conductive paste can also be filled in the via 21 in advance. The copper foil 30A is patterned.

In the foregoing manufacturing process, the formation of the window area 31 and the formation of the via 21 are achieved through two steps. However, in other possible implementations, a laser engraving machine can also be used to burn through the copper foil 30A and the insulating layer 20 at the same time. The window opening area 31 and the guide hole 21 are simultaneously formed in one processing station.

In summary, the present invention utilizes the feature that the photo-curable resin can be directly removed by the etching solution before the photo-curing treatment, and directly laminates a photo-curable insulating layer with copper foil on the top surface of the first circuit layer. Then, it is only necessary to form a window area in the copper foil at the position where the guide hole is needed, and the position where the guide hole needs to be provided can be exposed, and the incompletely cured insulating layer can be directly removed by etching liquid or other methods. The method provided by the present invention not only facilitates the formation of interlayer vias, but also eliminates the steps of electroless plating and circuit build-up treatment on the insulating layer, thereby solving many problems in the prior art due to the build-up treatment.

10: base circuit board

11: Substrate

12: The first circuit layer

20: Insulation layer

21: Pilot hole

30: The second circuit layer

31: window area

40: conductive layer

Claims (2)

A method for manufacturing a circuit structure with interlayer vias includes: providing a base circuit board, the base circuit board having a first circuit layer, the first circuit layer is located on the top layer of the base circuit board; in the first circuit layer The top surface is laminated with a light-curable insulating layer with a copper foil on the top surface; a plurality of window areas are formed on the copper foil; the insulating layer in the outline of the window areas is removed to form the insulating layer A plurality of via holes corresponding to the window opening areas are formed so that a part of the first circuit layer is exposed from the via holes; wherein, before the via holes are formed, the entire insulating layer is not performed Light curing treatment; and after forming the via hole, the copper foil is patterned into a second circuit layer. According to the method for manufacturing a circuit structure with interlayer vias according to claim 2, wherein after the vias are formed, a conductive layer that electrically connects the first and second circuit layers is formed in the vias.

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