TWI513392B - Manufacturing method for circuit structure embedded with electronic device - Google Patents

Description

Circuit structure for embedded electronic components

The present invention relates to a wiring structure, and more particularly to a wiring structure for a buried electronic component.

In recent years, in order to increase the application of printed circuit boards (PCBs), many techniques have been made to fabricate printed circuit boards into a multilayer wiring structure. The multi-layer circuit structure is formed by repeatedly stacking and bonding a layered structure composed of a copper foil and a prepreg (pp) to a core board for adding a multilayer circuit structure. The internal wiring space is filled with a conductive material in the blind vias using an electroplating process to turn on the layers. In addition, many suitable electronic components, such as passive electronic components, can also be embedded in multi-layer wiring structures as needed to increase the application of multilayer wiring structures.

In the manufacturing method of the wiring structure of the embedded electronic component of the prior art, before the laminated structure composed of the copper foil and the prepreg is pressed onto the core plate, the laser processing or mechanical drilling is performed on the core plate. Mode setting for accommodating electronic components Groove. In order to enable the electronic component to be placed in the recess, one side of the recess requires prior tape or other suitable securing member to close the recess. As such, the electronic component can be disposed within the recess and temporarily secured to a location of the recess by tape. Thereafter, the electronic component can be buried and fixed in the core board after the other prepregs are pressed onto the core board, and the tape can be removed after the electronic component is fixed in the core board. After the electronic component is buried in the core board through the above manner, the buildup structure composed of more prepreg and copper foil can continue to be pressed on the core board to complete the multilayer circuit structure of the embedded electronic component. However, the above manufacturing process is complicated, for example, it is necessary to arrange a groove on the core board by an additional processing process, and an additional consumable (for example, the aforementioned tape) is used as a step of disposing the electronic component in the groove. Auxiliary, the above production method produces higher production costs.

The invention provides a method for manufacturing a line structure of a buried electronic component, which has a simple manufacturing process and can reduce the manufacturing cost.

The method for fabricating the wiring structure of the embedded electronic component of the present invention comprises the following steps: providing a first dielectric material. Disposing at least one electronic component on the first dielectric material. Pressing a second dielectric material on the first dielectric material, and disposing the two conductive materials on the first dielectric material and the second dielectric material respectively, so that the electronic component is buried in the first dielectric material and the second dielectric material Between the dielectric materials, the first dielectric material and the second dielectric material are respectively located between the electronic component and the corresponding conductive material, and the first dielectric material, the second dielectric material, the electronic component and the two conductive materials form a core board. Forming an inner layer on the core board and the inner layer The line connects the electronic components.

In an embodiment of the invention, in the step of providing the first dielectric material, the first dielectric material is disposed on a carrier board, and a release layer is disposed between the first dielectric material and the carrier board. After the step of disposing the electronic component on the first dielectric material, the release layer and the carrier plate are removed from the first dielectric material.

In an embodiment of the invention, the method for fabricating the line structure of the embedded electronic component further includes forming a plurality of alignments on the first dielectric material before the step of disposing the electronic component on the first dielectric material Target hole.

In an embodiment of the invention, the method for fabricating the line structure of the embedded electronic component further includes: arranging at least one heat curing on the first dielectric material before the step of disposing the electronic component on the first dielectric material gum.

In an embodiment of the invention, in the step of disposing the electronic component on the first dielectric material, the electronic component is disposed on the thermosetting adhesive, and the thermosetting adhesive is cured after being subjected to a baking process to The component is attached to the first dielectric material.

In an embodiment of the invention, the step of forming the inner layer line on the core board further comprises the steps of: forming at least one blind via on the second dielectric material, and the blind via is connected to the electronic component. Etching the two conductive materials and forming a conductive layer in the blind hole, so that the two conductive materials form two inner layer circuit patterns, and the conductive layer is connected to the inner layer circuit pattern and the electrons on the second dielectric material through the blind holes. The components, while the two inner layer patterns and the conductive layer form an inner layer line.

In an embodiment of the invention, the step of forming a blind via includes a laser process, and the step of etching the two conductive materials includes a lithography process to form a conductive layer in a blind The steps within the well include an electroplating process.

In an embodiment of the invention, the method for fabricating the wiring structure of the embedded electronic component further includes forming at least one dielectric layer and at least one build-up line on the core board, wherein the dielectric layer is on the build-up line and Between the inner layers, and the build-up lines connect the inner lines.

In an embodiment of the invention, the method for fabricating the line structure of the embedded electronic component further includes performing a surface finish on the build-up line.

In an embodiment of the invention, the material of the first dielectric material and the second dielectric material comprises a prepreg (PP) doped with glass fibers, and the material of the two conductive materials comprises copper foil ( Copper foil).

Based on the above, in the method of fabricating the wiring structure of the embedded electronic component of the present invention, the electronic component is disposed on the first dielectric material, and the second dielectric material is pressed onto the first dielectric material to embed the electronic component in the electronic component. The first dielectric material and the second dielectric material are disposed on the first dielectric material and the second dielectric material to form a core plate. In this way, the electronic components are buried therein in the manufacturing process of the core board, and the processing steps and related consumables required for arranging the recesses for accommodating the electronic components on the core board in the prior art can be omitted. Accordingly, the method for fabricating the wiring structure of the embedded electronic component of the present invention has a simple manufacturing process and can reduce the manufacturing cost.

The above described features and advantages of the invention will be apparent from the following description.

20‧‧‧Loading board

30‧‧‧Fractal layer

100‧‧‧Line structure of embedded electronic components

102‧‧‧ core board

110‧‧‧First dielectric

112‧‧‧ alignment target hole

114‧‧‧Hot Curing Adhesive

120‧‧‧Electronic components

122a, 122b‧‧‧ electrodes

130‧‧‧Second dielectric

132, 162‧‧ ‧ blind holes

134‧‧‧through hole

140a and 140b‧‧‧electric materials

150‧‧‧ Inner line

152a, 152b‧‧‧ inner layer circuit pattern

154, 174‧‧‧ conductive layer

160‧‧‧ dielectric layer

170‧‧‧Additional line

172‧‧‧Additional line pattern

180‧‧‧ solder mask

182‧‧‧ openings

190‧‧‧ solder pads

1 is a flow chart showing a method of fabricating a wiring structure of a buried electronic component according to an embodiment of the present invention.

2A to 2J are schematic diagrams showing a manufacturing process of a wiring structure of the embedded electronic component of FIG. 1.

1 is a flow chart showing a method of fabricating a wiring structure of a buried electronic component according to an embodiment of the present invention. 2A to 2J are schematic diagrams showing a manufacturing process of a wiring structure of the embedded electronic component of FIG. 1. Referring to FIG. 1 and FIG. 2A to FIG. 2J, in the embodiment, the manufacturing method of the wiring structure of the embedded electronic component includes the following steps: In step S110, the first dielectric material 110 is provided. In step S120, at least one electronic component 120 is disposed on the first dielectric material 110. In step S130, the second dielectric material 130 is pressed onto the first dielectric material 110, and the two conductive materials 140a and 140b are respectively disposed on the first dielectric material 110 and the second dielectric material 130 to make the electrons. The component 120 is embedded between the first dielectric material 110 and the second dielectric material 130. The first dielectric material 110 and the second dielectric material 130 are respectively located between the electronic component 120 and the corresponding conductive materials 140a and 140b. The first dielectric material 110, the second dielectric material 130, the electronic component 120, and the two conductive materials 140a and 140b form a core board 102. In step S140, the inner layer line 150 is formed on the core board 102, and the inner layer line 150 is connected to the electronic component 120. In step S150, at least one dielectric layer 160 and at least one build-up line 170 are formed on the core board 102, wherein the dielectric layer 160 is located on the build-up line 170 and the inner layer line 150. Between, and the build-up line 170 is connected to the inner layer line 150. In step S160, the build-up line 170 is subjected to surface treatment. Hereinafter, a method of fabricating the wiring structure of the embedded electronic component of the present embodiment will be sequentially described with reference to FIGS. 2A to 2J.

First, in step S110, a first dielectric material 110 is provided. Referring to FIGS. 1 and 2A, in the embodiment, in the step of providing the first dielectric material 110, the first dielectric material 110 is disposed on the carrier board 20, and the release layer 30 is disposed on the first dielectric material 110 and the carrier. Between the boards 20. The material of the first dielectric material 110 of the present embodiment is, for example, a glass fiber prepreg (PP), so that the first dielectric material 110 has good strength, but the invention is not limited to the first medium. The material of the electrical material 110. Furthermore, the first dielectric material 110 is disposed on the carrier 20 having good strength, which facilitates subsequent processing of the first dielectric material 110, for example, configuring a blind hole or arranging a colloid on the first dielectric material 110 (eg, subsequent Description). Furthermore, the release layer 30 is disposed between the first dielectric material 110 and the carrier plate 20 to facilitate separation of the first dielectric material 110 from the carrier plate 20 after processing the first dielectric material 110. However, the present invention does not limit the configuration of the release layer 30 and the carrier plate 20, which may be selected as needed.

Next, in step S120, at least one electronic component 120 is disposed on the first dielectric material 110. Referring to FIG. 1 and FIG. 2B , in the embodiment, before the step of disposing the electronic component 120 on the first dielectric material 110 , the method further includes forming a plurality of alignment target holes 112 on the first dielectric material 110 . . The alignment target hole 112 is formed on the first dielectric material 110 through a laser process, and penetrates the first dielectric material 110 and the release layer 30, but the present invention does not limit the formation manner of the alignment target hole 112, It can be selected according to needs. The alignment target hole 112 can be defined on the first dielectric material 110 The area where the electronic component 120 is placed is placed. For example, the alignment target hole 112 may be disposed on the periphery of the first dielectric material 110 where the electronic component 120 is disposed, and in the subsequent step of configuring the electronic component 120, the electronic component 120 may be in accordance with the alignment target hole 112. The position is adjusted to adjust its position on the first dielectric member 110.

Then, referring to FIG. 1 and FIG. 2C , in the embodiment, before the step of disposing the electronic component 120 on the first dielectric material 110 , the method further includes disposing at least one heat curing adhesive 114 on the first dielectric material 110 . . The heat curing adhesive 114 is formed on the first dielectric material 110 through a spray process. However, the present invention does not limit the formation manner of the heat curing adhesive 11, which can be selected according to requirements. In the step of disposing the thermosetting adhesive 114, the thermosetting adhesive 114 may be disposed at a predetermined portion on the first dielectric material 110 according to the position of the alignment target hole 112, for example, a region disposed between the alignment target holes 112. The predetermined position on the first dielectric material 110 is such that the electronic component 120 can be disposed through the heat curing adhesive 114 at a predetermined place on the first dielectric material 110.

Next, referring to FIG. 1 and FIG. 2D , in the embodiment, in the step of disposing the electronic component 120 on the first dielectric material 110 , the electronic component 120 is disposed on the thermosetting adhesive 114 . Specifically, the electronic component 120 of the embodiment is illustrated as four, but the number of the electronic components 120 can be adjusted according to requirements, and the number and position of the thermosetting adhesives 114 correspond to the number and position of the electronic components 120. In addition, the electronic component 120 may be a thin passive electronic component such as a Si-base film capacitor having a thickness of about 35 micrometers (μm), but the invention is not limited thereto. Since the embodiment first forms the alignment target hole 112 on the first dielectric material 110 before the step of disposing the electronic component 120 on the first dielectric material 110, The thermosetting adhesive 114 is disposed at a predetermined position on the first dielectric material 110 according to the position of the alignment target hole 112. Therefore, in the step of disposing the electronic component 120 on the first dielectric material 110, the electronic component 120 can be aligned according to the alignment. The position of the target hole 112 is disposed at a predetermined place on the first dielectric material 110 through the corresponding heat curing adhesive 114. After the electronic component 120 is disposed on the thermosetting adhesive 114, the thermosetting adhesive 114 is cured by the baking process to fix the electronic component 120 to the first dielectric material 110. Among them, the material of the thermosetting adhesive 114 may be selected from materials having a shorter curing time. As such, the thermosetting adhesive 114 only needs to be cured by baking for a short period of time, and the temperature and time of baking the thermosetting adhesive 114 does not cause the first dielectric material 110 to change (for example, is melted by heat). The electronic component 120 can be fixed to the first dielectric material 110 through the heat curing adhesive 114. However, in other embodiments, the electronic component 120 can be directly disposed on the first dielectric material 110 or disposed on the first dielectric material 110 through other kinds of colloids. The present invention does not limit the configuration of the thermal curing adhesive 114. The arrangement of the electronic components 120.

Then, referring to FIG. 1 and FIG. 2E , in the embodiment, since the first dielectric material 110 is disposed on the carrier layer 20 and the release layer 30 , the electronic component 120 is disposed on the first dielectric material 110 after the completion of the foregoing. After the step, the release layer 30 and the carrier sheet 20 are removed from the first dielectric material 110. Since the release layer 30 is disposed between the first dielectric material 110 and the carrier plate 20, the carrier layer 20 and the release layer 30 can be easily removed from the first dielectric material 110. However, in the embodiment in which the carrier 20 and the release layer 30 are not disposed, the step of removing the carrier 20 and the release layer 30 may be omitted.

Next, in step S130, the second dielectric material 130 is pressed onto the first dielectric material 110, and the two conductive materials 140a and 140b are respectively disposed on the first dielectric material. 110 and the second dielectric material 130, so that the electronic component 120 is buried between the first dielectric material 110 and the second dielectric material 130, and the first dielectric material 110 and the second dielectric material 130 are respectively located in the electronic component 120 and the corresponding conductive materials 140a and 140b, and the first dielectric material 110, the second dielectric material 130, the electronic component 120 and the two conductive materials 140a and 140b form the core board 102. Referring to FIG. 1 and FIG. 2F , in the embodiment, the second dielectric material 130 is pressed onto the first dielectric material 110 , wherein the material of the second dielectric material 130 is, for example, a prepreg doped with glass fibers, so that The second dielectric material 130 has good strength, but the invention does not limit the material of the second dielectric material 130. After the second dielectric material 130 is pressed against the first dielectric material 110, the prepreg in the second dielectric material 130 covers the electronic component 120 and is filled into the alignment target hole 112 on the first dielectric material 110. As such, the electronic component 120 is buried between the first dielectric material 110 and the second dielectric material 130. Since the electronic component 120 of the present embodiment is a thin passive electronic component, the thin electronic component 120 can be easily covered by the first dielectric material 110 and the second dielectric material 130. In addition, the material of the conductive materials 140a and 140b, such as a copper foil or other suitable conductive material, is not limited by the present invention. In this step, the two conductive materials 140a and 140b are respectively disposed on the outer surfaces of the first dielectric material 110 and the second dielectric material 130, wherein the second dielectric material 130 and the conductive material 140b disposed thereon can be sequentially borrowed The first dielectric material 110 and the electronic component 120 are disposed on the first dielectric material 110 and the electronic component 120 by different processes, and may be fabricated into a composite material plate in advance and pressed onto the first dielectric material 110 and the electronic component 120 through the same process. So far, the first dielectric material 110, the second dielectric material 130, the electronic component 120 and the two conductive materials 140a and 140b form the core board 102, and the electronic component 120 is buried in the core board 102.

Next, in step S140, the inner layer line 150 is formed on the core board 102, and the inner layer line 150 is connected to the electronic component 120. In this embodiment, the step of forming the inner layer line 150 on the core board 102 (step S140) further comprises the steps of: forming at least one blind hole 132 on the second dielectric material 130, and the blind hole 132 is connected to the electronic component 120. . The two conductive materials 140a and 140b are etched, and the conductive layer 154 is formed in the blind hole 132, so that the two conductive materials 140a and 140b form two inner layer wiring patterns 152a and 152b, and the conductive layer 154 is connected through the blind hole 132. The inner layer wiring pattern 152b on the second dielectric material 130 and the electronic component 120, and the two inner layer wiring patterns 152a and 152b and the conductive layer 154 form the inner layer wiring 150. Furthermore, the step of forming the inner layer line 150 on the core board 102 (step S140) may further include the steps of: forming at least one through hole 134 on the core board 102, and the through hole 134 penetrating the core board 102. The conductive layer 154 is formed in the via 134 such that the inner layer trace patterns 152a and 152b are electrically connected to each other through the conductive layer 154 located in the via 134.

Specifically, referring to FIG. 1 and FIG. 2G, in the embodiment, after the core board 102 is completed through the above steps, and the electronic component 120 is buried in the core board 102, the blind hole 132 is first formed on the second dielectric. On the material 130, the blind holes 132 communicate with the electronic component 120. In addition, the through hole 134 may be formed on the core board 102 in this step, and the through hole 134 penetrates the core board 102. In the present embodiment, the step of forming the blind via 132 and the via 134 is, for example, a laser process, and the blind via 132 and the via 134 are laser vias, but the invention is not limited thereto. In addition, in the present embodiment, each of the electronic components 120 has two electrodes 122a and 122b, and each of the two blind vias 132 correspondingly connects the two electrodes 122a and 122b of one electronic component 120. Such as Therefore, the subsequently formed inner layer line 150 can be connected to the electronic component 120 through the blind via 132. However, the number of electrodes is not limited, and may be two or more.

Next, referring to FIG. 1 and FIG. 2H, in the embodiment, the two conductive materials 140a and 140b are etched, and the conductive layer 154 is formed in the blind via 132. The step of etching the two conductive materials 140a and 140b is, for example, a lithography process to etch the two conductive materials 140a and 140b in accordance with the desired line layout to form two inner layer wiring patterns 152a and 152b. In addition, the step of forming the conductive layer 152 in the blind via 132 includes an electroplating process to fill the conductive via 154 in the blind via 132, and the conductive layer 154 is connected to the inner via on the second dielectric 130 through the blind via 132. The line pattern 152b and the electrodes 122a and 122b of the electronic component 120. Furthermore, the conductive layer 154 of the present embodiment is also formed in the through hole 134, so that the inner layer wiring patterns 152a and 152b formed by the conductive materials 140a and 140b pass through the conductive layer 154 located in the through hole 134. Electrical connection. As such, the inner layer lines 152a and 152b and the conductive layer 154 located in the blind via 132 and the via 134 form the inner layer line 150, and the inner layer line 150 connects the electronic component 120. So far, the wiring structure 100 of the embedded electronic component 120 of the present embodiment has been initially completed, and has a core board 102, an electronic component 120 embedded in the core board 102, and an inner layer line 150 connecting the electronic component 120. However, in addition to the inner layer line 150, the line structure 100 of the buried electronic component 120 of the present embodiment can also be configured with an additional build-up line 170 (shown in FIG. 2I) that has the wiring structure of the embedded electronic component 120. 100 becomes a multi-layered line structure 100.

In step S150, at least one dielectric layer 160 and at least one build-up line 170 are formed on the core board 102, wherein the dielectric layer 160 is located in the build-up line 170 and Between the layer lines 150, and the build-up line 170 is connected to the inner layer line 150. Specifically, please refer to FIG. 1 and FIG. 2I. In the embodiment, the number of the dielectric layer 160 and the build-up line 170 are respectively two, but the invention is not limited thereto. One of the dielectric layers 160 corresponds to one of the build-up lines 170 and is pressed against the first dielectric material 110. The dielectric layer 160 covers the first dielectric material 110 and the inner layer wiring pattern 152a located on the first dielectric material 110, and is located between the inner layer wiring 150 and the build-up wiring 170. The build-up layer 170 disposed on the dielectric layer 160 can be formed by, for example, the method of fabricating the inner layer line 150 described above. First, a conductive material (not shown) is disposed on the dielectric layer 160, wherein the dielectric layer 160 is The conductive material may be sequentially pressed onto the first dielectric material 110 by different processes, or may be first formed into a composite material and then pressed onto the first dielectric material 110 by the same process. Thereafter, a blind via 162 is disposed on the dielectric layer 160 by a laser process, and the build-up wiring pattern 172 is formed by etching the conductive material by a lithography process, and a connection build-up line pattern is formed in the blind via 162 by an electroplating process. 172 and conductive layer 174 of inner layer pattern 152a, and build-up line pattern 172 and conductive layer 174 form build-up line 170. Similarly, another dielectric layer 160 corresponds to another build-up line 170 and is laminated to the second dielectric material 130. The dielectric layer 160 covers the second dielectric material 130 and the inner layer wiring pattern 152b located on the second dielectric material 130, and is located between the inner layer wiring 150 and the build-up wiring 170. In addition, the build-up line 170 is formed on the dielectric layer 160 by the foregoing manner, wherein the build-up line pattern 172 of the build-up line 170 and the conductive layer 174 are connected to the inner layer trace pattern 152b of the inner layer line 150. Therefore, in a similar manner, more dielectric layers 160 and build-up lines 170 may be disposed on the core board 102 or on the build-up line 170 that has been formed on the core board 102. The layer line 170 can be connected to the inner layer line 150 or to the more inner layer of the previous layer line 170 through the above-described fabrication manner, and a portion of the inner layer line 150 is also connected to the electronic component 120. As such, the wiring structure 100 for embedding electronic components can be configured with more dielectric layers 160 and build-up lines 170 as needed to form a multi-layered line structure 100, and the inner layer lines 150 and the build-up lines 170 are in communication with each other.

Finally, in step S160, the build-up line 170 is subjected to surface treatment. Referring to FIG. 1 and FIG. 2J, in the present embodiment, after the core board 102, the inner layer line 150, and the build-up line 170 are completed, the build-up line 170 is surface-treated. The surface treatment of this embodiment is, for example, forming the solder resist layer 180 and the plurality of pads 190 on the build-up line 170. Since the build-up electronic component 120 of the present embodiment has the build-up line 170 disposed on opposite sides of the line structure 100, the solder resist layer 180 is formed on each of the two build-up lines 170. The solder resist layer 180 covers the corresponding dielectric layer 160 and the build-up wiring 170, and a portion of the build-up wiring pattern 172 of the build-up wiring 170 is exposed by the plurality of openings 182. Thereafter, the pad 190 is disposed in the opening 182 and connected to the build-up wiring pattern 172. As such, the wiring structure 100 of the embedded electronic component 120 can be electrically connected to other electronic components (not shown) through the bonding pad 190, and the remaining portions covered by the solder resist layer 180 are electrically insulated from other electronic components.

In summary, in the method of fabricating the wiring structure of the embedded electronic component of the present invention, the electronic component is buried in the first dielectric material and the second while the second dielectric material is pressed onto the first dielectric material. Between the dielectric materials, the conductive material is disposed on the first dielectric material and the second dielectric material to form a core plate. In this way, the electronic component is buried in the manufacturing process of the core plate formed by the first dielectric material, the second dielectric material and the conductive material. The thin electronic component can be easily covered by the first dielectric material and the second dielectric material. The fabrication method of the present invention can omit the processing steps and associated consumables required to place the recesses on the core panel, as compared to conventional techniques for making recesses in the core board to accommodate electronic components. Accordingly, the method for fabricating the wiring structure of the embedded electronic component of the present invention has a simple manufacturing process and can reduce the manufacturing cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Line structure of embedded electronic components

102‧‧‧ core board

110‧‧‧First dielectric

120‧‧‧Electronic components

122a, 122b‧‧‧ electrodes

130‧‧‧Second dielectric

132‧‧‧Blind holes

134‧‧‧through hole

150‧‧‧ Inner line

152a, 152b‧‧‧ inner layer circuit pattern

154‧‧‧ Conductive layer

Claims (9)

A method for fabricating a wiring structure of an embedded electronic component, comprising: providing a first dielectric material; disposing at least one electronic component on the first dielectric material; and pressing a second dielectric material on the first dielectric material And disposing the two conductive materials on the first dielectric material and the second dielectric material respectively, so that the electronic component is buried between the first dielectric material and the second dielectric material, the first The dielectric material and the second dielectric material are respectively located between the electronic component and the corresponding conductive material, and the first dielectric material, the second dielectric material, the electronic component and the two conductive materials form a core board And forming an inner layer on the core board, and the inner layer is connected to the electronic component, wherein the step of forming the inner layer on the core board further comprises: forming at least one blind via to the second dielectric And forming at least one through hole on the core plate, wherein the blind hole communicates with the electronic component, and the through hole penetrates the core plate; and etches the two conductive materials, and forms a conductive layer in the blind hole and the Inside the through hole, so that the two conductive materials form two inner layers a circuit pattern, and the conductive layer is connected to the via hole through the blind via and the via layer on the second dielectric material and the electronic component, so that the two inner layer trace patterns and the conductive layers are formed The inner layer line. The method for fabricating a line structure of a buried electronic component according to claim 1, wherein in the step of providing the first dielectric material, the first dielectric material is provided And disposed on a carrier board, and a release layer is disposed between the first dielectric material and the carrier board, after the step of disposing the electronic component on the first dielectric material, the release layer and the carrier The board is removed from the first dielectric. The method for fabricating a line structure of a buried electronic component according to claim 1, further comprising: forming a plurality of the first dielectric material before the step of disposing the electronic component on the first dielectric material Counter target holes. The method for fabricating a line structure of a buried electronic component according to claim 1, further comprising: arranging at least the first dielectric material on the first dielectric material before the step of disposing the electronic component on the first dielectric material A heat curing adhesive. The method of fabricating a wiring structure for a buried electronic component according to claim 4, wherein in the step of disposing the electronic component on the first dielectric material, the electronic component is disposed on the thermosetting adhesive. And the thermosetting adhesive is cured after being subjected to a baking process to fix the electronic component on the first dielectric material. The method for fabricating a line structure of a buried electronic component according to claim 1, wherein the step of forming the blind hole comprises a laser process, and the step of etching the two conductive materials comprises a lithography process to form the conductive layer The steps within the blind via include an electroplating process. The method for fabricating a line structure of a buried electronic component according to claim 1, further comprising: forming at least one dielectric layer and at least one build-up line on the core board, wherein the A dielectric layer is between the build-up line and the inner layer line, and the build-up line connects the inner layer line. The method for fabricating a line structure of a buried electronic component according to claim 7, further comprising: surface treating the build-up line. The method for fabricating a line structure of a buried electronic component according to claim 1, wherein the material of the first dielectric material and the second dielectric material comprises a prepreg doped with glass fibers, and the two conductive materials are Materials include copper foil.