TW201540155A - Package substrate and manufacturing method thereof - Google Patents

Abstract

This invention provides a manufacturing method of package substrate, firstly providing a board body having opposite a first surface and a second surface, part of the first surface of the board body is formed with a release layer, then forming a first inner wiring layer on the first surface of the board body where the release layer is not covered, and simultaneously forming a cladding layer that covers the release layer on the release layer, after that, forming a first wiring adding layer structure on the first inner wiring layer and the cladding layer, and removing the structure of the release layer in a direction towards the second surface, so as to form an opening connecting the first and the second surfaces, and the opening extends to the cladding layer, to form a slot structure. The manufacturing method facilitates removal of the release layer by the design of the cladding layer. This invention further provides the package substrate.

Description

Package substrate and its preparation method

The invention relates to a package substrate, in particular to a package substrate capable of improving reliability and a preparation method thereof.

With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, and in order to meet the development direction of semiconductor packages, such as light, short, multi-functional, high-speed and high-frequency, The groove in which the component is placed can not only reduce the volume of the semiconductor device as a whole, but also enhance the electrical function, and becomes a packaging trend.

There are many ways to make grooves. For example, a core board and a circuit board having an opening are pressed, but it is easy to produce a precise error due to the alignment action when the connection is performed, and if the connection is bad, the layering problem is easily caused, and The process leads to a longer manufacturing time and thus increases costs.

In another way. The release film is embedded in the package substrate, and the structure on the release film is removed by the ejector pin. However, this method is only suitable for the groove of a larger size, and the bottom side of the package substrate needs to be formed with a socket for insertion of the thimble, so that the space for making the circuit of the package substrate is reduced.

Therefore, the industry has developed a method of making an opening, as shown in FIGS. 1A to 1B, which is a schematic cross-sectional view of a conventional method of manufacturing a package substrate 1.

As shown in FIG. 1A, a plate body 10 having a first surface 10a and a second surface 10b opposite to each other is provided, and a release layer 11 is formed on the first surface 10a, and is pressed on the first surface 10a. The line buildup structure 14 is integrated, and the circuit layer 13 is formed on the second surface 10b of the board 10.

As shown in FIG. 1B, the material of the wiring build-up structure 14 on the release layer 11 is removed to form an opening 100, and the release layer 11 is exposed to the opening 100 for placing electronic components such as semiconductor wafers ( Figure omitted).

However, in the conventional method of manufacturing a package substrate, since the release layer 11 contacts the line 140 of the board body 10 and the line build-up structure 14, and the board 10 and the line 140 are different in material, it is not easy to move. In addition to the release layer 11, the line 140 is easily damaged upon removal.

Moreover, if the release layer 11 is not removed, the space of the opening 100 will be made small, which is disadvantageous for the selectivity of placing electronic components.

Therefore, how to overcome the various problems of the above-mentioned prior art has become a difficult problem to be overcome in the industry.

The present invention provides a package substrate, comprising: a plate body having opposite first and second surfaces, The circuit layer is disposed on the first surface of the board body, and the first inner circuit layer has an exposed portion exposed to the opening, the edge of the exposed portion has a channel; and the first line build-up structure The first inner circuit layer is disposed on the first inner circuit layer, and the opening extends to the exposed portion, so that the exposed portion and the opening serve as a groove structure.

In the above package substrate, the depth of the channel is less than 25 μm, and the exposed portion is exposed to a height difference between the surface of the opening and the first surface.

The present invention also provides a package substrate, comprising: a plate body having opposite first and second surfaces, and an opening connecting the first and second surfaces; the first inner circuit layer is disposed on the plate body And the first line build-up structure is disposed on the first inner circuit layer and covers one side of the opening, and the opening extends to the first line build-up structure to form a groove structure. A portion of the first line build-up structure is made to be the bottom of the trench structure.

In the foregoing package substrate, the surface of the bottom portion in the opening has a height difference from the first surface.

The invention provides a method for manufacturing a package substrate, comprising: providing a plate body having an opposite first surface and a second surface, defining a pre-removed area on the first surface, and forming the pre-removed area a release layer; a first inner circuit layer formed on the first surface of the plate body not covered by the release layer, and a cladding layer covering the release layer is formed on the release layer; Forming a first line build-up structure on the circuit layer and the cover layer; and removing the release layer and the structure of the pre-removal area toward the second surface to form a communication between the first and second surfaces Opening, and the opening extends to the first cladding layer to form a groove structure.

In the above method, the material of the release layer is a non-stick or non-stick material. For example, the thickness of the release layer is at most 100 μm.

In the above method, the material between the second surface of the plate and the release layer is removed by blind routing. For example, the deep blind fishing method is performed along the edge of the release layer.

In the above method, the coating layer is exposed to the opening as the bottom of the groove structure, and the surface of the coating layer has a height difference from the first surface, and after the opening is formed, the edge of the bottom portion There is a channel, and the depth of the channel is less than 25 μm.

In the above method, when the opening is formed, the portion of the cladding exposed to the opening is removed, and the first line build-up structure is exposed to the opening to serve as the bottom of the trench structure, and the bottom portion There is a height difference between the surface and the first surface.

In the above package substrate and method of manufacturing the same, a circuit layer is formed on the second surface of the board.

In addition, in the foregoing package substrate and the manufacturing method thereof, the second line build-up structure is formed on the second surface of the board body, and the material between the second surface of the board body and the release layer is removed. At the same time, the material on the second surface of the plate body is removed. In this case, the upper layer is added once, and the layer may be selectively added and then removed according to the user's requirements.

As can be seen from the above, the package substrate of the present invention and the method for preparing the same by covering the release layer with the cladding layer, the release layer only contacts the cladding layer when the release layer is removed. The release layer is easily removed without damaging the wiring of the line build-up structure and providing a large space for the opening to facilitate the placement of electronic components.

1,2,2'‧‧‧Package substrate

10,20‧‧‧ board

10a, 20a‧‧‧ first surface

10b, 20b‧‧‧ second surface

100,200‧‧‧ openings

11,21‧‧‧ release layer

13,241,251‧‧‧ circuit layer

14‧‧‧Line layering structure

140‧‧‧ lines

22‧‧‧First inner circuit layer

22'‧‧‧Cladding

22a, 22b‧‧‧Metal

220‧‧‧Exposed Department

221‧‧‧Channel

23‧‧‧Second inner circuit layer

24‧‧‧First line build-up structure

240, 250‧‧‧ dielectric layer

242,252‧‧‧ conductive blind holes

25‧‧‧Second line build-up structure

26,26’‧‧‧ trough structure

260, 260’ ‧ ‧ bottom

C‧‧‧Pre-removal area

D, T‧‧‧ height difference

D‧‧‧depth

T‧‧‧thickness

1A to 1B are schematic cross-sectional views showing a method of manufacturing a conventional package substrate;

2A to 2E are schematic cross-sectional views showing a method of manufacturing the package substrate of the present invention; wherein the 2E' diagram is another embodiment of the 2Eth diagram.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower", "first", "second", "one", and the like, are used for convenience of description, and are not intended to limit the present invention. The scope of the invention, the change or adjustment of the relative relationship, is also considered to be within the scope of the invention.

2A to 2E are schematic cross-sectional views showing a method of manufacturing the package substrate 2 of the present invention.

As shown in FIG. 2A, a plate body 20 having a first surface 20a and a second surface 20b opposite thereto is provided, and a release layer 21 is formed on the first surface 20a. Then, the metal materials 22a, 22b are simultaneously formed on the first surface 20a and the second surface 20b of the plate body 20, and the metal materials 22a, 22b are, for example, copper plating, copper plating, or the like, and are not particularly limited.

In this embodiment, the plate body 20 can be a substrate after the copper foil substrate is removed from the copper foil, and the release layer 21 is formed after the copper foil is removed.

Furthermore, a pre-removed area C is defined on the first surface 20a such that the release layer 21 is disposed only on the pre-removed area C.

Moreover, the material of the release layer 21 is an anti-adhesive or non-adhesive solid release film material, such as a solid release polyimine (PI) material, and the thickness of the release layer 21 is t It is between about 1 μm and 100 μm.

In addition, the release layer 21 is formed by first attaching a solid release film to the first surface 20a, and then using laser processing to tear off the release film material outside the pre-removed area C, thereby forming The release layer 21 is.

As shown in FIG. 2B, the metal materials 22a, 22b are patterned and etched to form a first inner wiring layer 22 and cover the release layer 21 on the first surface 20a of the board 20 and the release layer 21, respectively. The cladding layer 22' is formed on the second surface 20b to form a second inner wiring layer 23.

As shown in FIG. 2C, a first line build-up structure 24 is formed on the first surface 20a of the board 20, the first inner circuit layer 22 and the cladding layer 22', and on the second surface of the board 20 A second line build-up structure 25 is formed on the second inner circuit layer 23 and 20b.

In this embodiment, the first line build-up structure 24 has at least one dielectric layer 240, a circuit layer 241 disposed on the dielectric layer 240, and a conductive via 242 electrically connected to the circuit layer 241.

Moreover, the conductive blind vias 242 are connected to the first inner wiring layer 22.

Moreover, the second circuit build-up structure 25 has at least one dielectric layer 250, a circuit layer 251 disposed on the dielectric layer 250, and a conductive blind via electrically connecting the circuit layer 251 and the second inner circuit layer 23. 252.

In addition, the circuit layer 251 and the second inner wiring layer 23 are not formed in the dielectric layer 250 corresponding to the pre-removed area C.

As shown in FIGS. 2D to 2E, the release layer 21 and the structure of the pre-removed area C in the direction of the second surface 20b are removed to form the first and second surfaces 20a, 20b and the second. An opening 200 of the line build-up structure 25, and the cover layer 22' is exposed to the opening 200 as an exposed portion 220, and the opening 200 extends to the first line build-up structure 24, so that the exposed portion 220 and the opening As a slot structure 26, an electronic component (not shown) such as a semiconductor wafer is placed, wherein the cladding layer 22' (or the exposed portion 220) is the bottom 260 of the trench structure 26.

In this embodiment, the material between the second surface 20b of the plate body 20 and the release layer 21, the release layer 21 and the plate body 20 are removed by blind routing. The material on the second surface 20b has an accuracy of up to 25 μm. Specifically, the cutting is performed along the edge of the release layer 21 (i.e., along the edge of the pre-removed area C) using a milling cutter.

Furthermore, after the opening 200 is formed, there is a trace of the milling cutter rotating on the exposed portion 220, and the edge of the exposed portion 220 has a channel 221 having a depth d of less than 25 μm.

Moreover, because the method of deep-blind fishing is to control the blind fishing depth by detecting the capacitance between the metal and the probe (not shown), when the blind fishing process is performed, the metal is retained on the bottom surface (ie, the cladding layer 22' The depth of the groove structure 26 can be more precisely controlled with an accuracy of up to 25 μm.

In addition, the surface of the bottom portion 260 (ie, the exposed portion 220 is exposed on the surface of the opening 200) has a height difference T from the first surface 20a. As shown in FIG. 2E, the surface height of the bottom portion 260 is lower than that. The height position of the first surface 20a.

In another embodiment, as shown in FIG. 2E′, after the removal process, the exposed portion 220 exposed to the opening 200 may be removed, so that the dielectric layer 240 of the first line build-up structure 24 is exposed. The opening 200 serves as the bottom portion 260' of the groove structure 26', and the surface of the bottom portion 260 in the opening 200 has a height difference D (D>10 μm) between the surface and the first surface 20a, that is, the bottom portion 260 The surface height position is lower than the height position of the first surface 20a, and the thickness of the dielectric layer 240 is greater than the value of the height difference D.

In the manufacturing method of the present invention, since the release layer 21 is first covered with the metal coating layer 22', when the release layer 21 is removed, the release layer 21 is only in contact with the metal material, so that the release is easily removed. The layer 21 does not damage the wiring layers 241, 251, the first inner wiring layer 22 and the second inner wiring layer 23.

Furthermore, the method of the present invention removes the release layer 21, so that the opening 200 of the present invention has a larger space than the conventional method, thereby facilitating the selectivity of placing electronic components.

The present invention further provides a package substrate 2, 2' comprising: a plate body 20, a first inner circuit layer 22, and a first line build-up structure 24.

The plate body 20 has opposite first and second surfaces 20a and 20b, and an opening 200 communicating with the first and second surfaces 20a and 20b.

The first inner circuit layer 22 is disposed on the first surface 20a of the board body 20.

The first line build-up structure 24 is disposed on the metal layer 22, and the opening 200 extends to the first line build-up structure 24.

In an embodiment, the first inner circuit layer 22 has an exposed portion 220 exposed to the opening 200, so that the exposed portion 220 and the opening 200 serve as the groove structure 26, and the exposed portion 220 serves as the bottom portion of the groove structure 26. 260. Specifically, the exposed portion 220 has a height difference T between the surface of the opening 200 and the first surface 20a, and the edge of the exposed portion 220 has a channel 221, for example, the depth d of the channel 221 Less than 25 μm.

In one embodiment, the first line build-up structure 24 covers one side of the opening 200 to form a groove structure 26', and a portion of the first line build-up structure 24 serves as the bottom portion 260 of the groove structure 26'. ', and the surface of the bottom portion 260' located in the opening 200 has a height difference D from the first surface 20a.

In one embodiment, the package substrate 2, 2' includes a circuit layer disposed on the second surface 20b of the board 20, such as the second inner circuit layer 23.

In one embodiment, the package substrate 2, 2' includes a second line build-up structure 25 disposed on the second surface 20b of the board 20.

In summary, the package substrate of the present invention and the manufacturing method thereof are mainly designed by the cover layer to facilitate removal of the release layer, thereby shortening the process time without damaging the circuit layer and facilitating placement. The selectivity of electronic components.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Package substrate

20‧‧‧ board

20a‧‧‧ first surface

20b‧‧‧second surface

200‧‧‧ openings

22‧‧‧First inner circuit layer

22'‧‧‧Cladding

220‧‧‧Exposed Department

221‧‧‧Channel

23‧‧‧Second inner circuit layer

24‧‧‧First line build-up structure

240, 250‧‧‧ dielectric layer

241,251‧‧‧circuit layer

242,252‧‧‧ conductive blind holes

25‧‧‧Second line build-up structure

26‧‧‧ trough structure

260‧‧‧ bottom

D‧‧‧depth

T‧‧‧ height difference

Claims (1)

[Item 1] A method for manufacturing a package substrate, comprising:
Providing a plate body having an opposite first surface and a second surface, and defining a pre-removal zone on the first surface, the pre-removal zone being formed with a release layer;
Forming a first inner wiring layer on the first surface of the plate body not covered by the release layer, and forming a coating layer covering the release layer on the release layer;
Forming a first line build-up structure on the first inner circuit layer and the cladding layer; and removing the release layer and the structure of the pre-removal area toward the second surface to form a first connection And an opening of the second surface, and the opening extends to the cladding layer to form a groove structure.
[Claim 2] The method of manufacturing a package substrate according to claim 1, wherein the coating layer is exposed to the opening to serve as a bottom portion of the groove structure.
[Claim 3] The method for manufacturing a package substrate according to claim 2, wherein, after the opening is formed, the edge of the bottom portion has a channel.
[Claim 4] The method for manufacturing a package substrate according to claim 1, wherein when the opening is formed, the coating layer exposed to the opening is removed to expose the first line build-up structure At the opening, as the bottom of the groove structure.
[Claim 5] The method for manufacturing a package substrate according to claim 1, wherein the material between the second surface of the plate body and the release layer is removed by blind fishing.
[Claim 6] The method for manufacturing a package substrate according to claim 5, wherein the depth of the blind fishing is 25 μm by the coating layer.
[Claim 7] The method for manufacturing a package substrate according to claim 5, wherein the deep blind fishing method is performed along an edge of the release layer.
[Embodiment 8] The method for manufacturing a package substrate according to claim 1, further comprising forming a circuit layer on the second surface of the board.
[Embodiment 9] The method for manufacturing a package substrate according to claim 1 or 8, further comprising forming a second line build-up structure on the second surface of the board.
[10] The method for manufacturing a package substrate according to claim 9, wherein the method further comprises removing the material between the second surface of the plate and the release layer. The material on the second surface.
[Item 11] A package substrate, comprising:
The plate body has opposite first and second surfaces, and an opening connecting the first and second surfaces;
a first inner circuit layer is disposed on the first surface of the board body, and the first inner circuit layer has an exposed portion exposed to the opening, the edge of the exposed portion has a channel; and the first line is layered The structure is disposed on the first inner circuit layer, and the opening extends to the exposed portion, so that the exposed portion and the opening serve as a groove structure.
[12] The package substrate of claim 11, wherein the channel has a depth of less than 25 μm.
[Claim 13] The package substrate of claim 11, further comprising a circuit layer disposed on the second surface of the board.
[Claim 14] The package substrate according to claim 11 or 13, further comprising a second line build-up structure disposed on the second surface of the board.
[Claim 15] The package substrate of claim 11, wherein the exposed portion has a height difference between a surface exposed to the opening and the first surface.
[Item 16] A package substrate, comprising:
The plate body has opposite first and second surfaces, and an opening connecting the first and second surfaces;
a first inner circuit layer disposed on the first surface of the board; and a first line build-up structure disposed on the first inner circuit layer and covering one side of the opening to make the first line The build-up structure covers a portion of the opening as the bottom of the groove structure and extends the opening to the first line build-up structure to form a groove structure.
[17] The package substrate of claim 16, comprising a circuit layer disposed on the second surface of the board.
[Embodiment 18] The package substrate of claim 16 or 17, further comprising a second line build-up structure disposed on the second surface of the board.
[Claim 19] The package substrate of claim 16, wherein the bottom surface of the bottom portion has a height difference from the first surface.