TW201526186A - 包含銅柱結構之積體電路及其製造方法 - Google Patents

包含銅柱結構之積體電路及其製造方法 Download PDF

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Publication number
TW201526186A
TW201526186A TW103123585A TW103123585A TW201526186A TW 201526186 A TW201526186 A TW 201526186A TW 103123585 A TW103123585 A TW 103123585A TW 103123585 A TW103123585 A TW 103123585A TW 201526186 A TW201526186 A TW 201526186A
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layer
integrated circuit
passivation layer
copper
metal layer
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TW103123585A
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English (en)
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TWI552292B (zh
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Mahesh Anant Bhatkar
Juan Boon Tan
Wei Liu
Jens Oswald
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Globalfoundries Sg Pte Ltd
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/384—Bump effects

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Abstract

本發明公開一種包含銅柱結構之積體電路及其製造方法。於一示例實施例中，積體電路包括最後金屬層以及設置於該最後金屬層上方之鈍化層，該最後金屬層及鈍化層二者係設置於形成於半導體基板上之積體電路主動元件上方。該積體電路進一步包括銅柱結構，其係部分設置於該鈍化層之第一部分內且位於該最後金屬層正上方。該鈍化層之該第一部分係由該鈍化層之第一及第二側壁以及該最後金屬層之上表面所定義。該銅柱結構包括沿著該第一及第二側壁以及該最後金屬層之該上表面上方所形成之襯裡以及該襯裡內之銅材料。包括該襯裡以及該襯裡內之銅材料之銅柱結構進一步延伸至該鈍化層之上表面之上一高度。

Description

包含銅柱結構之積體電路及其製造方法
本發明係關於一種積體電路及其製造方法，詳言之，係關於一種包含銅柱結構之積體電路及其製造方法。
現今大多數之積體電路係透過使用多個相互連接之場效電晶體(FET)來實現，該場效電晶體亦稱之為金屬氧化物半導體場效電晶體(MOSFET)，或簡稱為MOS電晶體。MOS電晶體包括用於作為控制電極之閘極電極，以及電流可於其間流動之相互間隔開之源極及汲極區域。施加於該閘極電極之控制電壓係用於控制通過該源極與汲極區域之間之通道之電流的流動。
當今積體電路係由百萬個主動裝置所組成，例如電晶體、電容器等。這些元件最初係彼此絕緣，但稍後會相互連接於一起以形成功能電路。典型的互連結構包括例如金屬線路(佈線)的橫向互連，以及例如通孔與接觸件之垂直內連。互連件對於當今積體電路的性能限制及密 度的決定作用日益增強。於該互連結構之頂部上，於各個半導體晶圓或“晶片”之表面上形成並暴露出焊墊。透過焊墊形成電性連接以將該晶片連接至封裝基板或另一裸晶(die)。焊墊可用於打線接合或所謂“覆晶(flip-chip)”接合。如習知技術所知，覆晶也被稱為受控坍塌晶片連接(controlled collapse chip connection)或其縮寫C4，係為一種利用沉積於晶片墊片上之焊料凸塊，將諸如積體電路晶片及微機電系統(MEMS)之半導體元件與外部電路互連的方法。在最終晶圓處理步驟期間，該焊料凸塊係沉積於該晶圓之頂側的晶片墊片上。為將晶片安裝至外部電路(例如，電路板或另一晶片或晶圓)，該晶片被翻轉而使其頂側朝下並對齊以使其墊片對準於該外部電路上相匹配之墊片，然後使焊錫流動以完成該互連。此係相對於打線結合，於該打線結合中該晶片係被直立地安裝，且引線係用於將該等晶片互連至外部電路。
在結構上，焊料凸塊實際包括該凸塊本身以及位於該凸塊與墊片之間的所謂凸塊下冶金層(under-bump-metallurgy；UBM)。凸塊下冶金層通常包括依序形成於該墊片上之黏著層、阻障層以及潤濕層。該凸塊本身，依據使用的材料可分為焊料凸塊、金凸塊、銅柱凸塊以及混合金屬凸塊。於銅柱凸塊的技術中，係採用銅柱凸塊(或銅柱)取代焊料凸塊而將電子組件連接至基板，以實現細距化(finer pitch)之功效且短路橋接(bump bridging)之可能性較低，可降低電路之電容負載，並提高電子組件 之操作頻率。
於目前的實踐中，該積體電路在製造廠商或“鑄造廠商”的製造流程係至該墊片以及所需的鈍化層(如可設置在最後的金屬化層上方)為止。此後，該積體電路將由該鑄造廠商送至外包半導體封裝測試(OSAT)廠商，以進行銅柱與該墊片的電性連接製程，並最終連接至該外部電路。然而，在OSAT製造銅柱的處理方式存在著一些缺點。例如，對於一些OSAT廠商而言，以目前正在開發及測試之小間距(例如大約10微米或更小)製造銅柱係非常困難，而這對於鑄造廠而言，早已完備這樣小間距的模具。再者，OSAT廠商無法將銅柱與柱體加固結構(例如為銅線通孔支撐結構)結合在一起，以使該積體電路與該外部電路之間形成更堅固的連接。
因此，希望提供一種改良之積體電路結構以及相對於OSAT，能在半導體鑄造廠製造包含銅柱之積體電路之製造方法。亦希望提供一種適用於10微米以下之間距設計組構之銅柱。此外，還希望提供一種可將銅柱連接至柱體加固結構之技術。再者，由以下的實施方式及所述之申請專利範圍，結合所附之圖式以及前述之發明所屬之技術領域及先前技術，則本發明之其他所希望的特徵和特性將變得清楚。
本發明揭露一種包含銅柱結構之積體電路及其製造方法。於一示例實施例中，積體電路包括最後金屬 層以及設置於該最後金屬層上方之鈍化層，該最後金屬層及鈍化層設置於半導體基板上之積體電路主動元件上方。該積體電路進一步包括銅柱結構，其部分設置於該鈍化層之第一部分內且位於該最後金屬層正上方。該鈍化層之第一部分係由該鈍化層之第一及第二側壁以及該最後金屬層之上表面所定義。該銅柱結構包括沿著該第一及第二側壁以及該最後金屬層之上表面上方所形成之襯裡以及該襯裡內之銅材料。包括襯裡及該襯裡內之銅材料之銅柱結構進一步延伸至該鈍化層之上表面之上一高度。
於另一示例實施例中，積體電路之製造方法包括：提供積體電路，其包括最後金屬層以及設置於該最後金屬層上方之鈍化層，該最後金屬層及鈍化層設置於形成於半導體基板上之積體電路元件上方，並蝕刻該鈍化層以形成第一空隙區域於其中。蝕刻該鈍化層以外露出設置於其下之該最後金屬層之表面，該第一空隙區域係由該鈍化層之側壁以及該最後金屬層之該外露表面所定義。該方法進一步包括於該第一空隙區域內沿著該側壁以及該最後金屬層之該外露表面的上方形成襯裡。該第一空隙區域之未被該襯裡填充之剩餘部分係定義為第二空隙區域，該第二空隙區域係小於該第一空隙區域。再者，該方法包括於該第二空隙區域內形成銅柱，並蝕刻該襯裡周圍之該鈍化層之第一部分以及該銅柱以露出該襯裡之一部分。該鈍化層之至少第二部分係設置於該最後金屬層上方並相鄰於該襯裡以及該銅柱。
39‧‧‧墊片層
43‧‧‧墊片部分
44‧‧‧通孔部分
40、111至114、119‧‧‧鈍化層
107‧‧‧支撐通孔
108‧‧‧銅線通孔支撐結構
109‧‧‧絕緣層
110‧‧‧最後金屬層
115‧‧‧氧化矽層
117、137‧‧‧上表面
120A、120B‧‧‧空隙區域
121、122、125、126、146、147‧‧‧側壁
123、148‧‧‧上表面
124‧‧‧襯裡
127‧‧‧表面
130‧‧‧銅柱
141、142‧‧‧部分
145‧‧‧空間支撐通孔
下文將配合以下圖式詳細描述本發明，其中相同數字表示相同元件。
第1至6圖係根據本發明之各種實施例所示之積體電路結構及其製造方法之剖面圖；以及第7A至7B圖係說明根據本發明揭露之實施例(第7B圖)所形成之積體電路與根據習知技術(第7A圖)所形成之積體電路之間的差異。
本發明之以下實施方式僅為示例且並不意欲限制本發明或本發明之應用及用途。再者，不欲受到本發明前述技術領域、先前技術、摘要或下列實施方式中提出之任何明示或暗示理論之限制。
本揭露提供一種包括銅(Cu)柱結構之積體電路及其製造方法。於本揭露中，術語“銅柱”係指由銅或銅合金所形成之導電柱(柱子或支撐座)。該銅柱可鋪設於覆晶組件之半導體晶片上之最後金屬層上方(此處使用之術語“最後金屬層”係指於該積體電路結構連接至外部電路之前，形成於積體電路結構上之最終金屬化層)或其他相似之應用。為簡潔起見，積體電路裝置製造之相關傳統技術於此將不再詳述。例如，示例實施例係顯示於製造之一階段中的積體電路，其中一個或多個電路元件(例如電晶體、電阻器等)係利用習知技術預先形成。再者，本文所述之多種工作及製程步驟可併入於具有本文未詳細揭示之 其他步驟或功能之更複雜的步驟或製程。特別的，製造以半導體為基礎之電晶體的各步驟已廣泛習知，所以為了簡潔起見，許多傳統步驟將僅簡單說明或全部省略而不提供習知的製程細節。
第1至6圖係顯示本發明之不同實施例之積體電路結構及其製造方法之剖視圖。請參考第1圖，於未圖示之半導體基板上方提供設置於最後金屬層110上方之鈍化層119。該半導體基板係定義成意指包含有半導體材料之任何構造，包括但不限於，塊狀矽、半導體晶圓、絕緣體上覆矽(SOI)基板或矽鍺基板。其他包括第III族、第IV族以及第V族元素的半導體材料亦可使用。該基板進一步包括複數個隔離特徵(未圖示)，例如淺溝槽隔離(STI)特徵或局部矽氧化(LOCOS)特徵。這些隔離特徵係可定義以及隔離各種微電子元件(未圖示)，此處亦稱之為主動積體電路結構。可形成於基板中之各種微電子元件之實例係包括電晶體(例如，金屬氧化物半導體場效應電晶體(MOSFET)、互補金屬氧化物半導體(CMOS)電晶體、雙極型接面電晶體(BJT)、高壓電晶體、高頻電積體，P通道及/或n通道場效應電晶體(PFET/NFET)等)、電阻器、二極體、電容器、電感器、熔斷器、或其他適合的元件。可施行包括沉積、蝕刻、植入、光微影、退火或其他適當製程之各種製程以形成各種微電子元件。該微電子元件透過互連以形成積體電路元件，例如以邏輯元件、記憶元件(如靜態隨機存取記憶體或SRAM)、射頻(RF)元件、輸入/輸出(I/O) 元件、系統單晶片(SoC)元件及上述元件的結合，或其他適當類型之元件。
該半導體基板進一步包括設置於其上方之層間介電質層(未圖示)以及覆於該主動積體電路結構上之金屬化結構，其為最後金屬層110形成之一部分。該金屬化結構中之層間介電質層包括低介電常數介電材料、未摻雜矽酸鹽玻璃(USG)、氮化矽、氮氧化矽或其他常用材料。低k介電材料的介電常數(k值)可低於約3.9或低於約2.8。金屬化結構中之金屬線，例如最後金屬層110，可包括銅或銅合金。本領域之技術人士將會了解該金屬化結構之形成細節。
如上所述，第1圖亦顯示覆於該半導體基板上之鈍化層119，特別是覆於該最後金屬層110上。關於該鈍化層119之目標及功能，由於當今係聚焦於提高電路之密度及速度，故使用銅作為互連材料係具有顯著成效，這是因為相較於鋁，銅係具有較低之電阻率以及對電遷移失效具有較低之敏感性。雖然儘管有這些優點，使用銅的一個缺點係在於在後續處理步驟中，其很容易擴散至周圍之介電質材料中，為抑制銅的擴散，銅互連器通常覆蓋有防護阻障層，其稱為鈍化層。該鈍化層119係由無機材料形成，該無機材料選自於未摻雜矽酸鹽玻璃(USG)、氮化矽、氮氧化矽、氧化矽或其組合。於某些替代實施例中，該鈍化層係由聚合物層形成，諸如環氧樹脂、聚亞硫胺、苯環丁烯(BCB)、聚苯并噁唑(PBO)等，然而也可以用其他 相對柔軟的，通常是有機的介電材料。
於第1圖所示的實施例中，鈍化層119係由五個分層111至115所形成。層111可為含氮之以碳化矽為基礎的鈍化材料層，於一實例中，含氮之碳化矽係由三甲基矽烷源利用化學氣相沉積法沉積而成，其可在商業上得自於應用材料公司商品名為BLOK®者，用於作為層119，並且係利用鑲嵌製程形成而設置於銅最後金屬層110上方之分層。低氮(N)(少於大約5mol%)化合物(例如SiaCbNcHd)係稱為“BLOK”，而高氮(大約10至25mol%)化合物(如SiwCxNyHz)係稱為“NBLOK”。BLOK具有小於4.0之較低的介電常數，而NBLOK具有約5.0之介電常數。雖然BLOK不是好的氧阻障層(oxygen barrier)卻是好的銅阻障層(Cu barrier)，NBLOK則同時是好的氧阻障層以及銅阻障層。於一實施例中，該層111包括NBLOK材料。
層112-115可於氮化矽及氧化矽之間交替以形成完整的鈍化層119。例如，如第1圖所示，層112可為氮化矽層，層113可為氧化矽層，層114可為另一氮化矽層，以及層115可為另一氧化矽層。當然，所提供之各層亦可以不同之順序或層數所形成，均屬於本發明之揭露範疇。鈍化層119之厚度，也就是從最後金屬層110之邊緣至上表面的定義範圍，可大約為1微米至約10微米，例如自大約3微米至大約8微米，然上述揭露內容並未用於限定任何鈍化層之厚度。
請參考第2圖，繼續形成一層或多層的遮罩材料(例如光阻材料)，覆於該鈍化層119上，以及於該遮罩材料中形成開口以外露出該鈍化層之一部分。根據一實施例，該遮罩材料係以均勻沉積的方式或其他鋪設方法覆於該鈍化層上，並可透過使用傳統光微影製程步驟以形成包括該開口之蝕刻遮罩以進行圖案化。該遮罩材料可包含一個或多個材料層。例如，於一替代實施例中，該遮罩材料可實現為三層遮罩，其包括位於硬遮罩材料層(例如碳硬遮罩層等)下方之抗反射氮氧化矽層，於該硬遮罩材料層上覆蓋有光阻材料。接著，移除該鈍化層中對應該開口下方之部分以於該鈍化層119中形成第一空隙區域120A。移除該鈍化層119中之該部分以形成該第一空隙區域120A可透過使用合適的蝕刻製程來完成，例如基於電漿之反應性電漿蝕刻法(RIE)使用非等向性蝕刻劑，並藉由施加偏壓電壓以非等向性蝕刻該鈍化層119，從而露出位於下方之最後金屬層110之上表面123。該第一空隙區域120A可定義為由該鈍化層119之側壁121、122以及該最後金屬層110之上表面123所形成。該空隙區域120A可具有與前述該鈍化層之厚度實質上相同之深度(係定義為自鈍化層上表面117至最後金屬層上表面123之間的距離)。該空隙區域120A可具有與對應深度值大約為1：1至約1：2之比例之寬度(係定義為該側壁121、122之間的距離)。惟，應了解到上述揭露內容並非用於限定該空隙區域120A為任何特定尺寸。進行蝕刻之後，該遮罩材料係透過使用習知技術移除 而留下實質上如第2圖所示之結構。
現參考第3圖所示之實施例，阻障材料層或“襯裡”124係透過沉積具有阻障特性(相對於銅擴散)材料之分層所形成，例如為氮化鈦(TiN)、氮化鉭(TaN)(或可能為Ti或Ta金屬)，或於習知技術領域中所了解之用於物理氣相沉積(PVD)、濺鍍等製程之其他材料。該襯裡124可具有大約1nm至約50nm之厚度，但通常任何適合之厚度皆可使用。該襯裡124係用於阻止隨後形成之銅柱(請參閱第4圖)擴散至周圍之鈍化層119中。該襯裡最初係沉積於整個基板上方，然而，後續之蝕刻及研磨步驟會將該襯裡124自該鈍化層119之上表面117從上方移除，僅留下形成於空隙120A(參閱第4圖)內之部分。藉由所沉積之襯裡124，該空隙區域120A之尺寸略有減少，而在第3圖中作為空隙區域120B。空隙區域120B具有由該阻障襯裡材料所形成之側壁125、126，以及具有由該阻障襯裡材料所形成之下表面127。
現參考第4圖所示，係說明銅柱130之形成。(此處所使用之術語“銅柱”僅指下述第4圖中所示之銅元件130，術語“銅柱機構”則指結合有阻障襯裡124之銅柱130。為形成該銅柱130，係形成晶種層(未獨立圖示)，該晶種層係藉由物理氣相沉積(PVD)或濺鍍製程並由銅或銅合金所形成，以提供起始層，於其上方係形成有藉由後續之電鍍製程所形成之銅柱130。該晶種層可沉積至例如大約500至10,000埃之厚度。於該晶種層沉積之後，執行 電化壆電鍍(ECP)製程以形成該銅柱130。或者，可使用其他沉積製程，例如無電電鍍、濺鍍、CVD或其他製程。形成該銅柱130以完全填充該空隙120B。於一些實施例中，為確保完全填充，可於該鈍化層119之該上表面117上方形成過量的銅。
現參閱第5圖，任何用於形成該銅柱130而電鍍之過量的銅可利用諸如化學機械平坦化或研磨(CMP)之方式移除。該鈍化層119以及該銅柱130之高度有些係由於該CMP製程而降低，如第5圖所示。如技術領域中所習知的，該CMP製程係使用具有研磨性和腐蝕性之化學漿，並配合使用拋光墊及支撐環，通常直徑係大於該晶圓。該拋光墊及晶圓係藉由動力拋光頭被壓在一起，並藉由塑料支撐環而保持位置。該動力拋光頭係依據不同之轉軸而轉動(例如並非同心)。典型之CMP工具係包括旋轉部以及被墊片覆蓋之極平坦之壓板。該正被拋光之晶圓係被倒置安裝於背膜上之載體/轉軸中。該支撐環用於保持該晶圓位於正確之水平位置。漿料引入機構將該漿料沉積於該墊片上。然後，該壓板及該載體兩者將進行旋轉，且該載體係同時保持震盪。向下壓力/向下作用力係施加於該載體，以將其壓抵該墊片。所施加之向下作用力係取決於接觸面積，而該接觸面積係取決於該晶圓以及該墊片兩者之結構。可執行該CMP製程，使得除了該空隙區域120B內之外位於其他各處的銅均被移除，因此留下與該空隙區域120B之尺寸實質相稱之銅柱130。因此，該銅柱係具有上 表面137，其與該鈍化層119或上表面117共平面。此後，該示例結構可暴露於適合之退火製程以對該銅柱130進行退火。於該退火製程中，該積體電路被暴露於高溫持續任何合適之退火時間。上述揭露並非意圖受到任何特別的銅退火條件的限制。於退火後，形成實質上如第5圖所示之結構。
現參考第6圖，本實施例方法繼續執行一蝕刻步驟以蝕刻該鈍化層119之至少一部分141。如第6圖所示，該鈍化層中所被蝕刻之該部分141係包括上方之氧化矽層115。在這方面，採用適合之蝕刻製程，例如無需遮罩層(masking layer)之包覆式氧化物乾(RIE)蝕刻法(a blanket oxide dry etch)(對於氧化物有選擇性之蝕刻化學)。於此蝕刻製程之後，上方之氮化矽層114成為該鈍化層之上層，並具有上表面148。因此，當該鈍化層119之一部分141藉由該蝕刻製程被移除時，該鈍化層之另一部分142，包括層111至114，仍維持於原位。相鄰於該銅柱結構(襯裡124及柱體130)之空隙空間係如第6圖所示之空間145。因此，於該蝕刻製程之後，該銅柱結構係具有由阻障襯裡124形成之暴露側壁146、147。如第6圖所示，由此而產生之結構係具有該銅柱結構中位於該鈍化層119之剩餘部分142內之第一部分，以及該銅柱結構中位於該鈍化層119之剩餘部分142之上表面148之上之第二部分。於一些實施例中，該第一部分與第二部分之間的比例可為自大約0.5：1至大約2：1的範圍。
據此，已揭露一種製造積體電路之方法，該方法係適用於在半導體鑄造廠(相對於前述之OSAT)執行。第7A及7B圖係說明根據本發明揭露之實施例(第7B圖)所形成之積體電路與根據習知技術(第7A圖)所形成之積體電路之間的差異。如上所述，如第7B圖所示，根據本發明實施例所製造之積體電路係包括最後金屬層110以及設置於該最後金屬層上方之鈍化層142，該最後金屬層110及鈍化層142二者皆係設置於半導體基板上之積體電路主動元件上方，該半導體基板上係形成有一個或多個絕緣層109(例如氟化之TEOS)。該積體電路進一步包括部分設置於該鈍化層142之第一部分內且在該最後金屬層110正上方的銅柱結構124、130。該鈍化層之第一部分係由該鈍化層之第一及第二側壁121、122以及該最後金屬層之上表面127定義而成。該銅柱結構124、130包括沿著該第一及第二側壁121、122以及該最後金屬層之上表面127上方所形成之襯裡124，以及該襯裡124內所形成之銅材料(或銅柱)130。包括襯裡124及該襯裡內之銅材料(或銅柱)130二者之銅柱結構進一步延伸至該鈍化層之上表面148之上一高度。
根據前述實施例之於鑄造廠內形成銅柱結構之另一優點係在於，可形成由下層支撐結構所支撐之銅柱結構，該下層支撐結構係例如銅線通孔支撐(CVLS)結構108，如第7B圖所示。CVLS 108包括具有複數個支撐通孔107之基底金屬層108(由例如銅形成)，該複數個支撐通孔 107連接於該基底金屬層108以及該最後金屬層110之間。由於該銅柱結構係連接至該最後金屬層110，所以額外之結構支撐係透過該CVLS 108予以提供。該額外之結構支撐係用於減少缺陷並提高製程之穩定性。再者，第7B圖所示之銅柱結構在鑄造廠進行製造時，可被製成約10微米或以下之間距，從而可於更小之晶片面積上包含更多的積體電路特徵。
第7B圖所示之結構，係相對於第7A圖所示之習知積體電路製造方法所製成之積體電路。於習知技術結構中，該積體電路可包括墊片層39(例如鋁墊片層)，其連接於該最後金屬層110以及該銅柱130之間。該墊片層39包括墊片部分43以及通孔部分44(請參考所形成之鈍化層40、114中的“草皮剖面”)。該鈍化層111至114(及氧化矽層40)係如上所述設置。該第7A圖所示之結構復包括前述之焊料材料41。於此組構中，該銅柱130與最後金屬層110之間可以沒有支撐。再者，若在OSAT中生產，該銅柱130將無法達到例如約10微米或以下之細小間距。
雖然前述之詳細說明已提出至少一個示例實施例，但應了解到仍存在有大量的變化例。示例實施例僅為例子，不應理解為以任何形式對本發明申請專利範圍、應用領域及形狀構造之限制，前述概要以及實施方式於一定程度上係為本領域技術人員提供了一個方便實現例示性實施例的指南，即在不超出所附之申請專利範圍所保護之範圍及其法律效果之前提下，例示性實施例中所述之 功能與元件之配置均可作不同之變化。
110‧‧‧最後金屬層
111至114‧‧‧鈍化層
124‧‧‧襯裡
130‧‧‧銅柱
137‧‧‧上表面
141、142‧‧‧部分
145‧‧‧空間支撐通孔
146、147‧‧‧側壁
148‧‧‧上表面

Claims (19)

  1. 一種積體電路，係包括：最後金屬層以及設置於該最後金屬層上方之鈍化層，該最後金屬層以及該鈍化層二者係設置於半導體基板上之積體電路主動元件上方；銅柱結構，係部分設置於該鈍化層之第一部分內且位於該最後金屬層正上方，其中，該鈍化層之該第一部分係由該鈍化層之第一和第二側壁以及該最後金屬層之上表面所定義，以及其中，該銅柱結構包含沿著該第一及第二側壁以及該最後金屬層之該上表面上方所形成之襯裡以及該襯裡內之銅材料，其中，包含該襯裡以及該襯裡內之該銅材料二者之該銅柱結構係進一步延伸至該鈍化層之上表面之上的一高度。
  2. 如申請專利範圍第1項所述之積體電路，其中，該鈍化層包括複合材料鈍化層。
  3. 如申請專利範圍第2項所述之積體電路，其中，該鈍化層包括以碳化矽為基礎之材料層、第一氮化矽材料層、氧化矽材料層以及第二氮化矽材料層。
  4. 如申請專利範圍第1項所述之積體電路，其中，該襯裡包含TiN材料。
  5. 如申請專利範圍第1項所述之積體電路，其中，該銅柱結構形成於約10微米及以下之間距。
  6. 如申請專利範圍第1項所述之積體電路，其中，該最後 金屬層包含銅材料。
  7. 如申請專利範圍第1項所述之積體電路，進一步包括與該最後金屬層連接之銅柱支撐結構。
  8. 如申請專利範圍第7項所述之積體電路，其中，該銅柱支撐結構包括銅線通孔支撐結構，包括連接至該最後金屬層之複數個通孔支撐部以及下方基底金屬層。
  9. 如申請專利範圍第1項所述之積體電路，其中，該銅柱結構具有約1微米至約10微米之高度。
  10. 如申請專利範圍第1項所述之積體電路，其中，該銅柱結構具有約3微米至約8微米之高度。
  11. 一種製造積體電路之方法，包括：提供積體電路，係包括最後金屬層以及設置於該最後金屬層上方之鈍化層，該最後金屬層以及該鈍化層二者係設置於形成於半導體基板上方之積體電路元件上方；蝕刻該鈍化層以形成第一空隙區域於其中，其中，蝕刻該鈍化層外露出設於其下之該最後金屬層的表面，該第一空隙區域係由該鈍化層之側壁以及該最後金屬層之該外露表面所定義；於該第一空隙區域內沿著該側壁以及該最後金屬層之該外露表面上方形成襯裡，其中，該第一空隙區域中未由該襯裡所填充之剩餘部分係定義為第二空隙區域，該第二空隙區域係小於該第一空隙區域；於該第二空隙區域內形成銅柱；以及 蝕刻該襯裡周圍之該鈍化層之第一部分以及該銅柱，以外露出該襯裡之一部分，其中，該鈍化層之至少第二部分係留存設置於該最後金屬層上方並相鄰於該襯裡以及該銅柱。
  12. 如申請專利範圍第11項所述之方法，其中，提供含有該最後金屬層之該積體電路包括提供一種積體電路，係包括含有銅材料之最後金屬層。
  13. 如申請專利範圍第11項所述之方法，其中，提供含有該鈍化層之該積體電路包括提供含有多層鈍化層之積體電路。
  14. 如申請專利範圍第13項所述之方法，其中，提供含有該多層鈍化層之該積體電路包括提供含有鈍化層之積體電路，該鈍化層包括以碳化矽為基礎之層、第一氮化矽層、第一氧化矽層、第二氮化矽層以及第二氧化矽層。
  15. 如申請專利範圍第14項所述之方法，其中，蝕刻該鈍化層之該第一部分包括利用包覆式氧化物乾蝕刻製程蝕刻該第二氧化矽層。
  16. 如申請專利範圍第14項所述之方法，其中，蝕刻以留下餘存之該鈍化層之第二部分包括留下餘存之該以碳化矽為基礎之層、該第一氮化矽層、該第一氧化矽層以及該第二氮化矽層。
  17. 如申請專利範圍第11項所述之方法，其中，形成該襯裡包括形成TiN襯裡。
  18. 如申請專利範圍第11項所述之方法，其中，於該第二 空隙區域內形成該銅柱包括於該第二空隙區域內形成晶種層。
  19. 如申請專利範圍第18項所述之方法，其中，於該第二空隙區域內形成該銅柱進一步包括於該晶種層上方電鍍銅材料，藉以填充該第二空隙區域。
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