TW512502B - Method for forming a wafer level chip scale package, and package formed thereby - Google Patents

Abstract

A layer of gold (405) is disposed on upper surfaces (225) of copper pillars (210) on a bumped wafer (205). Coating material (410) is then applied to a level which is less than the height of the copper pillars (210), and etchant is disposed to remove coating material on the layer of gold (405) and to remove coating material (410) adhering to side surfaces of the copper pillars (210). Solder deposits are then disposed on the gold layer and reflowed to form balls (405) on the ends of the copper pillars (210), with the copper pillars (210) protruding into the solder balls (405).

Description

V. Description of the invention (1) [Field of the invention] The present invention relates to the formation of wafer-level wafers. More specifically, the method of forming wafer-level wafer-scale seals: packaging methods, and grinding and spreading methods can avoid machinery. [Background of the Invention] The requirements for tiny semiconductor packages are for semiconductor integrated circuit or die packaging, round-level process wafers, A-level package packaging, etc. The resulting package is a t ”-scale package (WL-CSP). The wafer-level wafer of the month refers to Figures 1 and 2A-E. Now it is described in a manufacturing process of ㊂nchu ^. In order to understand this technology, the H-level wafer ruler J seal Jiang Jiii pulls the rain. … The process 100 understood by the literary artists is made from 105ρ1, and pads on the wafer 205, and packaged. Wide: Provide 110 wafers 2 ° 5 to form metal grain columns 210. Figure 2_ shows the wafer m to Metal particle pillars_Cheng Zai = Flanders, Francisca Tung in 2000, M = Wu 2 Li, serial number is 5 64382, and the name is for semiconductor wafers. Method of manufacture " and part continuous from Francesca Sch. Don 2 2 0 0 0 0 The United States filed a sequential wafer to improve the particle column connection and manufacturing method, and this book 1; Γ = specified ... This teaches that it has at least some particle columns of two structures, and some patents are incorporated for reference in this case. Material 215, such as molding compound, encapsulated cyclic grease, such as underfill coating material, or photo-imaging material, such as benzocyclobutene

Page 5 512502 V. Description of the invention (2) ~ `` U BCB) or polyimine, is applied 115 on the wafer 205, and the metal particle column 21 is covered with the coating material 21 5 'as shown in FIG. 2B The coating material layer 215 is applied in a spin coating process; typically, the two layers of coating material are each coated with a thickness of about 40-50 micrometers (um) so that the thickness of the coating material is about 100. um, the thickness of the coating material in the gold molecule layer 210 should not be greater than the thickness of i0um, and the coating material layer 215 is then aged. V S / After heating ’, the excess coating material on the copper metal particle column 210 is utilized 丨-mechanical grinder (by Okamoto e Co., Ltd. in the United States or

(Made by Kemet International Co., Ltd.) and use a porous polishing pad to remove the abrasive 12 0. The polishing 12 0 continues until the excess coating material is removed ... and the upper surface 22 of the copper metal particle column 210 is exposed. The polished wafer is shown in Figure 2C. On the upper surface 2 2 0 is formed a 1 2 5 second layer of gold molecules 2 2 5. For example, an electric ore method can be used as shown in FIG. 2D, and the solder ball 23 0 is connected 130 to the gold molecular layer 225 ′. Vendors include οκΐ, Casio, Fujitsu, which are all made in Japan and can be used for solder ball connection. The wafer-level wafer packaging process 1 00 will then end 1 3 5 'After the process 1 100, there are already raised wafers 2 3 5 and then do wafer-level daily-to-day-scale package singulation (si ngu 1 at e) 〇 During the grinding phase 1 2 〇, this wafer 2 0 5 will be subjected to extreme mechanical pressure 'so the wafer It will cause micro-cracks; therefore, the process of mechanical grinding and wafer-level wafer-scale packaging will potentially have a negative impact on reliability due to micro-cracks. Another disadvantage of mechanical grinding is that the grinding is too slow. The factor is the need to invest in grinding equipment, which is accompanied by the supply of grinding consumables. i

Page 6 M2502 V. Description of the invention! The etching has been removed and has phase 丨 removed, so that 丨 is adhered to the i-sheet scale 丨 molecular surface i | rotation 丨 to make;% coating transfer coating is still [ The invention of this invention poses a problem. According to this grade wafer ruler (a) provides a pad body (b) on gold (c) on the surface of the half edge material layer, and (3) Ί is another method instead of grinding, in which an etchant is applied to etch more The coating material layer 2 1 5 is, however, the etching is still a slow process. 2 A large amount of the coating material layer 21 5 must be further compounded to obtain the remaining process, which is more difficult. ; Only the upper surface of the gold molecular layer is exposed, so the solder ball 230 can be I. The area of the gold molecular layer is limited; therefore, another disadvantage of the reliability of the wafer-level crystal packaging is that the solder ball can adhere to the gold · Product is limited. · The coating process is too slow. In addition, two coating layers with the thickness required by the spin coating operation are required. In addition, about φ material waste is attached to the wafer in this spin coating process; therefore, One disadvantage of using spins is both blame and slowness. Brief summary] Ming seeks a way to package wafer-level wafer-scale packages into packages, which can overcome and at least reduce the number of conventional methods mentioned above. Π provides a package of semiconductors of 60% degree, This method includes the steps of: a semiconductor wafer having a plurality of layers of pad body surface, a metal conductor extending away from the surface of the first predetermined free end of the body is formed-a layer of conductive anti-isolation, the surface of the conductor wafer Cloth discharge insulation stand, with-" Conductor wafer surface to the second predetermined distance :: the first predetermined distance in the sexual insulation is less than the first predetermined distance * exposure% existence 12502 V. Description of the invention (4) \ The edge material is placed on the conductive anti-etching material layer, and there are at least some metallic conductors on the side surface; | 丨 (d) placed on the conductive anti-etching material layer and some metals on the side All the electrically insulating material portions on the semiconductor body ij are etched away. In another concept, the present invention provides a wafer-level wafer-scale seal. The package includes: '| A semiconductor die whose surface has Several layers of mats; metal conductors that are coupled and extend a first predetermined distance from a plurality of mats; an anti-etching layer at the free end of the metal conductor; 丨 an insulating layer on the surface, the insulating layer has a predetermined distance from the surface The exposed surface of the distance f, wherein the second predetermined distance is smaller than the first predetermined distance; and the reflowable material is attached to the anti-etching layer and at least part of the side surface 1 is substantially a metallic conductive body. [Brief description of the diagram] 丨 The specific embodiments of the present invention will be described in detail with reference to the drawings; 丨 FIG. 1 shows a detailed process flow chart of forming a wafer-level wafer-scale package according to conventional techniques; Section 2A- Figure E shows a cross-sectional side view of a wafer-level wafer-scale package formed according to the process of FIG. 1; Figure 3 shows a detailed process flow chart of a wafer-level wafer-scale package formed according to the present invention; Figures 4A-E show the cross-sectional side view of the package at the wafer-level wafer scale formed in accordance with the process of Figure 3; Figures 5-7 show the portion of the wafer-level wafer-scale package formation shown in Figure 4C-E

Page 8 ^ 12502 丨 V. Description of the invention (5) ~ 1 I enlarged cross-section side view; 丨 I Figure 8 shows that the film can be placed on the bulk wafer that can be seen as the promotion part of the process in Figure 3 Cross section side view. '| 丨 [Detailed description of the diagram] | On the wafer, a gold molecular layer is placed on the upper surface of the steel particle column, and the coating material is then pressed at a relatively low position of the copper particle column by an extrusion process. i is coated on the wafer so that the copper grain pillars protrude through the upper surface of the coating material and is etched ^ μ i is used to remove the coating material on the upper part of the gold molecular layer and the side surface of the copper grain pillars that are attached to the protrusion This part is coated with material; then the solder joint is placed on the gold molecular layer on the copper particle I i column, and this combination is reflowed; this solder joint is placed on the copper ... A sphere is formed on the molecular layer, and the copper particles pillars protrude into the solder balls; therefore, the 'solder balls are attached to the gold molecular layer, in addition, the solder balls can also be very favorably attached to the side surfaces of the copper particle pillars. 3 and 4A-E, a process 300 for forming a wafer-level wafer-scale package according to the present invention, starting from 30 5 to provide 310—semiconductor wafer 2 0 5 ′ on the wafer 2 0 5 with copper grain columns 2 1 0 Stretched from the grain 塾 2 1 2 As shown in Figure 4 A 'As mentioned before, Francisca Tung applied for a US patent on April 27, 2000. The serial number is 09/564382, and the name is for the semiconductor wafer to improve the particle column connection and manufacturing method, and part of it has been applied to the United States from April 26, 2000 by Franciscan Tang, serial number (so far (Unspecified), with the name 'for semiconductor wafers to improve the connection and manufacturing method of pellets, and "and this patent statement is also the co-designator of it" here to teach it at least some descriptions of the structure of a pellet, these patents are incorporated For reference in this case. I A gold molecular layer 40 5 is formed on the upper surface 22 5 of the copper particle column 210.

Page 9 512502 I. Description of the invention (6) --- 315, and the gold molecular layer is formed on the nickel molecular layer, and the nickel molecular layer can form a kind of barrier to prevent the gold molecules from penetrating into the copper molecules, during the etching process The gold knife layer with the knife is removed and / or gold molecules diffuse into the copper particle column 21, and the remaining copper particle column 210 is exposed. When the nickel molecular layer is used, the reference 405 in the figure indicates the anti-etching conductive layer composed of two layers of gold molecules and nickel molecules. Leng De: Figure '320 is applied to the semiconductor wafer 205 to form a fluid material = to form a coating 410, which has a height of 210 ° relative to the copper particle pillars, and therefore has a copper particle pillar 210 with a gold molecular layer 405 Convex dagger! 410; · Ideally, the coating material layer 41〇 is smaller than: um using an extrusion process to form the coating material layer 4 1〇, which can be achieved by Microelectronics (MicrOE) equipment of FAS technology in Dallas; The material is APS; it is called epoxy resin with round bottom coating (Qing), E'Xter S) epoxy coating or any light imaging coating material 2, using Micr〇W pressure coating equipment and Aps Wcu epoxy, this setting t set Λ includes a POH rate of 115 microliters (ul) per second, a shuttle speed of 2. ^ _), a coating thickness of 125 microns (um), the gap of the extrusion head is 0. 2mm; 80 ~ 90% of the coating material is distributed to form a coating layer 410 ′ using an extrusion coating process, and a single distribution can produce a coating layer 410 that meets the desired thickness; in addition, this extrusion coating The cloth process can be distributed with a tolerance that meets the needs of the jump. Extrusion coating is generally applied on the control panel display. Therefore, as described in the present invention, compared with spin coating, it can facilitate the rapid formation of a coating material layer on a semiconductor wafer with less waste, which can be achieved by a single application.

Page 10 M2502 V. Description of the invention (7), ~-thickness required for formation. The coating layer 410 can also be made using a conventional spin coating process, and the spin coating process must be controlled to obtain a coating layer 41 0 having a predetermined thickness; for example, the coating material is distributed in a semiconductor The amount on wafer 205, the type of coating material used v the speed of semiconductor wafer 205 during rotation, etc. can be selected to produce a coating material layer 410 having a desired thickness;- The embodiment is a spin coater manufactured by SITE in the United States. It applies a BCB coating or a polyimide or epoxy coating material. The spin coater sets the I parameter to include a first coating speed of 30 seconds and 30 seconds. , [800 second rotation of the second coating: a speed of 20 seconds, the thickness of the coating material layer applied is 30-40 um. Another method of forming the cloth layer 410 is to use a die-casting process related to a Teflon film similar to that taught in US Patent No. 5,891,384, Apic Yamada Co., Ltd., which is incorporated herein by reference. After the coating material layer 4 10 is applied, the semiconductor wafer is heated in a nitrogen (N2) environment at a temperature of 350 ° C for 45 to 60 minutes to heat the coating material layer 4 1 0, usually A stove with a controllable nitrogen chamber is used for curing. FIG. 5 shows an enlarged cross-sectional perspective view of a copper particle column having a gold molecular layer 4 0 5 after a coating material layer 4 10 has been formed, and a portion 5 05 is a mature coating material layer 410 attached to The surface 510 on the gold molecular layer 40 5, and part 5 1 5 is a cured coating material layer 4 1 0 adhered to the side surface 5 2 0 of the copper particle column 2 1 0. Subsequently, an etchant is applied to the coating surface of the semiconductor wafer, which is etched to remove the cured coating material layer 410 attached to the gold molecular layer 405.

Page 11 512502: V. Description of the invention (8) '] Part 5 5 of the surface 5 1 0 and the cured coating material layer 4 1 〇 attached to: the side surface of the copper particles 2 1 0 5 2 Part 5 1 5 of 0; Figure 4D shows the semiconductor wafer after etching, and Figure 6 shows an enlarged cross-sectional perspective view of a copper particle column 2 1 0 with one of the gold molecular layers, removing the cured coating material layer 504. A portion of 505 attached to the surface of the gold molecular layer 405 and a portion of 515 attached to the side surface of the copper particle column 205. When the plasma is used for the rest of the time, the electricity composition containing the 5% CF4, 90% 02, and 5% is used to set the electricity of the coin-cutting agent gas, and the power is set to 4,000 watts for 15 minutes for the rest of the time. The present invention can advantageously form a removal area with a relatively small portion of the coating material, so that etching can be used instead of directly using mechanical grinding. Referring to FIG. 4E, after etching 33 0, the solder particles are placed on the copper particles | pillar 210, reflow soldering 345, and the solder is melted to form a solder ball 415 connecting 335 to the copper particle pillar 210. And ended 355. Figure 7 shows an enlarged cross-sectional perspective view of one of the solder balls & 5 attached to the steel grain column 210 after reflow, a copper particle column with a gold molecular layer 4.05 and 2 10 protruding into the solder ball 41 5; In addition, the solder ball 415 is attached to the side surface 5 2 0 of the copper particle column 21 0. According to the invention, as described above, the solder joint can be advantageously allowed to be attached to the side surfaces of the gold molecular layer and the steel particle column, so that the electrical connection with stronger mechanical strength and reliability should be connected. ^ Refer to Figure 8 'To promote the efficiency of the etching process, an additional cleaning step can be used during the etching process. After the semiconductor wafer 205 is applied with a 32 ° gravel 7 material 410, Before the coating material 41 is matured, the Teflon film 05 is placed on the semiconductor wafer 2 and the Teflon is directed toward the semiconductor wafer 2

Page 12 512502 I V. Description of the invention (9) ~ i-i Long film applies pressure, then removes the Teflon film 805, and removes the uncured portion 505 of the coating material | After that, Leaving less mature portions 505 and | 515, these coating materials must be removed by an etching process 33.丨 Teflon film is a mold release film that is commonly used in mold casting. When mold casting is used, i | use a layer of coating release film. This release film can prevent the shank casting during the mold casting process. The compound adheres to the surface 510 of the gold molecular layer 405 and the-side surface 5 2 0 of the copper particle column 210.丨. I!! I " The embodiment that can assist the cleaning of the uncured part of the coating material is to use the US 3M release film, which can be applied manually. Alternatively, the laser cleaning method can be applied to remove the gold molecular layer 405. | The uncured part of the coating material is removed. The laser cleaning method is known to those skilled in the art and is known by the Singapore Automation Promotion System The laser cleaning equipment manufactured by (ASA) Co., Ltd. can be used in this embodiment. Therefore, as described in the present invention, semiconductor wafers do not need to be mechanically polished for manufacturing wafer-level wafer-scale packages; in addition, the connection between copper pellets and solder balls is more reliable. The foot is achieved by forming an f-etch-resistant conductive layer on the bumps of the semiconductor wafer. The bumps extend on the circle where the coating material is deposited and penetrate through the coating material layer. Then, the top i portion of the protrusion and the portion of the coating material layer on the side are etched away, and the solder ball is placed on the exposed portion of the protrusion. Therefore, the present invention provides a method for forming a wafer-level wafer-scale dream seal and a package formed by the method, which can at least overcome the problems known or known. State l

Page 13 512502 i V. Description of the Invention (I) It is commendable that although the present invention is only described in detail with a special embodiment, it can still make various modifications and improvements to those skilled in the art without departing from the spirit of the present invention .

Claims (1)

Patent application scope The second method used to form a wafer-level wafer-scale seal is to include the following steps: Develop the method 'this method (b (c)),-a semiconductor wafer has a plurality of pads with a metal guide The surface of the mat body, in which the mother is separated.-The free end of the first predetermined distance f metal conductor receding from the surface forms a layer of conductive anti-etching material. The electrical discharge is distributed on the surface of the semiconductor wafer. ^ Ba Zhuocai Village, in which the electrical insulation layer has an exposed surface from the semiconductor wafer, where the first pre-distance from the pre-distance from -π to π3w is less than the first The w-age in a box: And the electrical insulation material department Bagu Youlu Lu Lu, Yuan Li's trowel is placed on the layer of conductive anti-etching material and there are at least some metallic conductors on the side surface. The remaining material layer and all the electrically insulating material portions on some metallic conductors on the side are etched away. As one method described in the first patent application scope, one step is:% ^ 3) Lay the reflowable material on the metal conductor at the free end. Etch layer. ) This semiconductor wafer is reflow-soldered so that the reflow material is adhered to the side surfaces of the conductive anti-etch-off layer and the portion of the metallic conductor. The method according to item 1 of the scope of patent application, wherein step (b) comprises depositing a conductive anti-etching material on the free end of the metallic conductor. The method as described in claim 3, wherein step (b) includes a step of depositing gold molecules. The method as described in item 3 of the scope of patent application, wherein step (b) includes)) (d) 2.e (f 3.4. Page 16 512502 6. Scope of patent application Deposition of nickel molecular layer, and then deposit gold molecular layer on nickel molecular layer. 6. The method according to item 1 of the scope of patent application, wherein step (b) comprises plating an anti-etching material on the free end of the metallic conductor. 7. The method according to item 1 of the scope of patent application, wherein step (c) comprises a step of applying a discharge insulating process to the discharge insulating material. 8. The method as described in item 1 of the patent application scope, wherein step (c) includes a single deployment step. 9. The method according to item 1 of the scope of patent application, wherein step (c) includes a step of spin-coating an electrically insulating material layer on a surface of a semiconductor wafer. I 0. The method according to item 9 of the scope of patent application, wherein step (c) comprises a spin-coating step of one material selected from the group consisting of an underfill coating material and a photo-imaging developing material. II. The method according to item 1 of the scope of patent application, wherein step (c) includes a step of molding an electrically insulating material layer on the surface of the semiconductor wafer using a release film. 1 2. The method according to item 1 of the scope of patent application, wherein step (d) comprises a plasma etching step. 1 3 The method according to item 1 of the scope of the patent application, wherein step (e) includes a step of printing and depositing solder joints. 14. The method according to item 1 of the scope of patent application, further comprising the step of curing the electrical insulating material after step (c) and before step (d). 15 · The method as described in item 14 of the scope of patent application, in step (c) 512502 VI. After applying for the patent scope and maturity: Before the step of insulating insulation material, the cleaning cloth is placed on the conductive anti-etching material layer of the part of the wire insulation holding material. The steps include: Applying force: On the release film on the conductive anti-etching material layer; and removing the release film 17. The method described in item 15 of the "patent dry enclosure", wherein the cleaning step includes a laser cleaning step. 1 8 · — wafer A chip-scale package, comprising: a semiconductor die surface having a plurality of pads; a metal conductor extending a first predetermined distance from the plurality of carcasses; an anti-etching layer on a free end of the metal conductor; a surface There is an insulating layer thereon, the insulating layer has an exposed surface and a second predetermined distance from the surface, wherein the second predetermined distance is less than the first predetermined distance; and the reflow soldering material is attached to the side surface of the anti-etching layer and all metallic conductors. 1 9 · While applying for a wafer-level wafer-scale package with a scope of patent No.8, where the metallic conductor contains a copper conductor. "Wafer-level package" where the copper conductor contains a laminated copper plate layer. 2 1 ・ Wafer-level wafer-level package with a patent scope of item 8 "where the anti-etch layer contains a molecular layer of gold. 2 2. 堑 Application Wafer-level wafer-scale package of item 18 of the patent scope, wherein the anti-etching layer includes a nickel molecular layer containing gold molecule layer. 23. No. 22 of the patent application scope of the wafer-level wafer-scale package Page 18 512502 VI. Scope of patent application, in which the thickness of the gold molecular layer is smaller than the value between the first predetermined distance and the second predetermined distance. 2 4. The wafer-level wafer-scale package according to item 18 of the patent application scope, wherein the insulating layer comprises a material selected from the group consisting of a molding compound, a capsule epoxy resin, an underfill coating, and a photo-imaging material such as a benzo ring One of materials composed of butene (BCB) or polyimide. 2 5. 堑 The wafer-level wafer-scale package of item 18 in the scope of patent application, wherein the reflow soldering material contains solder (s ο 1 d e r). 2 6. The wafer-level wafer-scale package of the 25th item in the scope of Chu's patent application, in which the solder contains low common solder. Page 19