TW201511339A - 發光二極體製造方法 - Google Patents

發光二極體製造方法 Download PDF

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Publication number
TW201511339A
TW201511339A TW102130906A TW102130906A TW201511339A TW 201511339 A TW201511339 A TW 201511339A TW 102130906 A TW102130906 A TW 102130906A TW 102130906 A TW102130906 A TW 102130906A TW 201511339 A TW201511339 A TW 201511339A
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Taiwan
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retaining wall
substrate
light
electrode
cavity
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TW102130906A
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English (en)
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Fu-Hsiang Yeh
Pin-Chuan Chen
Lung-Hsin Chen
Hou-Te Lin
Chao-Hsiung Chang
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Advanced Optoelectronic Tech
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)

Abstract

一種發光二極體製造方法,包括:提供基座,基座包括基板、與基板接合的電極及形成於基板上的擋牆,擋牆圍設形成空腔;將發光晶片安裝於空腔內,使發光晶片與電極電連接;在空腔內注入覆蓋發光晶片的螢光膠;固化螢光膠;切割螢光膠,使螢光膠與擋牆分離,形成獨立的發光二極體。由於無需單獨為分離螢光膠及擋牆設置額外的步驟,因此發光二極體的製造過程更為快捷。

Description

發光二極體製造方法
本發明涉及一種二極體,特別是指一種發光二極體製造方法。
發光二極體作為新興的光源,已被廣泛地應用於各種用途當中。發光二極體通常包括發光晶片及與之搭配使用的螢光粉,以通過螢光粉轉換晶片的出光顏色而獲得理想的光輸出。
現有的發光二極體的螢光粉通常是通過成型的方式設置於晶片上的。具體而言,先採用一個環形的模具同時圍住設於同一基板上的多個晶片,然後再通過射入或其他的成型方式將摻有螢光粉的螢光膠注入環形模具圍設的空間內,再加熱固化螢光膠,最後再移除模具並切割固化的螢光膠。
然而,螢光膠在加熱之後與模具的附著力增大,容易在移除模具的時候黏接或殘留在模具上。將附著的螢光膠從模具上分離需要額外的工序,且過程較為繁瑣,從而影響到發光二極體的生產效率。
因此,有必要提供一種生產效率較高的發光二極體製造方法。
一種發光二極體製造方法,包括:提供基座,基座包括基板、與基板接合的電極及形成於基板上的擋牆,擋牆圍設形成空腔;將發光晶片安裝於空腔內,使發光晶片與電極電連接;在空腔內注入覆蓋發光晶片的螢光膠;固化螢光膠;切割螢光膠,使螢光膠與擋牆分離,形成獨立的發光二極體。
由於擋牆可在最後形成獨立的發光二極體的切割步驟當中直接與螢光膠分離,而無需單獨為分離擋牆及螢光膠增設額外的步驟,因此可快速地製造出發光二極體,從而獲得較高的生產效率。
10‧‧‧基座
12‧‧‧基板
120‧‧‧底面
122‧‧‧頂面
14‧‧‧電極
140‧‧‧第一電極
142‧‧‧第二電極
144‧‧‧頂面
146‧‧‧底面
16‧‧‧擋牆
160‧‧‧側壁
162‧‧‧空腔
164‧‧‧頂面
20‧‧‧發光晶片
30‧‧‧螢光膠
32‧‧‧頂面
40‧‧‧發光二極體
圖1為本發明一實施例的發光二極體製造方法的第一個步驟。
圖2為圖1的剖面示意圖。
圖3為發光二極體製造方法的第二個步驟。
圖4為圖3的剖面示意圖。
圖5為發光二極體製造方法的第三個步驟。
圖6為圖5的剖面示意圖。
圖7為發光二極體製造方法的第四個步驟。
圖8為圖7的剖面示意圖。
圖9為製造完成的發光二極體。
請參閱圖1-9,示出了本發明發光二極體製造方法,其主要包括如下步驟:
首先,如圖1-2所示,提供一基座10。基座10包括一基板12、形成於基板12內的多對電極14及環繞電極14的一擋牆16。基板12由環氧樹脂、矽膠等絕緣材料製造。基板12呈矩形,其包括一底面120及一平行於底面120的頂面122。多對電極14呈矩陣式嵌設於基板12內。每對電極14包括一第一電極140及一第二電極142。第一電極140與第二電極142相互隔開以避免短路。第一電極140及第二電極142的頂面144均與基板12的頂面122齊平而暴露於基板12外,第一電極140及第二電極142的底面146也均與基板12的底面120齊平而暴露於基板12外。本實施例中,第一電極140及第二電極142均採用導電材料製造,如銅、鋁等金屬。擋牆16可與基板12一體成型,也可以先分別形成基板12及擋牆16,然後再通過黏膠等方式固定。擋牆16呈環形,其由四側壁160首尾連接而成。每一側壁160為縱長的條狀,其高度大於基板12的厚度。每一側壁160均與相鄰的二側壁160垂直,且與相對的一側壁160平行。四側壁160共同圍設出一矩形的空腔162。多對電極14均位於空腔162內。
然後,如圖3-4所示,在各對電極14上安裝發光晶片20。每一發光晶片20通過固晶膠或其他固定方式安裝於相應的第二電極142上,並通過導線22與相鄰的第一電極140及第二電極142電連接。發光晶片20可採用諸如氮化鎵、氮化鋁鎵、氮化鋁銦鎵等半導體發光材料製造,其受到電流激發而發出光線。優選地,本實施例中的發光晶片20為藍光晶片,以合成出白光。發光晶片20均被收容於空腔162內而被擋牆16所環繞。發光晶片20的高度小於擋牆16的高度。可以理解地,對於倒裝型發光晶片20而言,本步驟當中可直接將其倒置固定於第一電極140及第二電極142上,而無需使用導線22。
之後,如圖5-6所示,在空腔162內注入螢光膠30。螢光膠30的注入方式可採用射入成型、轉移成型、印刷等方法實現。螢光膠30在注入之後填滿整個空腔162並覆蓋住發光晶片20及導線22。由於擋牆16的阻擋,螢光膠30被限制在空腔162內而不會發生流動,從而使形狀被暫時固定。螢光膠30的頂面32可低於擋牆16的頂面164或與擋牆16的頂面164齊平。螢光膠30是由摻雜有螢光粉顆粒的透明膠體組成。螢光粉顆粒可由釔鋁石榴石、矽酸鹽、氮氧化物等螢光材料製造,其可在某種特定顏色光線的激發下發出其他顏色的光線。本實施例中,螢光粉顆粒優選為黃色螢光粉顆粒,其可在發光晶片20藍光的激發下發出黃光,進而與藍光合成白光。
最後,如圖7-8所示,固化螢光膠30,再切割基座10及螢光膠30。固化螢光膠30可採用烘烤、紫外光照射等方法實現。螢光膠30在固化之後硬度增大,且形狀隨之固定。固化後的螢光膠30的硬度仍小於基板12及擋牆16的硬度。切割線可選在每兩對相鄰的電極14之間以及每對電極14與擋牆16之間的位置處。由此,切割之後可確保每對電極14都與相鄰的電極14及擋牆16分離,從而形成多個獨立的發光二極體40。切割過程中,固化的螢光膠30也同時被切割成多塊並與擋牆16分離,從而覆蓋住每一發光二極體40的發光晶片20。在此步驟當中,擋牆16是隨著切割基座10及螢光膠30形成發光二極體40的過程一同從螢光膠30上分離,因此無需單獨為分離螢光膠30及擋牆16設立額外的步驟。由此,發光二極體40可被快速地進行製造,從而提升整個生產過程的效率。
如圖9所示,每一獨立的發光二極體40均包括一對電極14、一發光晶片20及覆蓋發光晶片20的螢光膠30。發光晶片20在通電之後將發出藍光,進而激發螢光膠30發出黃光。激發的黃光與剩餘的藍光再混合形成白光。
本發明之技術內容及技術特點已揭示如上,然而熟悉本項技術之人士仍可能基於本發明之教示及揭示而作種種不背離本發明精神之替換及修飾。因此,本發明之保護範圍應不限於實施例所揭示者,而應包括各種不背離本發明之替換及修飾,並為以下之申請專利範圍所涵蓋。
10‧‧‧基座
14‧‧‧電極
16‧‧‧擋牆
20‧‧‧發光晶片
30‧‧‧螢光膠

Claims (10)

  1. 一種發光二極體製造方法,包括:
    提供基座,基座包括基板、與基板接合的電極及形成於基板上的擋牆,擋牆圍設形成空腔;
    將發光晶片安裝於空腔內,使發光晶片與電極電連接;
    在空腔內注入覆蓋發光晶片的螢光膠;
    固化螢光膠;
    切割螢光膠,使螢光膠與擋牆分離,形成獨立的發光二極體。
  2. 如申請專利範圍第1項所述之方法,其中擋牆的高度大於基板的厚度。
  3. 如申請專利範圍第1項所述之方法,其中電極被擋牆所環繞。
  4. 如申請專利範圍第1項所述之方法,其中擋牆與基板一體成型。
  5. 如申請專利範圍第1項所述之方法,其中發光晶片的高度小於擋牆的高度。
  6. 如申請專利範圍第1項所述之方法,其中電極的數量為多對,切割螢光膠的位置位於相鄰兩對電極之間以及各對電極與擋牆之間。
  7. 如申請專利範圍第1項所述之方法,其中在切割螢光膠之前電極與擋牆相互隔開。
  8. 如申請專利範圍第1項所述之方法,其中擋牆包括四首尾相連的側壁,每一側壁與相鄰的二側壁垂直,並與相對的一側壁平行。
  9. 如申請專利範圍第1項所述之方法,其中固化後的螢光膠的硬度小於擋牆的硬度。
  10. 如申請專利範圍第1項所述之方法,其中注入空腔的螢光膠的頂面與擋牆的頂面齊平。
TW102130906A 2013-08-23 2013-08-28 發光二極體製造方法 TW201511339A (zh)

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CN105374923A (zh) * 2015-10-28 2016-03-02 江苏新广联半导体有限公司 五面出光的led封装结构及其制备方法
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EP2378576A2 (en) * 2010-04-15 2011-10-19 Samsung LED Co., Ltd. Light emitting diode package, lighting apparatus having the same, and method for manufacturing light emitting diode package
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