TW201505144A - Chip package and method for forming the same - Google Patents

Abstract

A chip package is disclosed. The chip package includes a chip having an upper surface, a lower surface and a sidewall. The chip includes a sensing region or device region and a signal bonding pad region adjacent to the upper surface. A shallow recess structure is outside of the signal bonding pad region and extends from the upper surface toward the lower surface along the sidewall. The shallow recess structure has at least a first recess and a second recess under the first recess. A redistribution layer is electrically connected to the signal bonding pad region and extends into the shallow recess structure. A wire has a first end and a second end. The first end is in the shallow recess structure and is electrically connected to the redistribution layer. The second end is used for external electrical connection. A method for forming the chip package is also disclosed.

Description

Chip package and method of manufacturing same

The present invention relates to a chip package technology, and more particularly to a chip package and a method of fabricating the same.

The wafer packaging process is an important step in the process of forming electronic products. In addition to protecting the wafer from the external environment, the chip package also provides an electrical connection path between the electronic components inside the wafer and the outside.

A conventional chip package having a sensing function, such as the fingerprint identification chip package disclosed in FIG. 4, places the fingerprint identification chip 520 on the printed circuit board 510 and is connected to the upper surface of the wafer 520 through a plurality of wires 530. The pad region is soldered to the printed circuit board 510, after which the fingerprint identification wafer 520 is overlaid with the encapsulation layer 540. Since the thickness of the wiring layer 530 is such that the thickness of the encapsulation layer 540 cannot be reduced, in order to avoid the influence of the sensitivity of the sensing region 523 due to the encapsulation layer 540 being too thick, the height of the surrounding side of the packaged fingerprint identification wafer 520 is designed to be higher than The central sensing area 523 is therefore unable to form a flat surface. In addition, since the wiring 530 is adjacent to the edge of the fingerprint recognition wafer 520, it is easy to cause a short circuit or a disconnection due to touching the edge of the wafer during the soldering process, resulting in a decrease in yield.

Therefore, it is necessary to find a novel chip package and a method of manufacturing the same to reduce the thickness of the package layer, thereby improving the sensing sensitivity of the chip package, and providing a chip package having a flat contact surface.

Embodiments of the present invention provide a chip package including a wafer having an upper surface, a lower surface, and a sidewall, wherein the upper surface includes a sensing region and a signal pad region. A shallow groove structure is located outside the signal pad region and extends along the sidewall from the upper surface toward the lower surface. The shallow groove structure has at least a first recess and a second recess, and the second recess is located below the first recess. A heavy wiring layer is electrically connected to the signal pad region and extends to the shallow groove structure. A wire has a first end point and a second end point, wherein the first end point is electrically connected to the redistribution layer in the shallow groove structure, and the second end point is used for external electrical connection.

Embodiments of the present invention provide a method of fabricating a chip package, comprising providing a wafer having a plurality of wafers, each wafer having an upper surface and a lower surface, wherein the wafer includes a sensing region and a signal connection at the upper surface Pad area. A shallow groove structure is formed on each of the wafers, located outside the signal pad region and extending from the upper surface toward the lower surface. The shallow groove structure has at least a first recess and a second recess, and the second recess is located below the first recess. A redistribution layer is formed on each of the wafers, electrically connected to the signal pad region and extending to the shallow groove structure. The wafer is diced to separate the wafers such that each wafer has a sidewall and the shallow groove structure extends along the sidewall. A wire is soldered to each of the wafers, the wire having a first end point and a second end point, wherein the first end point is electrically connected to the redistribution layer in the shallow groove structure, and the second end point is used for external electrical connection.

Embodiments of the present invention provide a chip package including a wafer having an upper surface, a lower surface, and a sidewall, wherein the wafer includes a sensing region or component region and a signal pad region on the upper surface. A shallow groove structure is located outside the signal pad region and extends along the sidewall from the upper surface toward the lower surface. Shallow groove structure There is at least a first recess and a second recess, and the second recess is located below the first recess. A heavy wiring layer is electrically connected to the signal pad region and extends to the shallow groove structure. A wire has a first end point and a second end point. The first end point is electrically connected to the redistribution layer in the shallow groove structure, and the second end point is used for external electrical connection. The wafer includes a semiconductor substrate and an insulating layer. The sidewall of the first recess abuts the insulating layer, the sidewall of the second recess abuts the semiconductor substrate, and the bottom of the first recess exposes the surface of the semiconductor substrate. An encapsulation layer covers at least the wiring.

Embodiments of the present invention provide a chip package including a wafer having an upper surface, a lower surface, and a sidewall, wherein the wafer includes a sensing region or component region and a signal pad region on the upper surface. A shallow groove structure is located outside the signal pad region and extends along the sidewall from the upper surface toward the lower surface. The shallow groove structure has at least a first recess and a second recess, and the second recess is located below the first recess. A wiring layer is electrically connected to the signal pad region and extends to the sidewalls and the bottom of the first recess and the second recess. A wire has a first end point and a second end point, wherein the first end point is electrically connected to the redistribution layer at the bottom of the second notch, the second end point is used for external electrical connection, and wherein the first recess is The lateral width of the bottom of the mouth is narrower than the lateral width of the bottom of the second recess. An encapsulation layer covers at least the wiring.

Embodiments of the present invention provide a chip package including a wafer having an upper surface, a lower surface, and a sidewall, wherein the wafer includes a sensing region or component region and a signal pad region on the upper surface. A shallow groove structure is located outside the signal pad region and extends along the sidewall from the upper surface toward the lower surface. The shallow groove structure has at least a first recess and a second recess, and the second recess is located below the first recess. A heavy wiring layer is electrically connected to the signal pad region and extends to the shallow groove structure. A wire has a first end point and a second end point, and the first end point is in a shallow groove structure The inner wiring is electrically connected to the redistribution layer, and the second terminal is used for external electrical connection, wherein one of the wires is higher than the upper surface of the wafer. An encapsulation layer covers at least the wiring.

100‧‧‧ wafer

100a‧‧‧ upper surface

100b‧‧‧ lower surface

120‧‧‧ wafer area

140, 260‧‧‧ insulation

150‧‧‧Base

160‧‧‧Signal pad area

180, 320, 340‧‧‧ openings

200, 523‧‧‧Sensing area/component area

220‧‧‧ first notch

220a‧‧‧first side wall

220b‧‧‧ first bottom

230‧‧‧second notch

230a‧‧‧second side wall

230b‧‧‧ second bottom

280‧‧‧Rewiring layer

300‧‧ ‧ protective layer

360‧‧‧Adhesive layer

380‧‧‧External components

400‧‧‧Pushing area

440, 530‧‧‧ wiring

440a‧‧‧first endpoint

440b‧‧‧second endpoint

The highest part of 440c‧‧

460, 540‧‧ ‧ encapsulation layer

480‧‧‧decorative layer

500‧‧‧protection layer

510‧‧‧Printed circuit board

520‧‧‧Fingerprinting chip

D1, D2‧‧ depth

H1‧‧‧ distance

H2‧‧ depth

H3‧‧‧ Coverage thickness

1A to 1F are cross-sectional views showing a method of manufacturing a chip package in accordance with an embodiment of the present invention.

2 through 3 are schematic cross-sectional views showing a chip package in accordance with various embodiments of the present invention.

Figure 4 is a schematic cross-sectional view showing a conventional chip package.

The manner of making and using the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many inventive concepts that can be applied in various specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the invention and are not to be construed as a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers.

The chip package of one embodiment of the present invention can be used to package a sensing wafer, such as a biometric wafer such as a fingerprint reader. However, the application is not limited thereto. For example, in the embodiment of the chip package of the present invention, it can be applied to various active or passive elements, digital circuits or analog circuits. Integrated circuit electronic components (electronic components), for example, about opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or the use of physical quantities such as heat, light, capacitance, and pressure To measure the physical sensor (Physical Sensor). In particular, some or all of the process of wafer scale package (WSP) can be used for image sensing components, light-emitting diodes (LEDs), solar cells, and radio frequency components. RF circuits), accelerators, gyroscopes, micro actuators, surface acoustic wave devices, process sensors, or ink printer heads The semiconductor wafer is packaged.

The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also applicable to a chip package in which a plurality of wafers having integrated circuits are arranged by a stack to form multi-layer integrated circuit devices.

Referring to FIG. 1F, a cross-sectional view of a chip package in accordance with an embodiment of the present invention is shown. In the present embodiment, the chip package includes a wafer 100, a shallow recess structure, an external component 380, and a wire 440. The wafer 100 has an upper surface 100a and a lower surface 100b. In one embodiment, the wafer 100 includes an insulating layer 140 adjacent to the upper surface 100a and a substrate 150 therebelow. In general, the insulating layer 140 may be an interlayer dielectric layer (interlayer) Dielectric, ILD), inter-metal dielectric (IMD) and covered passivation. In the present embodiment, the insulating layer 140 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination of the foregoing or other suitable insulating materials. In this embodiment, substrate 150 can comprise germanium or other semiconductor material.

In the present embodiment, the wafer 100 includes a signal pad region 160 and a sensing region/element region 200 that can be adjacent to the upper surface 100a. In one embodiment, the signal pad region 160 includes a plurality of conductive pads, which may be a single conductive layer or a conductive layer structure having multiple layers. To simplify the drawing, only a single conductive layer is exemplified herein, and only one conductive pad in the insulating layer 140 is illustrated as an example. In this embodiment, one or more openings 180 may be included in the insulating layer 140 to expose corresponding conductive pads.

In one embodiment, the sensing region/element region 200 of the wafer 100 contains a sensing element. For example, a biosensing wafer whose sensing elements can be used to sense biological features. In another embodiment, the wafer 100 is used to sense environmental characteristics, and may include, for example, a temperature sensing component, a humidity sensing component, a pressure sensing component, a capacitive sensing component, or other suitable sensing component. . In yet another embodiment, the sensing wafer 100 can include an image sensing element. In one embodiment, the sensing elements in the sensing wafer 100 are electrically connected to the conductive pads through an interconnect structure within the insulating layer 140.

In one embodiment, the shallow groove structure is composed of a first recess 220, located outside the signal pad region 160, and extends along the sidewall of the wafer 100 from the upper surface 100a toward the lower surface 100b. The first recess 220 includes a first A side wall 220a and a first bottom portion 220b. In an embodiment, the first sidewall 220a of the first recess 220 is adjacent to The insulating layer 140 is attached to expose the substrate 150 below it. In the present embodiment, the depth D1 of the first recess 220 (indicated in FIG. 1B) is no more than 15 micrometers. In one embodiment, the sidewalls 220a are substantially perpendicular to the upper surface 100a by etching the first recess 220 formed by the insulating layer 140. For example, the first sidewall 220a and the upper surface 100a of the first recess 220 The angle between the two can be approximately in the range of 84° to 90°. In addition, in another embodiment, by cutting the first recess 220 formed by the insulating layer 140, the angle between the first sidewall 220a of the first recess 220 and the upper surface 100a may be approximately 55° to 90°. The scope.

In an embodiment, an insulating layer 260 may be selectively disposed on the upper surface 100a of the wafer 100 and extend to the first sidewall 220a and the first bottom 220b in the first recess 220, and expose portions. Signal pad area 160. In the present embodiment, the insulating layer 260 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination thereof, or other suitable insulating materials.

A patterned redistribution layer (RDL) 280 extends compliantly to the opening 180 and the first sidewall 220a and the first bottom 220b of the first recess 220. The redistribution layer 280 can be electrically connected to the signal pad region 160 via the opening 180. In an embodiment, the redistribution layer 280 is disposed on the insulating layer 260, thereby avoiding electrical contact with the substrate 150. In an embodiment, the redistribution layer 280 may include copper, aluminum, gold, platinum, nickel, tin, a combination of the foregoing, a conductive polymer material, a conductive ceramic material (eg, indium tin oxide or indium zinc oxide) or other suitable Conductive material.

A protection layer 300 is disposed on the redistribution layer 280 and the insulating layer 260 and extends into the first recess 220. Protective layer 300 One or more openings are included to expose a portion of the redistribution layer 280. In the present embodiment, the protective layer 300 includes openings 320 and 340 that expose the signal pad region 160 and the redistribution layer 280 in the first recess 220, respectively. In other embodiments, the protective layer 300 may include only an opening 340 therein, such as covering the opening 320 of the signal pad region 160. In the present embodiment, the protective layer 300 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination thereof, or other suitable insulating materials.

The outer member 380 can be a substrate that is attached to the lower surface 100b of the wafer 100 through an adhesive layer (e.g., glue) 360. In this embodiment, the external component 380 can be a circuit board, a wafer (eg, a processor), or an interposer. In the case of a circuit board, the surface may have one or more pad regions 400.

The wire 440 has a first end point 440a and a second end point 440b, wherein the first end point 440a is electrically connected to the redistribution layer in the shallow groove structure, and the second end point 440b is used for electrical connection of the external component. And a portion of the wiring 440 protrudes from the upper surface 100a of the wafer. For example, the wiring 440 is electrically connected to the pad region 400 of the circuit board 380 through the second terminal 440b, and electrically connected to the redistribution layer on the first bottom portion 220b of the first recess 220 through the first terminal 440a. 280, wherein the highest portion 440c of the wiring 440 protrudes from the upper surface 100a of the wafer. In this embodiment, although one portion of the wire 440 protrudes from the upper surface 100a of the wafer as an example, it is not limited thereto. In some embodiments, the shallow groove structure can also make the wire 440 lower than the upper surface 100a.

In this embodiment, the chip package may further include an encapsulant 460 that can selectively cover the wiring 440 and the dimple The trench structure extends over the upper surface 100a of the wafer to form a flattened contact surface over the sensing region/element region 200. The encapsulation layer 460 is generally composed of a molding material or a sealing material.

In an embodiment, the decorative layer 480 may be additionally disposed on the encapsulation layer 460, and may have a color according to design requirements to display an area having a sensing function. A protective layer (eg, a sapphire substrate or a hard rubber) 500 may be additionally disposed on the decorative layer 480 to further provide a wear-resistant, scratch-resistant, and highly reliable surface, thereby avoiding the feeling of using the chip package. The sensing device is contaminated or destroyed during the measurement function.

According to the above embodiment of the invention, the highest portion 440c of the wiring 440 has a distance H1 between the bottom of the shallow groove structure (i.e., the first bottom 220b of the first recess 220), and the shallow groove structure has a The depth H2 (that is, the depth D1 of the first notch 220). The cover thickness H3 of the encapsulation layer 460 in the sensing region/element region 200 is determined by the difference between the distance H1 between the highest portion 440c of the wiring 440 and the bottom of the shallow groove structure and the depth H2 of the shallow groove structure (H1- H2). Therefore, by adjusting the depth H2 of the shallow groove structure, the cover thickness of the encapsulation layer 460 can be reduced, the sensitivity of the sensing region can be increased, and a flattened contact surface can be formed. In addition, since such a shallow groove structure does not require removal of excessive base material, the structural strength of the substrate can be maintained.

Referring to FIGS. 2 to 3, there are shown schematic cross-sectional views of a chip package according to various embodiments of the present invention, wherein components in the same reference numerals are used for the same reference numerals and the description thereof is omitted. The structure of the chip package in FIG. 2 is similar to the structure of the chip package in FIG. 1F. The difference is that the chip package further includes a second notch 230 in FIG. 2, the first from the first notch 220. Bottom 220b The second recess 230 has a second sidewall 230a and a second bottom portion 230b. The second sidewall 230a of the second recess 230 abuts the substrate 150. The lateral width of the second recess 230 in the lower layer is narrower than the first recess 220 of the upper layer. In an embodiment, the insulating layer 260 extends to the second sidewall 230a and the second bottom portion 230b of the second recess 230.

In the present embodiment, the highest portion 440c of the wiring 440 has a distance H1 from the first bottom 220b of the first recess 220. The cover thickness H3 of the encapsulation layer 460 in the sensing region/element region 200 is determined by the difference between the distance H1 between the highest portion 440c of the wiring 440 and the bottom of the shallow groove structure and the depth D1 of the first notch 220 (H1) -D1).

In the present embodiment, the first end point 440a of the wiring 440 electrically contacts the redistribution layer 280 on the first bottom portion 220b of the upper first recess 220, so that the maximum height of the wiring 440 can be further reduced, The two notches 230 increase the distance between the wire 440 and the first bottom portion 220b of the first recess 220, thereby reducing the probability of the wire being shorted or broken due to touching the edge of the first recess 220.

The structure of the chip package in FIG. 3 is similar to the structure of the chip package in FIG. 2, with the difference that the lateral width of the second recess 230 in the lower layer in FIG. 3 is wider than the first recess 220 of the upper layer. At the same time, the redistribution layer 280 further extends to the second sidewall 230a and the second bottom portion 230b of the second recess 230 of the lower layer, and the first end 440a of the wiring 440 electrically contacts the second recess 230 of the lower layer from the opening 340. The redistribution layer 280 on the second bottom portion 230b. In addition, the first recess 220 of the upper layer extends beyond the insulating layer 140 and may extend into the substrate 150 below it.

In the present embodiment, the highest portion 440c of the wiring 440 has a distance from the bottom of the shallow groove structure (i.e., the second bottom portion 230b of the second recess 230). From H1, and the shallow groove structure has a depth H2 (i.e., the depth D1 of the first notch 220 plus the depth D2 of the second notch 230). The cover thickness H3 of the encapsulation layer 460 in the sensing region/element region 200 is determined by the difference between the distance H1 between the highest portion 440c of the wiring 440 and the bottom of the shallow groove structure and the depth H2 of the shallow groove structure (H1- H2).

In the present embodiment, the second recess 230 is further extended into the substrate 150, so that the maximum height of the wiring 440 can be further reduced, but the structural strength of the substrate is less affected, and the first recess 220 can be avoided directly. The over-etching caused by the extension causes an undercut phenomenon of the interface between the insulating layer 140 and the substrate 150.

In other embodiments, the wire 440 is soldered to the redistribution layer 280 starting from the second end point 440b to form a first end point 440a.

Hereinafter, a method of manufacturing a chip package according to an embodiment of the present invention will be described with reference to FIGS. 1A to 1F, wherein FIGS. 1A to 1F are schematic cross-sectional views showing a method of manufacturing a chip package according to an embodiment of the present invention.

Referring to FIG. 1A, a wafer having a wafer region 120 is provided. The wafer region 120 includes a plurality of wafers 100 each having an upper surface 100a and a lower surface 100b. In one embodiment, the wafer includes a substrate 150 and an insulating layer 140 adjacent to the upper surface 100a. Generally, the insulating layer 140 may be composed of an interlayer dielectric layer (ILD), an inter-metal dielectric layer (IMD), and a passivation layer covering the layer. composition. In the present embodiment, the insulating layer 140 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination of the foregoing or other suitable insulating materials. In this embodiment, substrate 150 can comprise germanium or other semiconductor material.

In this embodiment, one or more signal pad regions 160 are included in each wafer, which may be adjacent to the upper surface 100a and include a plurality of conductive layers. pad. To simplify the drawing, only a single wafer region 120 and one conductive pad located within the insulating layer 140 are shown. In an embodiment, the conductive pad may be a single conductive layer or a conductive layer structure having multiple layers. Here, only a single conductive layer is exemplified. In this embodiment, one or more openings 180 may be included in the insulating layer 140 to expose corresponding conductive pads.

In this embodiment, each wafer 100 has a sensing region/element region 200 that is adjacent to the upper surface 100a. In an embodiment, the sensing region/element region 200 is used to sense a biological feature, for example, may include a fingerprint recognition component. In another embodiment, the sensing region/element region 200 is used to sense environmental features, and may include a temperature sensing component, a humidity sensing component, a pressure sensing component, a capacitive sensing component, or other suitable Sensing element. In yet another embodiment, the sensing region/element region 200 can include an image sensing element. In an embodiment, the sensing elements in the sensing region/element region 200 are electrically connected to the conductive pads through an interconnect structure within the insulating layer 140.

Please refer to FIG. 1B, which can be formed on the sidewall of each wafer 100 through a lithography process and an etching process (eg, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or other suitable process). The shallow groove structure, for example, forms a first recess 220 from the insulating layer 140, which extends along the scribe line (not shown) from the upper surface 100a toward the lower surface 100b, and penetrates the insulating layer 140 to expose the substrate below it. 150, that is, the depth of the first recess 220 is approximately equal to the thickness of the insulating layer 140 or more. In the present embodiment, the depth D1 of the first recess 220 is no more than 15 micrometers. In one embodiment, the first sidewall 220a of the first recess 220 formed by the etching process is substantially perpendicular to the upper surface 100a. For example, the angle between the sidewall of the first recess 220 and the upper surface 100a may be approximately 84° to 90°. The scope. In another embodiment, the sidewall of the first recess 220 formed by the cutting process is substantially oblique to the upper surface 100a. For example, the angle between the sidewall of the first recess 220 and the upper surface 100a may be in the range of approximately 55° to 90°.

Referring to FIG. 1C, an insulating layer 260 may be formed on the upper surface 100a of the wafer 100 by a deposition process (for example, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process). It extends into the opening 180 of the insulating layer 140 and the first recess 220. In the present embodiment, the insulating layer 260 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination of the foregoing or other suitable insulating materials.

Then, the insulating layer 260 in the opening 180 can be removed through a lithography process and an etching process (eg, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or other suitable process) to expose Part of the signal pad area 160. Then, through the deposition process (for example, coating process, physical vapor deposition process, chemical vapor deposition process, electroplating process, electroless process or other suitable process), lithography process and etching process, on the insulating layer 260 A patterned redistribution layer 280 is formed.

The redistribution layer 280 is compliantly extended to the opening 180 and the first sidewall 220a and the first bottom 220b of the first recess 220, and the exposed pad region 160 can be electrically connected via the opening 180. In an embodiment, the redistribution layer 280 does not extend to the edge of the first bottom 220b of the first recess 220. Moreover, when the substrate 150 includes a semiconductor material, the redistribution layer 280 can be electrically isolated through the insulating layer 260. In an embodiment, the redistribution layer 280 may include copper, aluminum, gold, platinum, nickel, tin, a combination of the foregoing, a conductive polymer material, a conductive ceramic material (eg, indium tin oxide or indium zinc oxide) or other suitable Conductive material.

Referring to FIG. 1D, the protection can be formed on the redistribution layer 280 and the insulating layer 260 by a deposition process (for example, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process). Layer 300 extends into first recess 220. In the present embodiment, the protective layer 300 may include an inorganic material such as hafnium oxide, tantalum nitride, hafnium oxynitride, metal oxide or a combination of the foregoing or other suitable insulating materials.

Then, one or more openings may be formed in the protective layer 300 through a lithography process and an etching process (eg, a dry etching process, a wet etching process, a plasma etching process, a reactive ion etching process, or other suitable process). A portion of the redistribution layer 280 is exposed. In the present embodiment, openings 320 and 340 are formed in the protective layer 300 to expose the opening 180 and the redistribution layer 280 in the first recess 220, respectively.

In other embodiments, only the opening 340 may be formed within the protective layer 300. It will be understood that the number and location of the openings in the protective layer 300 are not limited to this depending on the design requirements.

Next, along the dicing streets (not shown), the wafer is subjected to a dicing process to form a plurality of individual wafers 100. After the cutting process is performed, the first recess 220 of each wafer extends along the sidewall from the upper surface 100a toward the lower surface 100b.

Referring to FIG. 1E, an external component 380 can be attached to the lower surface 100b of the substrate 150 in a separate wafer through an adhesive layer (eg, adhesive) 360. In this embodiment, the external component 380 can be a circuit board, a wafer, or an interposer. In the case of a circuit board, the outer component 380 can have one or more pad regions 400 therein. Similarly, the pad region 400 can include a plurality of conductive pads and is electrically conductive The pad may be a single conductive layer or a conductive layer structure having multiple layers. To simplify the drawing, only a single conductive layer is taken as an example here, and only one conductive pad of one pad region 400 is illustrated as an example.

Then, a second terminal 440b starting from the pad region 400 of the external component 380 can be formed through a wire bonding process to form a wire 440 and electrically connected to the first notch 220 by the first terminal 440a. The redistribution layer 280 on the first bottom portion 220b. In the present embodiment, the wire 440 has a highest portion 440c that is at a distance H1 from the first bottom portion 220b of the first recess 220. In this embodiment, the wires 440 may comprise gold or other suitable electrically conductive material.

In another embodiment, as shown in FIG. 2, the difference is that a portion of the substrate is removed by an etching or dicing process to form a second recess 230 from the first bottom 220b of the first recess 220 toward the lower surface. Extendingly, the second recess 230 has a second sidewall 230a and a second bottom 230b, wherein the second sidewall 230a of the second recess 230 abuts the substrate 150, and the lateral width of the second recess 230 in the lower layer is narrower than the upper layer The first recess 220. In an embodiment, the insulating layer 260 extends to the second sidewall 230a and the second bottom portion 230b of the second recess 230.

In the present embodiment, the first end point 440a of the wiring 440 electrically contacts the redistribution layer 280 on the bottom of the upper first recess 220, so that in addition to further reducing the highest height of the wiring 440, the second recess 230 is further The distance between the wire 440 and the first bottom portion 220b of the first recess 220 is increased, thereby reducing the probability of the wire being shorted or broken due to touching the edge of the first recess 220.

In still another embodiment, the structure of the chip package in FIG. 3 is similar to the structure of the chip package in FIG. 2, with the difference that the lateral width of the second recess 230 in the lower layer is formed by an etching or cutting process. The first notch wider than the upper layer 220. At the same time, the redistribution layer 280 further extends to the second sidewall 230a and the second bottom portion 230b of the second recess 230 of the lower layer, but does not extend to the edge of the second bottom portion 230b. The first terminal 440a of the wiring 440 electrically contacts the redistribution layer 280 on the second bottom portion 230b of the second recess 230 of the lower layer from the opening 340.

In the present embodiment, since the second recess 230 further extends into the substrate 150, the maximum height of the wiring 440 can be further reduced, but the structural strength of the substrate is less affected, and the first recess 220 of the upper layer can be directly etched. The undercut of the interface between the insulating layer 140 and the substrate 150 is caused by over-etching.

Referring to FIG. 1F, an encapsulation layer 460 may be formed on the upper surface 100a of the wafer through a molding process or other suitable process, which may selectively cover the first recess 220, the external component 380, and the wiring 440. Or extending to the upper surface 100a of the wafer to form a flattened contact surface over the sensing region/element region 200.

Next, a decorative layer 480 can be formed on the encapsulation layer 460 through a deposition process (eg, a coating process or other suitable process) that can be colored according to design requirements to display areas with sensing functionality. Next, a protective layer (eg, sapphire substrate or hard plastic) 500 may be formed on the decorative layer 480 through a deposition process (eg, a coating process, a physical vapor deposition process, a chemical vapor deposition process, or other suitable process). To further provide a wear-resistant, scratch-resistant and highly reliable surface.

While the invention has been described above in terms of the preferred embodiments thereof, which are not intended to limit the invention, the invention may be modified and combined with the various embodiments described above without departing from the spirit and scope of the invention. example.

100‧‧‧ wafer

100a‧‧‧ upper surface

100b‧‧‧ lower surface

140, 260‧‧‧ insulation

150‧‧‧Base

160‧‧‧Signal pad area

180, 320, 340‧‧‧ openings

200‧‧‧Sensing area/component area

220‧‧‧ first notch

220a‧‧‧first side wall

220b‧‧‧ first bottom

230‧‧‧second notch

230a‧‧‧second side wall

230b‧‧‧ second bottom

280‧‧‧Rewiring layer

300‧‧ ‧ protective layer

360‧‧‧Adhesive layer

380‧‧‧External components

400‧‧‧Pushing area

440‧‧‧ wiring

440a‧‧‧first endpoint

440b‧‧‧second endpoint

The highest part of 440c‧‧

460‧‧‧Encapsulation layer

480‧‧‧decorative layer

500‧‧‧protection layer

D1, D2‧‧ depth

H1‧‧‧ distance

H2‧‧ depth

H3‧‧‧ Coverage thickness

Claims (34)

A chip package includes: a wafer having an upper surface, a lower surface, and a sidewall, wherein the wafer includes a sensing region or component region and a signal pad region on the upper surface; and a shallow groove structure An outer side of the signal pad region and extending along the sidewall from the upper surface toward the lower surface, wherein the shallow groove structure has at least a first recess and a second recess, and the second recess is located at the bottom a first wiring layer, electrically connected to the signal pad region and extending to the shallow groove structure; and a wire having a first end point and a second end point, wherein the first end point The redistribution layer is electrically connected to the shallow recess structure, and the second end is used for external electrical connection. The chip package of claim 1, wherein the first recess has a first sidewall and a first bottom, and the redistribution layer extends to the first sidewall of the first recess and the First bottom. The chip package of claim 2, wherein the second recess extends from the first bottom of the first recess toward the lower surface, wherein the second recess has a second sidewall and a Second bottom. The chip package of claim 3, wherein the first bottom has a lateral width wider than the second bottom, and the first end of the wiring is electrically connected to the redistribution at the first bottom On the floor. The chip package of claim 3, wherein the redistribution layer extends from the upper surface to the second sidewall and the second bottom of the second recess unit. The chip package of claim 5, wherein the first bottom has a lateral width narrower than the second bottom, wherein the first end of the wire is electrically connected to the weight at the second bottom On the wiring layer. The chip package of claim 3, wherein the wafer comprises a substrate and an insulating layer, wherein the first sidewall of the first recess abuts the insulating layer and a portion of the substrate, the second recess The second side wall of the mouth abuts the substrate. The chip package of claim 7, further comprising an encapsulation layer covering the wiring and the upper surface to form a flat contact surface over the sensing region or the component region, wherein the a bottom lateral width is wider than the second bottom, and the first end of the wiring is electrically connected to the redistribution layer on the first bottom, and a highest portion of the wiring protrudes from the wafer a surface, and a thickness of the encapsulation layer on the sensing region or the component region is determined by a distance between the highest portion of the wiring and the first bottom of the first recess and a depth of the first recess The difference. The chip package of claim 8, wherein the wafer is a biometric wafer. The chip package of claim 7, further comprising an encapsulation layer covering the wiring and the upper surface to form a flat contact surface over the sensing region or the component region, wherein the a lateral width of the bottom portion is narrower than the second bottom portion, the redistribution layer further extends to the second sidewall and the second bottom portion of the second recess, and the first end of the connection is electrically connected to the second sidewall The second part of the redistribution layer, the highest part of the wiring Projecting on the upper surface of the wafer, and the thickness of the encapsulation layer on the sensing region or the component region is determined by a distance between the highest portion of the wiring and the second bottom portion of the second recess The difference in depth of the shallow groove structure. The chip package of claim 10, wherein the wafer is a fingerprint identification wafer. The chip package of claim 10, wherein the redistribution layer does not extend to an edge of the second recess. The chip package of claim 1, further comprising a protective layer covering the redistribution layer and forming an opening in the shallow groove structure for the first end of the wiring The redistribution layer is electrically connected. The chip package of claim 13, wherein the signal pad region is covered by the protective layer. The chip package of claim 1, wherein the second end of the wire is a starting point of welding. The chip package of claim 1, wherein the redistribution layer does not extend to an edge of the shallow groove structure. The chip package of claim 1, wherein the first end point and the second end point of the wiring are lower than the upper surface of the wafer, and a highest portion of the wiring protrudes from the wafer Upper surface. The chip package of claim 17, further comprising an encapsulation layer covering the wiring and the upper surface to form a flat contact surface over the sensing region or the component region, wherein the package The thickness of the layer on the sensing region or the component region is determined by the highest portion of the wiring and the The difference between the distance between the bottoms of the shallow groove structure and the depth of the shallow groove structure. A method of manufacturing a chip package, comprising: providing a wafer comprising a plurality of wafers, each wafer having an upper surface and a lower surface, wherein each of the wafers includes a sensing region or an element region and a surface on the upper surface a signal pad region; a shallow groove structure is formed on each of the wafers, and is located outside the signal pad region and extends from the upper surface toward the lower surface, wherein the shallow groove structure has at least a first recess and a second recess, and the second recess is located under the first recess; forming a redistribution layer on each of the wafers, electrically connecting the signal pad region and extending to the shallow recess structure; cutting the crystal Rounding the wafers such that each wafer has a sidewall along which the shallow recess structure extends; and soldering a wire to each of the wafers, having a first end point and a second end point The first end point is electrically connected to the redistribution layer in the shallow groove structure, and the second end point is used for external electrical connection. The method of manufacturing a chip package according to claim 19, wherein the first recess has a first sidewall and a first bottom, wherein the redistribution layer extends to the first of the first recess a side wall and the first bottom. The method of manufacturing the chip package of claim 20, wherein the second recess extends from the first bottom of the first recess toward the lower surface, wherein the second recess has a second a side wall and a second bottom. A method of manufacturing a chip package as described in claim 21, The first bottom portion has a lateral width wider than the second bottom portion, and the first end of the wiring is electrically connected to the redistribution layer on the first bottom portion. The method of manufacturing a chip package according to claim 22, further comprising forming an encapsulation layer covering the wiring and the upper surface to form a flat contact surface over the sensing region or the component region, wherein The wafer includes a substrate and an insulating layer, wherein the first sidewall of the first recess abuts the insulating layer, the second sidewall of the second recess abuts the substrate, and the encapsulation layer is in the sensing region or The thickness of the cover on the component area is determined by the difference between the distance between the highest portion of the wire and the first bottom of the first recess and the depth of the first recess. The method of manufacturing a chip package according to claim 21, wherein the first bottom has a lateral width narrower than the second bottom, and the redistribution layer extends to the second sidewall of the second recess and The second bottom portion, and the first end of the wiring is electrically connected to the redistribution layer on the second bottom. The method of manufacturing a chip package according to claim 24, further comprising forming an encapsulation layer covering at least the wiring, wherein the wafer comprises a substrate and an insulating layer, wherein the first recess The sidewall abuts the insulating layer and a portion of the substrate, the second sidewall of the second recess abuts the substrate, and the thickness of the encapsulation layer is determined by the highest portion of the wiring and the second recess The difference between the distance between the two bottoms and the depth of the shallow groove structure. The method of manufacturing a chip package according to claim 25, wherein the wafer is a fingerprint identification wafer. The method of manufacturing a chip package according to claim 26, further comprising forming a protective layer covering the redistribution layer and forming an opening in the second recess for the first end of the wiring The redistribution layer is electrically connected. The method of manufacturing a chip package according to claim 27, wherein the signal pad region is covered by the protective layer. The method of manufacturing a chip package according to claim 27, wherein the second end of the wiring is a starting point of soldering. The method of manufacturing a chip package according to claim 29, wherein the redistribution layer does not extend to an edge of the second recess. The method of manufacturing a chip package according to claim 19, further comprising forming an encapsulation layer covering the wiring and the upper surface to form a flat contact surface over the sensing region or the component region, wherein The first end of the wiring and the second end are lower than the upper surface of the wafer, and a highest portion of the wiring protrudes from the upper surface of the wafer, and the encapsulation layer is in the sensing region or the component region The thickness of the overlay is determined by the difference between the distance between the highest portion of the wiring and the bottom of the shallow groove structure and the depth of the shallow groove structure. A chip package includes: a wafer having an upper surface, a lower surface, and a sidewall, wherein the wafer includes a sensing region or component region and a signal pad region on the upper surface; and a shallow groove structure An outer side of the signal pad region and extending along the sidewall from the upper surface toward the lower surface, wherein the shallow groove structure has at least a first recess and a second recess, and the second recess is located at the bottom Below the first recess; a wiring layer electrically connected to the signal pad region and extending to the shallow groove structure; a wire having a first end point and a second end point, wherein the first end point is electrically charged in the shallow groove structure Connecting the redistribution layer to the external electrical connection, wherein the wafer comprises a semiconductor substrate and an insulating layer, the sidewall of the first recess abuts the insulating layer, and the sidewall of the second recess Adjacent to the semiconductor substrate, the bottom of the first recess exposes a surface of the semiconductor substrate; and an encapsulation layer covers at least the wiring. A chip package includes: a wafer having an upper surface, a lower surface, and a sidewall, wherein the wafer includes a sensing region or component region and a signal pad region on the upper surface; and a shallow groove structure An outer side of the signal pad region and extending along the sidewall from the upper surface toward the lower surface, wherein the shallow groove structure has at least a first recess and a second recess, and the second recess is located at the bottom a first wiring layer having a first terminal and a second portion; a wiring layer electrically connected to the signal pad region and extending to the sidewalls and the bottom of the first recess and the second recess; An end point, wherein the first end is electrically connected to the redistribution layer at a bottom of the second recess, the second end is used for external electrical connection, and wherein a lateral width of the bottom of the first recess is narrow a lateral width at the bottom of the second recess; and an encapsulation layer covering at least the wiring. A chip package comprising: a wafer having an upper surface, a lower surface and a sidewall, wherein the wafer includes a sensing region or component region and a signal pad region on the upper surface; and a shallow groove structure outside the signal pad region And extending along the sidewall from the upper surface toward the lower surface, wherein the shallow groove structure has at least a first recess and a second recess, and the second recess is located below the first recess; a wiring layer electrically connected to the signal pad region and extending to the shallow groove structure; a wire having a first end point and a second end point, wherein the first end point is electrically in the shallow groove structure Connecting the redistribution layer, the second terminal is for external electrical connection, wherein one portion of the wiring is higher than the upper surface of the wafer; and an encapsulation layer covering at least the wiring.