CN204045565U - Wafer encapsulation body - Google Patents

Wafer encapsulation body Download PDF

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Publication number
CN204045565U
CN204045565U CN201420411731.0U CN201420411731U CN204045565U CN 204045565 U CN204045565 U CN 204045565U CN 201420411731 U CN201420411731 U CN 201420411731U CN 204045565 U CN204045565 U CN 204045565U
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CN
China
Prior art keywords
recess
wafer
layer
wiring
end points
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn - After Issue
Application number
CN201420411731.0U
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Chinese (zh)
Inventor
何彦仕
刘沧宇
张恕铭
黄玉龙
林超彦
孙唯伦
陈键辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XinTec Inc
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XinTec Inc
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Filing date
Publication date
Priority claimed from US13/950,101 external-priority patent/US8952501B2/en
Application filed by XinTec Inc filed Critical XinTec Inc
Application granted granted Critical
Publication of CN204045565U publication Critical patent/CN204045565U/en
Withdrawn - After Issue legal-status Critical Current
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The utility model discloses a kind of wafer encapsulation body, comprises a wafer, has upper surface, lower surface and sidewall, and wherein wafer comprises a sensing area or element region and a signal bonding pad district in upper surface.One shallow grooves structure, is positioned at outside signal bonding pad district, and extends towards lower surface from upper surface along sidewall.Shallow grooves structure at least has one first recess and one second recess, and the second recess is positioned at below the first recess.One floor that reroutes is electrically connected signal bonding pad district and extend to shallow grooves structure.One wiring, has the first end points and the second end points, and wherein the first end points is electrically connected the layer that reroutes in shallow grooves structure, and the second end points is used for exposed electrical and connects.The utility model can reduce the cladding thickness of the encapsulated layer in wafer encapsulation body, increases the susceptibility of sensing area, and can maintain the structural strength of substrate.

Description

Wafer encapsulation body
Technical field
The utility model has about a kind of wafer package technology, has been in particular about a kind of wafer encapsulation body.
Background technology
Wafer encapsulation procedure forms the important step in electronic product process.Wafer encapsulation body except by wafer protection in wherein, make it from outside external environmental, inner wafer electronic component and extraneous electric connection path be also provided.
Tradition has the wafer encapsulation body of sensing function, as Fig. 4 the fingerprint identifying chip packaging body that discloses, that fingerprint identifying chip 520 is placed on printed circuit board (PCB) 510, and be soldered on printed circuit board (PCB) 510 by many wiring 530 from the connection pad district of wafer 520 upper surface, cover fingerprint identifying chip 520 with encapsulated layer 540 more afterwards.The height outstanding due to wiring 530 makes the thickness of encapsulated layer 540 to reduce, in order to avoid affecting the susceptibility of sensing area 523 because encapsulated layer 540 is too thick, surrounding's side height of the fingerprint identifying chip 520 after encapsulation is designed to the sensing area 523 higher than central authorities, therefore cannot form flat surfaces.In addition, because wiring 530 is adjacent to the edge of fingerprint identifying chip 520, therefore easily in welding process, causing short circuit or broken string because touching Waffer edge, causing yield to decline.
Therefore, be necessary the wafer encapsulation body seeking a kind of novelty, to reduce the thickness of encapsulated layer, and then promote the sensing sensitivity of wafer encapsulation body, and a kind of wafer encapsulation body with flattening contact surface is provided.
Utility model content
The utility model embodiment provides a kind of wafer encapsulation body, comprises a wafer, has upper surface, lower surface and sidewall, and wherein wafer comprises a sensing area or element region and a signal bonding pad district in upper surface.One shallow grooves structure, is positioned at outside signal bonding pad district, and extends towards lower surface from upper surface along sidewall.Shallow grooves structure at least has one first recess and one second recess, and the second recess is positioned at below the first recess.One floor that reroutes is electrically connected signal bonding pad district and extend to shallow grooves structure.One wiring, has the first end points and the second end points, and wherein the first end points is electrically connected the layer that reroutes in shallow grooves structure, and the second end points is used for exposed electrical and connects.
According to wafer encapsulation body described in the utility model, preferably, this first recess has bottom a first side wall and one first, and this reroutes, layer extends to this first side wall of this first recess and this is bottom first.
According to wafer encapsulation body described in the utility model, preferably, this second recess extends towards this lower surface bottom first from this of this first recess, and wherein this second recess has bottom one second sidewall and one second.
According to wafer encapsulation body described in the utility model, preferably, this transverse width bottom first is wider than this bottom second, and this first end points of this wiring is electrically connected to and is positioned at this this bottom first and reroutes on layer.
According to wafer encapsulation body described in the utility model, preferably, this layer that reroutes extends to this second sidewall of this second recess from this upper surface and this is bottom second.
According to wafer encapsulation body described in the utility model, preferably, this transverse width bottom first is narrower than this bottom second, and this first end points of wherein this wiring is electrically connected to and is positioned at this this bottom second and reroutes on layer.
According to wafer encapsulation body described in the utility model, preferably, this wafer comprises a substrate and an insulating barrier, and wherein this first side wall of this first recess adjoins this substrate of this insulating barrier and part, this this substrate of the second adjacent sidewalls of this second recess.
According to wafer encapsulation body described in the utility model, preferably, also comprise an encapsulated layer, this encapsulated layer covers this wiring and this upper surface, and a flattening contact surface is formed above this sensing area or this element region, wherein this transverse width bottom first is wider than this bottom second, and this first end points of this wiring is electrically connected to and is positioned at this this bottom first and reroutes on layer, one highest portion of this wiring divides this upper surface protruding from this wafer, and the cladding thickness of this encapsulated layer on this sensing area or this element region be decided by this highest portion of this wiring divide and this of this first recess bottom first between distance and the difference of the degree of depth of this first recess.
According to wafer encapsulation body described in the utility model, preferably, this wafer is a biological identification wafer.
According to wafer encapsulation body described in the utility model, preferably, also comprise an encapsulated layer, this encapsulated layer covers this wiring and this upper surface, and a flattening contact surface is formed above this sensing area or this element region, wherein this transverse width bottom first is narrower than this bottom second, this layer that reroutes also extends to this second sidewall of this second recess and this is bottom second, and this first end points of this wiring is electrically connected to and is positioned at this this bottom second and reroutes on layer, one highest portion of this wiring divides this upper surface protruding from this wafer, and the cladding thickness of this encapsulated layer on this sensing area or this element region be decided by this highest portion of this wiring divide and this of this second recess bottom second between distance and the difference of the degree of depth of this shallow grooves structure.
According to wafer encapsulation body described in the utility model, preferably, this layer that reroutes does not extend to the edge of this second recess.
According to wafer encapsulation body described in the utility model, preferably, also comprise a protective layer, this protective layer covers this layer that reroutes, and forms an opening in this shallow grooves structure, and this first end points for this wiring is electrically connected this layer that reroutes.
According to wafer encapsulation body described in the utility model, preferably, this signal bonding pad district is covered by this protective layer.
According to wafer encapsulation body described in the utility model, preferably, this second end points of this wiring is the starting point of welding.
According to wafer encapsulation body described in the utility model, preferably, this layer that reroutes does not extend to the edge of this shallow grooves structure.
According to wafer encapsulation body described in the utility model, preferably, this first end points of this wiring and this second end points are lower than this upper surface of this wafer, and a highest portion of this wiring divides this upper surface protruding from this wafer.
According to wafer encapsulation body described in the utility model, preferably, also comprise an encapsulated layer, this encapsulated layer covers this wiring and this upper surface, and a flattening contact surface is formed above this sensing area or this element region, wherein the cladding thickness of this encapsulated layer on this sensing area or this element region is decided by that this highest portion of this wiring divides the difference of the degree of depth of distance between the bottom of this shallow grooves structure and this shallow grooves structure.
The utility model embodiment provides a kind of wafer encapsulation body, comprises a wafer, has a upper surface, a lower surface and a sidewall, and wherein wafer comprises a sensing area or element region and a signal bonding pad district in upper surface.One shallow grooves structure is positioned at outside signal bonding pad district, and extends towards lower surface along sidewall from upper surface.Shallow grooves structure at least has one first recess and one second recess, and the second recess is positioned at below the first recess.One floor that reroutes is electrically connected signal bonding pad district and extend to shallow grooves structure.One wiring has one first end points and one second end points, and the first end points is electrically connected the layer that reroutes in shallow grooves structure, and the second end points is used for exposed electrical and connects.Wafer comprises semiconductor substrate and an insulating barrier, the adjacent sidewalls insulating barrier of the first recess, the adjacent sidewalls semiconductor base of the second recess, and the bottom-exposed of the first recess goes out the surface of semiconductor base.One encapsulated layer at least covers wiring.
The utility model embodiment provides a kind of wafer encapsulation body, comprises a wafer, has a upper surface, a lower surface and a sidewall, and wherein wafer comprises a sensing area or element region and a signal bonding pad district in upper surface.One shallow grooves structure is positioned at outside signal bonding pad district, and extends towards lower surface along sidewall from upper surface.Shallow grooves structure at least has one first recess and one second recess, and the second recess is positioned at below the first recess.One floor that reroutes is electrically connected signal bonding pad district and extends to sidewall and the bottom of the first recess and the second recess.One wiring has one first end points and one second end points, wherein the first end points is electrically connected in the bottom of the second recess the layer that reroutes, second end points is used for exposed electrical and connects, and wherein the transverse width of the bottom of the first recess is narrower than the transverse width of the bottom of the second recess.One encapsulated layer at least covers wiring.
The utility model embodiment provides a kind of wafer encapsulation body, comprises a wafer, has a upper surface, a lower surface and a sidewall, and wherein wafer comprises a sensing area or element region and a signal bonding pad district in upper surface.One shallow grooves structure is positioned at outside signal bonding pad district, and extends towards lower surface along sidewall from upper surface.Shallow grooves structure at least has one first recess and one second recess, and the second recess is positioned at below the first recess.One floor that reroutes is electrically connected signal bonding pad district and extend to shallow grooves structure.One wiring has one first end points and one second end points, and the first end points is electrically connected the layer that reroutes in shallow grooves structure, and the second end points is used for exposed electrical and connects, and the part of wherein wiring is higher than the upper surface of wafer.One encapsulated layer at least covers wiring.
The utility model can reduce the cladding thickness of the encapsulated layer in wafer encapsulation body, increases the susceptibility of sensing area, and can maintain the structural strength of substrate.
Accompanying drawing explanation
Figure 1A to Fig. 1 F shows the generalized section of the manufacture method of the wafer encapsulation body according to the utility model one embodiment.
Fig. 2 to Fig. 3 shows the generalized section of the wafer encapsulation body according to the various embodiment of the utility model.
Fig. 4 illustrates the generalized section of conventional wafer packaging body.
Being simply described as follows of symbol in accompanying drawing:
100 wafers
100a upper surface
100b lower surface
120 wafer regions
140,260 insulating barriers
150 substrates
160 signal bonding pad districts
180,320,340 openings
200,523 sensing areas/element region
220 first recesses
220a the first side wall
Bottom 220b first
230 second recesses
230a second sidewall
Bottom 230b second
280 reroute layer
300 protective layers
360 adhesion coatings
380 outer members
400 connection pad districts
440,530 wiring
440a first end points
440b second end points
440c highest portion is divided
460,540 encapsulated layers
480 decorative layers
500 protective layers
510 printed circuit board (PCB)s
520 fingerprint identifying chips
D1, D2 degree of depth
H1 distance
The H2 degree of depth
H3 cladding thickness.
Embodiment
Making and the occupation mode of the utility model embodiment will be described in detail below.So it should be noted, the utility model provides many creation concepts for application, and it can multiple specific pattern be implemented.In literary composition illustrate discuss specific embodiment be only manufacture with use ad hoc fashion of the present utility model, be not used to limit scope of the present utility model.In addition, label or the sign of repetition may be used in different embodiments.These repeat only clearly to describe the utility model in order to simple, do not represent between discussed different embodiment and/or structure and have any association.Moreover, when address one first material layer to be positioned on one second material layer or on time, comprise the first material layer directly contacted or to be separated with one or more other materials layer situation with the second material layer.
The wafer encapsulation body of the utility model one embodiment can in order to encapsulate sensing wafer, the biological identification wafers such as such as fingerprint identifier.So its application is not limited thereto, such as in the embodiment of wafer encapsulation body of the present utility model, it can be applicable to variously comprise active element or passive component (active or passive elements), the electronic component (electronic components) of the integrated circuits such as digital circuit or analog circuit (digital or analog circuits), such as relate to photoelectric cell (opto electronic devices), MEMS (micro electro mechanical system) (Micro Electro Mechanical System, MEMS), microfluid system (micro fluidic systems), or utilize heat, light, the physics sensor (Physical Sensor) that the physical quantity variation such as electric capacity and pressure is measured.Particularly can choice for use wafer-level packaging (wafer scale package, WSP) part or all of processing procedure is to Image Sensor, light-emitting diode (light-emitting diodes, LEDs), solar cell (solar cells), radio-frequency (RF) component (RF circuits), accelerometer (accelerators), gyroscope (gyroscopes), micro-brake (micro actuators), surface acoustic wave element (surface acoustic wave devices), the semiconductor wafers such as pressure sensor (process sensors) or ink gun (ink printer heads) encapsulate.
Wherein above-mentioned wafer-level packaging processing procedure mainly refers to after wafer stage completes encapsulation step, cut into independently packaging body again, but, in a specific embodiment, such as the semiconductor wafer redistribution be separated is carried on wafer one, carry out encapsulation procedure again, also can be referred to as wafer-level packaging processing procedure.In addition, above-mentioned wafer-level packaging processing procedure is also applicable to the more wafers by stacking (stack) mode arrangement with integrated circuit, to form the wafer encapsulation body of multilevel integration (multi-layer integrated circuit devices).
Please refer to Fig. 1 F, it shows the generalized section of the wafer encapsulation body according to the utility model one embodiment.In the present embodiment, wafer encapsulation body comprises wafer 100, shallow grooves structure, an outer member 380 and a wiring (wire) 440.Wafer 100 has a upper surface 100a and a lower surface 100b.In one embodiment, wafer 100 comprises the insulating barrier 140 and the substrate below it 150 that are adjacent to upper surface 100a, generally speaking, insulating barrier 140 can be made up of interlayer dielectric layer (ILD), metal intermetallic dielectric layer (IMD) and the passivation layer (passivation) covered.In the present embodiment, insulating barrier 140 can comprise inorganic material, such as silica, silicon nitride, silicon oxynitride, metal oxide or aforesaid combination, or other insulating material be applicable to.In the present embodiment, substrate 150 can comprise silicon or other semi-conducting materials.
In the present embodiment, wafer 100 comprises a signal bonding pad district 160 and a sensing area or element region 200, and it can be adjacent to upper surface 100a, illustrates below for sensing area.In one embodiment, signal bonding pad district 160 comprises multiple conductive pad, can be single conductive layer or has the conductive coating structure of multilayer.For simplicity of illustration, only illustrate using single conductive layer as example, and the conductive pad only shown in insulating barrier 140 illustrates as example herein.In the present embodiment, in insulating barrier 140, one or more opening 180 can be comprised, expose corresponding conductive pad.
In one embodiment, the sensing area 200 of wafer 100 includes a sensing element.Such as one biological sensing wafer, its sensing element can in order to sense biological characteristic.In another embodiment, wafer 100 in order to sensitive context feature, such as, can comprise a temperature sensor, a moisture sensing element, a pressure sensing element, a capacitance sensing element or other sensing elements be applicable to.In another embodiment, sensing wafer 100 can comprise an Image Sensor.In one embodiment, the sensing element in sensing wafer 100 is electrically connected with conductive pad by the internal connection-wire structure in insulating barrier 140.
In one embodiment, shallow grooves structure is made up of one first recess 220, is positioned at outside signal bonding pad district 160, and extends towards lower surface 100b along wafer 100 sidewall from upper surface 100a, and the first recess 220 comprises 220b bottom a first side wall 220a and one first.In one embodiment, the first side wall 220a of the first recess 220 adjoins insulating barrier 140 and the substrate 150 exposed below it.In the present embodiment, the degree of depth D1 (being shown in Figure 1B) of the first recess 220 is not more than 15 microns.In one embodiment, the first recess 220 formed by etching isolation layer 140, its sidewall 220a is haply perpendicular to upper surface 100a, and for example, the angle between the first side wall 220a of the first recess 220 and upper surface 100a can be approximately the scope of 84 ° to 90 °.In addition, in another embodiment, the scope of 55 ° to 90 ° can be approximately by the angle cut between the first side wall 220a of the first recess 220, first recess 220 that insulating barrier 140 is formed and upper surface 100a.
In one embodiment, can selecting, an insulating barrier 260 is set and is arranged on the upper surface 100a of wafer 100 with compliance, and extend to 220b bottom the first side wall 220a and first in the first recess 220, and expose the signal bonding pad district 160 of part.In the present embodiment, insulating barrier 260 can comprise inorganic material, such as silica, silicon nitride, silicon oxynitride, metal oxide or aforesaid combination, or other insulating material be applicable to.
The layer that reroutes (redistribution layer, RDL) 280 of one patterning, bottom the first side wall 220a and first that compliance extends to opening 180 and the first recess 220 on 220b.The floor 280 that reroutes can be electrically connected to signal bonding pad district 160 via opening 180.In one embodiment, the layer 280 that reroutes is arranged on insulating barrier 260, therefore can avoid with substrate 150 in electrical contact.In one embodiment, the layer 280 that reroutes can comprise copper, aluminium, gold, platinum, nickel, tin, aforesaid combination, conducting polymer composite, conducting ceramic material (such as, tin indium oxide or indium zinc oxide) or other electric conducting materials be applicable to.
One protection (protection) layer 300 compliance is arranged at and reroutes on layer 280 and insulating barrier 260, and extends in the first recess 220.Comprise one or more opening in protective layer 300, expose a part for the layer 280 that reroutes.In the present embodiment, in protective layer 300, comprise opening 320 and 340, expose the floor 280 that reroutes in signal bonding pad district 160 and the first recess 220 respectively.In other embodiments, can only comprise opening 340 in protective layer 300, such as, the opening 320 in signal bonding pad district 160 be covered.In the present embodiment, protective layer 300 can comprise inorganic material, such as, and silica, silicon nitride, silicon oxynitride, metal oxide or aforesaid combination, or other insulating material be applicable to.
Outer member 380 can be a substrate, is attached on the lower surface 100b of wafer 100 by an adhesion coating (glue (glue) of such as, adhering) 360.In the present embodiment, outer member 380 can be circuit board, wafer or intermediary layer (interposer).For circuit board, its surface can have one or more connection pad district 400.
Wiring 440 has the first end points 440a and the second end points 440b, wherein, first end points 440a is electrically connected the layer that reroutes in shallow grooves structure, and the second end points 440b is then for the electric connection of outer member, and a part for wiring 440 protrudes from upper wafer surface 100a.For example, wiring 440 is electrically connected the connection pad district 400 of circuit board 380 by the second end points 440b, and by the first end points 440a be electrically connected the first recess 220 first bottom the layer 280 that reroutes on 220b, the highest portion of wherein wiring 440 divides 440c to protrude from upper wafer surface 100a.Though the present embodiment protrudes from upper wafer surface 100a for a part for wiring 440, it is not as limit, wiring 440 also can be made lower than upper surface 100a in embodiments by shallow grooves structure.
In the present embodiment, wafer encapsulation body also can comprise an encapsulated layer (encapsulant) 460, its alternative (optionally) covers wiring 440, shallow grooves structure or extends on upper wafer surface 100a, to form a flattening contact surface above sensing area 200.Encapsulated layer (encapsulant) 460 is generally by moulding material (molding material) or encapsulant (sealing material) is formed.
In one embodiment, decorative layer 480 can be set in addition on encapsulated layer 460, and color can be had according to design requirement, to show the region with sensing function.Protective layer (such as; sapphire substrates or hard plastic glue (hard rubber)) 500 items can be arranged in addition on decorative layer 480; to provide the surface of wear-resisting, scratch resistant and high-reliability further, and then sensing apparatus in the process of the sensing function using wafer encapsulation body is avoided to be polluted or destroy.
According to above-described embodiment of the present utility model, the highest portion of wiring 440 divide 440c and shallow grooves structure bottom (that is, first recess 220 first bottom 220b) between there is a distance H1, and shallow grooves structure has a depth H 2 (that is, the degree of depth D1 of the first recess 220).In the cladding thickness H3 of sensing area 200, encapsulated layer 460 is decided by that the highest portion of wiring 440 divides the difference (H1-H2) of the depth H 2 of distance H1 between the bottom of 440c and shallow grooves structure and shallow grooves structure.Therefore by the depth H 2 of adjustment shallow grooves structure, the cladding thickness of encapsulated layer 460 can be reduced, increase the susceptibility of sensing area, form the contact surface of flattening simultaneously.In addition, because this kind of shallow grooves structure does not need to remove too much base material, the structural strength of substrate can therefore be maintained.
Please refer to Fig. 2 to Fig. 3, it shows the generalized section of the wafer encapsulation body according to the various embodiment of the utility model, and the parts be wherein same as in Fig. 1 F use identical label and the description thereof will be omitted.The structure of the wafer encapsulation body of similar in Fig. 1 F of the wafer encapsulation body in Fig. 2, difference is that in Fig. 2, wafer encapsulation body also comprises one second recess 230, bottom first of the first recess 220,220b extends towards lower surface, second recess 230 has 230b bottom one second sidewall 230a and one second, wherein the second sidewall 230a adjacent substrate 150 of the second recess 230.First recess 220 on upper strata is narrower than at the transverse width of the second recess 230 of lower floor.In one embodiment, insulating barrier 260 extend to the second recess 230 the second sidewall 230a and second bottom 230b.
In the present embodiment, the highest portion of wiring 440 has a distance H1 between 220b bottom dividing first of 440c and the first recess 220.In the cladding thickness H3 of sensing area 200, encapsulated layer 460 is decided by that the highest portion of wiring 440 divides the difference (H1-D1) of the degree of depth D1 of distance H1 between the bottom of 440c and shallow grooves structure and the first recess 220.
In the present embodiment, first end points 440a upper strata first in electrical contact recess 220 of wiring 440 first bottom the layer 280 that reroutes on 220b, therefore except reducing further except the maximum height of wiring 440, also due to the second recess 230 add wiring 440 and the first recess 220 first bottom the spacing of 220b, therefore can reduce wiring because touching the first recess 220 edge the probability of short circuit or broken string.
The structure of the wafer encapsulation body of similar in Fig. 2 of the wafer encapsulation body in Fig. 3, difference is in Fig. 3 at first recess 220 of the transverse width of the second recess 230 of lower floor wider than upper strata, simultaneously, 230b bottom the second sidewall 230a and second that the layer 280 that reroutes extends to the second recess 230 of lower floor further, the reroute layer 280 of the first end points 440a then bottom second of the second recess 230 of opening 340 lower floor in electrical contact on 230b of wiring 440.In addition, first recess 220 on upper strata runs through outside insulating barrier 140, also may extend in the substrate 150 below it.
In the present embodiment, the highest portion of wiring 440 divide 440c and shallow grooves structure bottom (that is, second recess 230 second bottom 230b) between there is a distance H1, and shallow grooves structure has a depth H 2 (that is the degree of depth D1 of the first recess 220 adds the degree of depth D2 of the second recess 230).In the cladding thickness H3 of sensing area 200, encapsulated layer 460 is decided by that the highest portion of wiring 440 divides the difference (H1-H2) of the depth H 2 of distance H1 between the bottom of 440c and shallow grooves structure and shallow grooves structure.
In the present embodiment, the second recess 230 is utilized to extend in substrate 150 further, therefore, it is possible to reduce the maximum height of wiring 440 further, but more do not affect the structural strength of substrate, and the undercut phenomenon directly causing insulating barrier 140 and substrate 150 interface with the first recess 220 to the over etching caused by downward-extension can be avoided.
In other embodiments, wiring 440 to be rerouted for starting point is soldered on layer 280 with the second end points 440b and is formed the first end points 440a.
Below coordinate Figure 1A to Fig. 1 F that the manufacture method of the wafer encapsulation body of the utility model one embodiment is described, wherein Figure 1A to Fig. 1 F shows the generalized section of the manufacture method of the wafer encapsulation body according to the utility model one embodiment.
Please refer to Figure 1A, provide the wafer that has a wafer region 120, wafer region 120 comprises multiple wafer 100, and each wafer 100 has a upper surface 100a and a lower surface 100b.In one embodiment, wafer comprises substrate 150 and is adjacent to the insulating barrier 140 of upper surface 100a, generally speaking, insulating barrier 140 can be made up of interlayer dielectric layer (ILD), metal intermetallic dielectric layer (IMD) and the passivation layer (passivation) covered.In the present embodiment, insulating barrier 140 can comprise inorganic material such as, silica, silicon nitride, silicon oxynitride, metal oxide or aforesaid combination or other insulating material be applicable to.In the present embodiment, substrate 150 can comprise silicon or other semi-conducting materials.
In the present embodiment, comprise one or more signal bonding pad district 160 in each wafer, it can be adjacent to upper surface 100a and comprise multiple conductive pad.For simplicity of illustration, only show single wafer district 120 herein and be positioned at a conductive pad of insulating barrier 140.In one embodiment, conductive pad can be single conductive layer or has the conductive coating structure of multilayer.Herein, only illustrate using single conductive layer as example.In the present embodiment, in insulating barrier 140, one or more opening 180 can be comprised, expose corresponding conductive pad.
In the present embodiment, have a sensing area or element region 200 in each wafer 100, it can be adjacent to upper surface 100a.In one embodiment, sensing area 200 in order to sense biological characteristic, such as, can comprise an identification of fingerprint element.In another embodiment, sensing area 200 in order to sensitive context feature, and can comprise a temperature sensor, a moisture sensing element, a pressure sensing element, a capacitance sensing element or other sensing elements be applicable to.In another embodiment, sensing area 200 can comprise an Image Sensor.In one embodiment, the sensing element in sensing area 200 is electrically connected with conductive pad by the internal connection-wire structure in insulating barrier 140.
Please refer to Figure 1B, by micro-photographing process and etch process (such as, dry ecthing procedure, wet etching processing procedure, plasma etching process, reactive ion etching processing procedure or other processing procedures be applicable to), shallow grooves structure is formed at the sidewall of each wafer 100, such as in insulating barrier 140, form the first recess 220, it extends towards lower surface 100b along Cutting Road (not illustrating) from upper surface 100a, and the substrate 150 running through insulating barrier 140 and expose below it, that is the degree of depth of the first recess 220 approximates the thickness or darker of insulating barrier 140.In the present embodiment, the degree of depth D1 of the first recess 220 is not more than 15 microns.In one embodiment, the first side wall 220a of the first recess 220 formed with etch process is haply perpendicular to upper surface 100a.For example, the angle between the sidewall of the first recess 220 and upper surface 100a can be approximately the scope of 84 ° to 90 °.In another embodiment, upper surface 100a is favoured haply with the sidewall cutting the first recess 220 that processing procedure is formed.For example, the angle between the sidewall of the first recess 220 and upper surface 100a can be approximately the scope of 55 ° to 90 °.
Please refer to Fig. 1 C, by deposition manufacture process (such as, coating process, physical vapour deposition (PVD) processing procedure, chemical vapor deposition process or other processing procedures be applicable to), on the upper surface 100a of wafer 100, compliance forms an insulating barrier 260, in its opening 180 extending to insulating barrier 140 and the first recess 220.In the present embodiment, insulating barrier 260 can comprise inorganic material such as, silica, silicon nitride, silicon oxynitride, metal oxide or aforesaid combination or other insulating material be applicable to.
Then, by micro-photographing process and etch process (such as, dry ecthing procedure, wet etching processing procedure, plasma etching process, reactive ion etching processing procedure or other processing procedures be applicable to), remove the insulating barrier 260 in opening 180, to expose the signal bonding pad district 160 of part.Then, by deposition manufacture process (such as, coating process, physical vapour deposition (PVD) processing procedure, chemical vapor deposition process, electroplating process, electroless plating processing procedure or other processing procedures be applicable to), micro-photographing process and etch process, insulating barrier 260 is formed the layer 280 that reroutes of a patterning.
Bottom the first side wall 220a and first that layer 280 compliance that reroutes extends to opening 180 and the first recess 220 on 220b, and can be electrically connected via opening 180 the connection pad district 160 exposed.In one embodiment, the layer 280 that reroutes do not extend to the first recess 220 first bottom 220b edge.Moreover when substrate 150 comprises semi-conducting material, the layer 280 that reroutes is by insulating barrier 260 electrical isolation.In one embodiment, the layer 280 that reroutes can comprise copper, aluminium, gold, platinum, nickel, tin, aforesaid combination, conducting polymer composite, conducting ceramic material (such as, tin indium oxide or indium zinc oxide) or other electric conducting materials be applicable to.
Please refer to Fig. 1 D; by deposition manufacture process (such as; coating process, physical vapour deposition (PVD) processing procedure, chemical vapor deposition process or other processing procedures be applicable to), rerouting, compliance on layer 280 and insulating barrier 260 forms a protective layer 300, and it extends in the first recess 220.In the present embodiment, protective layer 300 can comprise inorganic material such as, silica, silicon nitride, silicon oxynitride, metal oxide or aforesaid combination or other insulating material be applicable to.
Then; by micro-photographing process and etch process (such as; dry ecthing procedure, wet etching processing procedure, plasma etching process, reactive ion etching processing procedure or other processing procedures be applicable to); in protective layer 300, form one or more opening, expose a part for the layer 280 that reroutes.In the present embodiment, opening 320 and 340 is formed in protective layer 300, to expose the layer 280 that reroutes in opening 180 and the first recess 220 respectively.
In other embodiments, opening 340 can only be formed in protective layer 300.Be understandable that, quantity and the position of the opening in protective layer 300 are depended on design requirement and are not limited to this.
Then, along Cutting Road (not illustrating), cutting processing procedure is carried out to wafer, to form plural number independently wafer 100.After carrying out cutting processing procedure, the first recess 220 of each wafer extends towards lower surface 100b along sidewall from upper surface 100a.
Please refer to Fig. 1 E, by an adhesion coating (such as, adhesion glue) 360, an outer member 380 is attached on the lower surface 100b of substrate 150 in independently wafer.In the present embodiment, outer member 380 can be circuit board, wafer or intermediary layer.For circuit board, in outer member 380, one or more connection pad district 400 can be had.Similarly, connection pad district 400 can comprise multiple conductive pad, and conductive pad can be single conductive layer or has the conductive coating structure of multilayer.For simplicity of illustration, only illustrate using single conductive layer as example, and the conductive pad only showing a connection pad district 400 illustrates as example herein.
Then, by welding (Wire Bonding) processing procedure, with the second end points 440b that the connection pad district 400 of outer member 380 is initial, form a wiring 440 and with the first end points 440a be electrically connected the first recess 220 first bottom the layer 280 that reroutes on 220b.In the present embodiment, wiring 440 has a highest portion and divides 440c, itself and the first recess 220 first bottom the distance of 220b be H1.In the present embodiment, wiring 440 can comprise gold or other electric conducting materials be applicable to.
In another embodiment, as shown in Figure 2, its difference is to remove part of substrate formation one second recess 230 by etching or cut processing procedure, its 220b bottom first of the first recess 220 extends towards lower surface, second recess 230 has 230b bottom the second sidewall 230a and second, wherein the second sidewall 230a adjacent substrate 150 of the second recess 230, and first recess 220 on upper strata is narrower than at the transverse width of the second recess 230 of lower floor.In one embodiment, insulating barrier 260 extend to the second recess 230 the second sidewall 230a and second bottom 230b.
In the present embodiment, the layer 280 that reroutes on bottom first end points 440a upper strata first in electrical contact recess 220 of wiring 440, therefore except reducing further except the maximum height of wiring 440, also due to the second recess 230 add wiring 440 and the first recess 220 first bottom the spacing of 220b, therefore can reduce wiring because touching the first recess 220 edge the probability of short circuit or broken string.
Again in another embodiment, the structure of the wafer encapsulation body of similar in Fig. 2 of the wafer encapsulation body in Fig. 3, difference is to make transverse width at the second recess 230 of lower floor wider than first recess 220 on upper strata by etching or cut processing procedure, simultaneously, 230b bottom the second sidewall 230a and second that the layer 280 that reroutes extends to the second recess 230 of lower floor further, but do not extend to bottom margin.The reroute layer 280 of the first end points 440a then bottom second of the second recess 230 of opening 340 lower floor in electrical contact on 230b of wiring 440.
In the present embodiment, because the second recess 230 extends in substrate 150 further, therefore, it is possible to reduce the maximum height of wiring 440 further, but more do not affect the structural strength of substrate, and can avoid directly etching first recess 220 on upper strata and cause the undercut phenomenon of insulating barrier 140 and substrate 150 interface because of over etching.
Please refer to Fig. 1 F, by molded (molding) processing procedure or other processing procedures be applicable to, upper wafer surface 100a is formed an encapsulated layer 460, its alternative covers the first recess 220, outer member 380, wiring 440 or extends to upper wafer surface 100a, forms a flattening contact surface above sensing area 200.
Then, by deposition manufacture process (such as, coating process or other processing procedures be applicable to), encapsulated layer 460 is formed a decorative layer 480, and it can have color according to design requirement, to show the region with sensing function.Then; by deposition manufacture process (such as; coating process, physical vapour deposition (PVD) processing procedure, chemical vapor deposition process or other processing procedures be applicable to); decorative layer 480 forms a protective layer (such as; sapphire substrates or hard plastic glue) 500, to provide the surface of wear-resisting, scratch resistant and high-reliability further.
The foregoing is only the utility model preferred embodiment; so itself and be not used to limit scope of the present utility model; anyone familiar with this technology; not departing from spirit and scope of the present utility model; can do on this basis and further improve and change, the scope that therefore protection range of the present utility model ought define with claims of the application is as the criterion.

Claims (21)

1. a wafer encapsulation body, is characterized in that, comprising:
One wafer, has a upper surface, a lower surface and a sidewall, and wherein this wafer comprises a sensing area or an element region and a signal bonding pad district in this upper surface;
One shallow grooves structure, is positioned at outside this signal bonding pad district, and extends towards this lower surface from this upper surface along this sidewall, and wherein this shallow grooves structure at least has one first recess and one second recess, and this second recess is positioned at below this first recess;
One reroutes layer, is electrically connected this signal bonding pad district and extends to this shallow grooves structure; And
One wiring, have one first end points and one second end points, wherein this first end points is electrically connected this layer that reroutes in this shallow grooves structure, and this second end points is used for exposed electrical and connects.
2. wafer encapsulation body according to claim 1, is characterized in that, this first recess has bottom a first side wall and one first, and this reroutes, layer extends to this first side wall of this first recess and this is bottom first.
3. wafer encapsulation body according to claim 2, is characterized in that, this second recess extends towards this lower surface bottom first from this of this first recess, and wherein this second recess has bottom one second sidewall and one second.
4. wafer encapsulation body according to claim 3, is characterized in that, this transverse width bottom first is wider than this bottom second, and this first end points of this wiring is electrically connected to and is positioned at this this bottom first and reroutes on layer.
5. wafer encapsulation body according to claim 3, is characterized in that, this layer that reroutes extends to this second sidewall of this second recess from this upper surface and this is bottom second.
6. wafer encapsulation body according to claim 5, is characterized in that, this transverse width bottom first is narrower than this bottom second, and this first end points of wherein this wiring is electrically connected to and is positioned at this this bottom second and reroutes on layer.
7. wafer encapsulation body according to claim 3, is characterized in that, this wafer comprises a substrate and an insulating barrier, and wherein this first side wall of this first recess adjoins this substrate of this insulating barrier and part, this this substrate of the second adjacent sidewalls of this second recess.
8. wafer encapsulation body according to claim 7, it is characterized in that, also comprise an encapsulated layer, this encapsulated layer covers this wiring and this upper surface, and a flattening contact surface is formed above this sensing area or this element region, wherein this transverse width bottom first is wider than this bottom second, and this first end points of this wiring is electrically connected to and is positioned at this this bottom first and reroutes on layer, one highest portion of this wiring divides this upper surface protruding from this wafer, and the cladding thickness of this encapsulated layer on this sensing area or this element region be decided by this highest portion of this wiring divide and this of this first recess bottom first between distance and the difference of the degree of depth of this first recess.
9. wafer encapsulation body according to claim 8, is characterized in that, this wafer is a biological identification wafer.
10. wafer encapsulation body according to claim 7, it is characterized in that, also comprise an encapsulated layer, this encapsulated layer covers this wiring and this upper surface, and a flattening contact surface is formed above this sensing area or this element region, wherein this transverse width bottom first is narrower than this bottom second, this layer that reroutes also extends to this second sidewall of this second recess and this is bottom second, and this first end points of this wiring is electrically connected to and is positioned at this this bottom second and reroutes on layer, one highest portion of this wiring divides this upper surface protruding from this wafer, and the cladding thickness of this encapsulated layer on this sensing area or this element region be decided by this highest portion of this wiring divide and this of this second recess bottom second between distance and the difference of the degree of depth of this shallow grooves structure.
11. wafer encapsulation bodies according to claim 10, is characterized in that, this wafer is a fingerprint identifying chip.
12. wafer encapsulation bodies according to claim 10, is characterized in that, this layer that reroutes does not extend to the edge of this second recess.
13. wafer encapsulation bodies according to claim 1, is characterized in that, also comprise a protective layer, and this protective layer covers this layer that reroutes, and form an opening in this shallow grooves structure, and this first end points for this wiring is electrically connected this layer that reroutes.
14. wafer encapsulation bodies according to claim 13, is characterized in that, this signal bonding pad district is covered by this protective layer.
15. wafer encapsulation bodies according to claim 1, is characterized in that, this second end points of this wiring is the starting point of welding.
16. wafer encapsulation bodies according to claim 1, is characterized in that, this layer that reroutes does not extend to the edge of this shallow grooves structure.
17. wafer encapsulation bodies according to claim 1, is characterized in that, this first end points of this wiring and this second end points are lower than this upper surface of this wafer, and a highest portion of this wiring divides this upper surface protruding from this wafer.
18. wafer encapsulation bodies according to claim 17, it is characterized in that, also comprise an encapsulated layer, this encapsulated layer covers this wiring and this upper surface, and a flattening contact surface is formed above this sensing area or this element region, wherein the cladding thickness of this encapsulated layer on this sensing area or this element region is decided by that this highest portion of this wiring divides the difference of the degree of depth of distance between the bottom of this shallow grooves structure and this shallow grooves structure.
19. 1 kinds of wafer encapsulation bodies, is characterized in that, comprising:
One wafer, has a upper surface, a lower surface and a sidewall, and wherein this wafer comprises a sensing area or an element region and a signal bonding pad district in this upper surface;
One shallow grooves structure, is positioned at outside this signal bonding pad district, and extends towards this lower surface from this upper surface along this sidewall, and wherein this shallow grooves structure at least has one first recess and one second recess, and this second recess is positioned at below this first recess;
One reroutes layer, is electrically connected this signal bonding pad district and extends to this shallow grooves structure;
One wiring, there is one first end points and one second end points, this first end points is electrically connected this layer that reroutes in this shallow grooves structure, this second end points is used for exposed electrical and connects, wherein this wafer comprises semiconductor substrate and an insulating barrier, this insulating barrier of the adjacent sidewalls of this first recess, this semiconductor base of the adjacent sidewalls of this second recess, and the bottom-exposed of this first recess goes out the surface of this semiconductor base; And
One encapsulated layer, at least covers this wiring.
20. 1 kinds of wafer encapsulation bodies, is characterized in that, comprising:
One wafer, has a upper surface, a lower surface and a sidewall, and wherein this wafer comprises a sensing area or an element region and a signal bonding pad district in this upper surface;
One shallow grooves structure, is positioned at outside this signal bonding pad district, and extends towards this lower surface from this upper surface along this sidewall, and wherein this shallow grooves structure at least has one first recess and one second recess, and this second recess is positioned at below this first recess;
One reroutes layer, is electrically connected this signal bonding pad district and extends to sidewall and the bottom of this first recess and this second recess;
One wiring, there is one first end points and one second end points, wherein this first end points is electrically connected this layer that reroutes in the bottom of this second recess, and this second end points is used for exposed electrical and connects, and wherein the transverse width of the bottom of this first recess is narrower than the transverse width of the bottom of this second recess; And
One encapsulated layer, at least covers this wiring.
21. 1 kinds of wafer encapsulation bodies, is characterized in that, comprising:
One wafer, has a upper surface, a lower surface and a sidewall, and wherein this wafer comprises a sensing area or an element region and a signal bonding pad district in this upper surface;
One shallow grooves structure, is positioned at outside this signal bonding pad district, and extends towards this lower surface from this upper surface along this sidewall, and wherein this shallow grooves structure at least has one first recess and one second recess, and this second recess is positioned at below this first recess;
One reroutes layer, is electrically connected this signal bonding pad district and extends to this shallow grooves structure;
One wiring, have one first end points and one second end points, this first end points is electrically connected this layer that reroutes in this shallow grooves structure, and this second end points is used for exposed electrical and connects, and the part of wherein this wiring is higher than this upper surface of this wafer; And
One encapsulated layer, at least covers this wiring.
CN201420411731.0U 2013-07-24 2014-07-24 Wafer encapsulation body Withdrawn - After Issue CN204045565U (en)

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US13/950,101 2013-07-24
US13/950,101 US8952501B2 (en) 2010-05-11 2013-07-24 Chip package and method for forming the same
US201462002774P 2014-05-23 2014-05-23
US62/002,774 2014-05-23

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TWI559495B (en) 2016-11-21
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CN104347576A (en) 2015-02-11
CN104347537B (en) 2017-05-17
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CN104347536A (en) 2015-02-11
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CN104347576B (en) 2017-06-09
TWI534969B (en) 2016-05-21

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