CN100552963C - Integrated circuit package body and preparation method thereof - Google Patents
Integrated circuit package body and preparation method thereof Download PDFInfo
- Publication number
- CN100552963C CN100552963C CN 200710091415 CN200710091415A CN100552963C CN 100552963 C CN100552963 C CN 100552963C CN 200710091415 CN200710091415 CN 200710091415 CN 200710091415 A CN200710091415 A CN 200710091415A CN 100552963 C CN100552963 C CN 100552963C
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- barricade
- chip
- bond pad
- package body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a kind of integrated circuit package body and preparation method thereof.The said integrated circuit packaging body comprises integrated circuit (IC) chip, and its upper surface is formed with photo-sensitive cell; Bond pad is formed at the upper surface of this integrated circuit (IC) chip, and is electrically connected this photo-sensitive cell; First barricade is formed between this photo-sensitive cell and this bond pad; And conductive layer, be formed on the sidewall of this integrated circuit (IC) chip, and be electrically connected this bond pad.First barricade of the present invention can stop the zone of sticker overflow to photo-sensitive cell, with the qualification rate of the manufacturing process of improving integrated circuit package body.
Description
Technical field
The present invention is particularly to a kind of integrated circuit package body with high qualification rate and preparation method thereof relevant for integrated circuit package body and preparation method thereof.
Background technology
In the manufacturing process of integrated circuit (IC) apparatus, integrated circuit is used in various application after must handling through encapsulation step, for example, and computer, mobile phone or digital camera etc.Therefore, the qualification rate of integrated circuit encapsulation also directly influences the qualification rate of final integrated circuit (IC) apparatus.
Figure 1A-Fig. 1 D shows the profile of existing integrated circuit encapsulation.Be presented at before the engagement step as Figure 1A and Figure 1B, protective layer 8 is formed at the form on the cover plate 4.And Fig. 1 C and Fig. 1 D are presented at before the engagement step, and protective layer 8 is formed at the form on the integrated circuit (IC) chip 2.In Figure 1A, shown that the top is formed with the integrated circuit (IC) chip 2 of photo-sensitive cell 12, and photo-sensitive cell 12 is electrically connected on bond pad 6.And for example shown in Figure 1A,, attach cover plate 4, and between cover plate 4 and integrated circuit (IC) chip 2, form gap 14 in the top of integrated circuit (IC) chip 2 by sticker 10.In the step of above-mentioned joint cover plate 4 and integrated circuit (IC) chip 2, sticker 10 meeting overflows are to the zone of photo-sensitive cell 12, shown in Figure 1A.Figure 1B show according among Figure 1A when the engagement step sticker overflow to the profile of the integrated circuit package body of photo-sensitive cell.In Figure 1B, sticker 10 can overflows to the zone of photo-sensitive cell 12, and cover part photo-sensitive cell 12, make 12 pairs of photo-sensitive cells from the external world through the light reaction in cover plate 4 and gap 14 and inconsistent, and cause integrated circuit package body defective.
Shown in Fig. 1 C, the integrated circuit (IC) chip 2 that provides the top to be formed with photo-sensitive cell 12 and bond pad 6, and protective mulch 8 is in the top of bond pad 6.Then, engage cover plate 4 on integrated circuit (IC) chip 2, and form gap 14 between cover plate 4 and integrated circuit (IC) chip.When above-mentioned engagement step, the zone that sticker 10 can be along the sidewall overflow of protective layer 8 to photo-sensitive cell 12 is shown in Fig. 1 C.Fig. 1 D show according among Fig. 1 C when the engagement step sticker overflow to the profile of the integrated circuit package body of photo-sensitive cell.Shown in Fig. 1 D, sticker 10 meeting overflows are to the zone of photo-sensitive cell 12, and cover part photo-sensitive cell 12, thereby cause the encapsulation qualification rate of integrated circuit package body to reduce.Thus, existing as can be known juncture all can cause above-mentioned problem.
Therefore, need a kind of integrated road packaging body and preparation method thereof badly, addressing the above problem, and improve the manufacturing process qualification rate of integrated circuit package body.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of integrated circuit package body.The said integrated circuit packaging body comprises integrated circuit (IC) chip, and its upper surface is formed with photo-sensitive cell; Bond pad is formed at the upper surface of this integrated circuit (IC) chip, and is electrically connected this photo-sensitive cell; Substrate is arranged on this integrated circuit (IC) chip, and and this integrated circuit (IC) chip between be separated with a gap; First barricade be formed between this photo-sensitive cell and this bond pad, and the height of this first barricade equals the width in this gap; And conductive layer, be formed on the sidewall of this integrated circuit (IC) chip, and be electrically connected this bond pad.
Aforesaid integrated circuit package body also comprises second barricade, between this bond pad and this first barricade.
Aforesaid integrated circuit package body, wherein the height of this second barricade is less than or equal to the height of this first barricade.
Aforesaid integrated circuit package body, wherein this second barricade is positioned on this integrated circuit (IC) chip.
Aforesaid integrated circuit package body, wherein this second barricade is positioned on the substrate, and this substrate is arranged at the top of this integrated circuit (IC) chip accordingly.
Aforesaid integrated circuit package body also comprises: protective layer coats this bond pad; And adhesion coating, be formed between this protective layer and this first barricade, and bonding this integrated circuit (IC) chip and this substrate.
Aforesaid integrated circuit package body also comprises the scolder spheroid, is formed on this conductive layer.
Another object of the present invention provides a kind of manufacture method of integrated circuit package body.The manufacture method of said integrated circuit packaging body comprises: provide upper surface to be formed with the integrated circuit (IC) chip of photo-sensitive cell; Substrate is provided, is arranged on this integrated circuit (IC) chip, and and this integrated circuit (IC) chip between be separated with a gap; Form bond pad on this integrated circuit package body, and be electrically connected this photo-sensitive cell; Form first barricade between this bond pad and this photo-sensitive cell, and the height of this first barricade equals the width in this gap; And form conductive layer on the sidewall of this integrated electrical chip, and be electrically connected this bond pad.The said integrated circuit packaging body also comprises by sticker, engages the top of first substrate in this integrated circuit (IC) chip.In the integrated circuit package body, it has barricade between bond pad and photo-sensitive cell according to an embodiment of the invention.
The manufacture method of aforesaid integrated circuit package body wherein forms the mode of this first barricade between this bond pad and this photo-sensitive cell, comprises this first barricade being set on this substrate; And, this substrate is attached on this integrated circuit (IC) chip, to form this first barricade between this bond pad and this photo-sensitive cell by adhesion coating.
The manufacture method of aforesaid integrated circuit package body also comprises second barricade being set on this substrate, and by attaching the step of this substrate in this integrated circuit (IC) chip top, to form this second barricade between this bond pad and this first barricade.
The manufacture method of aforesaid integrated circuit package body also comprises second barricade being set on this integrated circuit, and between this bond pad and this first barricade.
The manufacture method of aforesaid integrated circuit package body wherein forms the mode of this conductive layer, comprising: remove this integrated circuit (IC) chip of part and this protective layer, forming groove, and expose this bond pad; And form this conductive layer among this groove, be electrically connected this bond pad and this conductive layer extends on the lower surface of this integrated circuit (IC) chip.
The manufacture method of aforesaid integrated circuit package body also comprises forming the scolder spheroid on this conductive layer.
Therefore, when engagement step, barricade can stop the zone of sticker overflow to photo-sensitive cell.Moreover, owing between bond pad and photo-sensitive cell, be provided with barricade, make and can more precisely control position and the use amount that sticker forms, and then reduce cost of manufacture.
Description of drawings
Figure 1A-Fig. 1 D shows the profile of existing integrated circuit package body;
Fig. 2 A-Fig. 2 H shows the profile of the integrated circuit package body of making according to first embodiment of the invention;
Fig. 3 A-Fig. 3 B shows the profile of the integrated circuit package body of making according to second embodiment of the invention;
Fig. 4 A-Fig. 4 D shows the profile of the integrated circuit package body of making according to third embodiment of the invention; And
Fig. 5 A-Fig. 5 B shows the profile of the integrated circuit package body of making according to fourth embodiment of the invention.
Wherein, description of reference numerals is as follows:
Prior art
2～integrated circuit (IC) chip; 4～cover plate;
6～bond pad; 8～protective layer;
10～sticker; 12～photo-sensitive cell;
14～gap.
The present invention
102～integrated circuit (IC) chip; 103～upper surface;
104～photo-sensitive cell; 105～lower surface;
106～bond pad; 108～barricade;
110～the first substrates; 112～protective layer;
114～sticker; 116～gap;
118～opening; 120～glue material;
122～the second substrates; 124～insulating barrier;
126～groove; 128～conductive layer;
130～soldering-resistance layer; 132～scolder spheroid;
140～integrated circuit package body;
202～integrated circuit (IC) chip; 204～photo-sensitive cell;
206～bond pad; 208～the first barricades;
210～the second barricades; 212～the first substrates;
214～protective layer; 216～sticker;
218～gap; 220～glue material;
222～the second substrates; 224～insulating barrier;
226～conductive layer; 228～soldering-resistance layer;
230～scolder spheroid; 232～integrated circuit package body;
302～integrated circuit (IC) chip; 304～photo-sensitive cell;
306～bond pad; 308～protective layer;
310～sticker; 312～the first substrates;
314～barricade; 316～gap;
318～glue material; 320～the second substrates;
322～insulating barrier; 324～conductive layer;
326～soldering-resistance layer; 328～scolder spheroid;
330～integrated circuit package body;
402～integrated circuit (IC) chip; 404～photo-sensitive cell;
406～contact pad; 408～protective layer;
410～sticker; 412～the first substrates;
414～the first barricades; 416～the second barricades;
418～gap; 420～glue material;
422～the second substrates; 424～insulating barrier;
426～conductive layer; 428～soldering-resistance layer;
430～scolder spheroid; 432～Integrated electrode packaging body.
Embodiment
Next describe the present invention in detail with embodiment and conjunction with figs., at accompanying drawing or in describing, similar or same section uses identical symbol.In the accompanying drawings, the shape of embodiment or thickness can enlarge, to simplify or convenient the sign.The part of element will be to describe explanation in the accompanying drawing.Apprehensiblely be that the element of not describing or describing can be the form that has known to various those skilled in the art.In addition, when narration one deck was positioned at base material or another layer and goes up, this layer can be located immediately on base material or another layer, or intermediary layer can also be arranged therebetween.
In Fig. 2 A-Fig. 2 H, show the profile of making integrated circuit package body according to first embodiment of the invention.In Fig. 2 A, the integrated circuit (IC) chip 102 with upper surface 103 and lower surface 105 is provided, and forms photo-sensitive cell 104 on the upper surface 103 of integrated circuit (IC) chip 102.And for example shown in Fig. 2 A, form bond pad 106 in the upper surface of said integrated circuit chip 102, and be electrically connected above-mentioned photo-sensitive cell 104.
In a preferred embodiment, said integrated circuit chip 102 can be the sensitive integrated circuits chip, but not as limit.Above-mentioned bond pad 106 preferably can be copper, aluminium or other electric conducting material.In a preferred embodiment, form the mode of above-mentioned bond pad 106, for example can be that mode with sputter (sputtering), evaporation (evaporation) forms conductive material layer, then carry out photoetching and etched technology again, to form above-mentioned bond pad 106.Though the bond pad of display separation in Fig. 2 A, scrutable is that bond pad also can be the bond pad that extends.
Shown in Fig. 2 B, then, form barricade (barrier) 108 and can be described as gate pattern (gate pattern) again on the upper surface of integrated circuit (IC) chip 102, and between bond pad 106 and photo-sensitive cell 104.In a preferred embodiment, above-mentioned barricade 108 preferences are as being polyimide resin (polyimide resin; PI), epoxy resin (epoxy), mylar (polyester) or other suitable insulation material.The mode that forms above-mentioned barricade 108 preferably can be the mode of elder generation with coating, forms insulation material layer in the upper surface of said integrated circuit chip 102, then again with photoetching and the above-mentioned insulation material layer of etched mode patterning, to form barricade 108.
Shown in Fig. 2 C, first substrate 110 (also can be called cover plate) is provided, and forms protective layer 112 in the top of first substrate 110.Above-mentioned first substrate 110 preferably can be glass, quartz, opal, plastic cement or other suitable transparency carrier.Above-mentioned protective layer 112 preferably can be polyimide resin, epoxy resin or other suitable insulation material.And for example shown in Fig. 2 C, then, form sticker 114 on above-mentioned protective layer 112.Above-mentioned sticker 114 preferably can be the sticky material that comprises epoxy resin.
In Fig. 2 D, then, by the upper surface top of above-mentioned sticker 114 gluings first substrate 110, to form gap 116 between first substrate 110 and integrated circuit (IC) chip 102 in integrated circuit (IC) chip 102.After above-mentioned engagement step, above-mentioned protective layer 112 can cover bond pads 106, and with protection bond pad 106, and the distance between barricade 108 and the protective layer 112 is preferably greater than or equals 0.5 μ m.
It should be noted that in the present embodiment owing to be provided with barricade 108 between bond pad 106 and photo-sensitive cell 104, therefore, sticker 114 can be formed between barricade 108 and the bond pad 106, shown in Fig. 2 D.In view of the above, when engagement step, barricade can stop the zone of sticker overflow to photo-sensitive cell, caused the integrated circuit package body performance not high with improvement because of sticker overflow to photo-sensitive cell, for example sticker is covered in the photo-sensitive cell top, make the optical index be incident to photo-sensitive cell change, even cause the photo-sensitive cell can't induction light, and cause photo-sensitive cell to lose efficacy.Moreover, owing between bond pad and photo-sensitive cell, be provided with barricade, make and can more precisely control position and the use amount that sticker forms, and then reduce cost of manufacture.
After finishing above-mentioned engagement step, also can optionally carry out grinding steps, with the thickness of thinning said integrated circuit chip 102.In a preferred embodiment, behind grinding steps, the thickness of integrated circuit (IC) chip 102 preferably can be between 10～250 μ m, is beneficial to the carrying out of follow-up incision integrated circuit (IC) chip 102 steps.
Shown in Fig. 2 E, use photoetching and etching step, the predetermined cuts line along cutting individual die removes partly integrated circuit chip 102, and forms opening 118, to cut other crystal grain.Above-mentioned opening 118 can expose the lower surface and the protective layer 114 of bond pad 106.
In a preferred embodiment, above-mentioned etching step can be to use for example SF
6, C
4F
8Or the dry etching process of other suitable dry etching gas is finished.In another embodiment, above-mentioned etching step also can be to use and comprise the silicon etching liquid wet etching process, the mixed solution of 2.5% hydrofluoric acid (HF), 50% nitric acid (HNO3), 10% acetate (CH3COOH) and 37.5% water for example, removing partly integrated circuit chip 102, and expose bond pad 106.In above-mentioned wet etching process, also can be to use the etching solution that includes potassium hydroxide (KOH).
And for example shown in Fig. 2 E, form glue material 120 on the lower surface 105 of integrated circuit (IC) chip 102, and be filled among the opening 118.Then, by above-mentioned glue material 120, attach lower surface 105 tops of second substrate 122 in integrated circuit (IC) chip 102.Above-mentioned glue material preferably can be epoxy resin or other suitable material, and by for example be the coating mode be formed on the lower surface 105 of integrated circuit (IC) chip 102.Above-mentioned second substrate 122 can be and the substrate of the similar material of above-mentioned first substrate, it should be noted that second substrate 112 also can be the opaque substrate of other suitable material.Moreover second substrate 122 can be used for bearing integrated chip 102, so also can be called bearing substrate.
Shown in Fig. 2 F, it turns over the profile of turnback for integrated circuit package body among Fig. 2 E.In Fig. 2 F, form insulating barrier 124 on second substrate 122, then, by scratching device, the predetermined cuts line along cutting individual die carries out indentation step (also can be called cutting step), with formation groove 126, and expose the sidewall of bond pad 106 and the surface of first substrate 110.
In a preferred embodiment, above-mentioned insulating barrier 124 can be for example silica, silicon dioxide, silicon nitride, photoresist or other suitable dielectric material, and insulating barrier 124 can be by for example spin coating (spincoating), spray coating (spray coating) or for example be low-pressure chemical vapor deposition (low pressurechemical vapor deposition; LPCVD) or plasma enhanced chemical vapor deposition (plasmaenhanced chemical vapor deposition; PECVD) method is finished.
And for example shown in Fig. 2 F, then, form conductive layer 128 on insulating barrier 124, and extend among the groove 126, to be electrically connected bond pad 106.Above-mentioned conductive layer 128 preferably can be aluminium, copper, nickel or other suitable electric conducting material.In a preferred embodiment, the mode that forms conductive layer 128 can be, form conductive material layer in insulating barrier 124 tops by for example sputter, evaporation, plating or plasma enhanced vapour deposition process compliance ground, and conductive material layer can extend to first substrate 110 through the sidewall of bond pad 106 from the surface of insulating barrier 124.Then, by photoetching and etching step, the above-mentioned conductive material layer of patterning, forming above-mentioned conductive layer 128, and the surface of expose portion insulating barrier 124.
After finishing above-mentioned conductive layer 128,, make electric conducting material also can't preferably be formed at this groove 126 bottoms because groove 126 bottoms are comparatively narrow usually.Therefore, also can optionally carry out electroless plating (electroless plating) step, to form conductive layer 128 preferably in groove 126 bottoms.Scrutable is that conductive layer 128 also can be directly to form in the electroless plating mode.
Shown in Fig. 2 G, form soldering-resistance layer 130 in conductive layer 128 tops, and expose portion conductive layer 128, to define the position of scolder spheroid 132.Then, form scolder spheroid 132, to be electrically connected conductive layer 128 in conductive layer 128 tops of above-mentioned exposure.Above-mentioned soldering-resistance layer 130 can be used as protective layer at this.
After finishing above-mentioned steps, then, by the precut line of cutting blade, be divided into individual die, to finish integrated circuit package body 140, shown in Fig. 2 H along individual die.In Fig. 2 H, be the profile that turn over turnback of integrated circuit package body after cutting step is handled among the displayed map 2G.Integrated circuit package body 140 shown in Fig. 2 H, integrated circuit (IC) chip 102 tops are formed with photo-sensitive cell 104 and bond pad 106, and bond pad 106 is electrically connected photo-sensitive cell 104.And for example shown in Fig. 2 H, form conductive layer 128 on the sidewall of said integrated circuit chip 102, and be electrically connected bond pad 106 and scolder spheroid.
Shown in Fig. 3 A-Fig. 3 B, be the integrated circuit package body of the second embodiment of the present invention.In Fig. 3 A, provide the top to be formed with the integrated circuit (IC) chip 202 of photo-sensitive cell 204.Then, form bond pad 206, and be electrically connected photo-sensitive cell 204 in integrated circuit (IC) chip 202 tops.Afterwards, form first barricade 208 and second barricade 210 in the top of integrated circuit (IC) chip 202, and between bond pad 206 and photo-sensitive cell 204.In a preferred embodiment, the height of second barricade 210 can be the height that is less than or equal to first barricade 208.Above-mentioned second barricade 210 is between first barricade 208 and bond pad 206, and the distance between second barricade 210 and the protective layer 214 is preferably approximately more than or equal to 0.5 μ m.
Again as shown in Figure 3A, provide the top to be formed with first substrate 212 of protective layer 214 and sticker 216.Then,, engage first substrate 212, to form gap 218 in the top of integrated circuit (IC) chip 202 by sticker 216.After engagement step, protective layer 214 can cover bond pad 206, and sticker 216 can coat second barricade 210.
After finishing above-mentioned engagement step, cut the step of integrated circuit (IC) chip 202, and then use glue material 220, attach second substrate 222 on the lower surface of integrated circuit (IC) chip 202.Afterwards, forming insulating barrier 224 after on the lower surface of second substrate 222, then, carry out the scratch step, to expose bond pad 206.Then, form conductive layer 226 on the sidewall of second substrate 222, and extend to bond pad 206, and be electrically connected bond pad 206, then form soldering-resistance layer 228 in conductive layer 226 tops.At last, form the step of scolder spheroid 230 after, utilize cutting blade along the predetermined cuts line again, be divided into other crystal grain, to finish the making of integrated electric body packaging body 232, shown in Fig. 3 B.The material of said elements and generation type can be identical with first embodiment, therefore, and at this and repeat no more.
It should be noted that integrated circuit package body according to a second embodiment of the present invention, it has first barricade and second barricade between bond pad and photo-sensitive cell.Therefore, when engagement step, sticker can't overflow to the zone of photo-sensitive cell, to improve because of the underproof problem of sticker integrated circuit package body that overflow is caused.And, in the present embodiment,, therefore, can stop the overflow phenomena of sticker more effectively owing to be formed with first and second barricade.Scrutablely be, in first and second embodiment, protective layer (Dam) also can be formed on the integrated circuit (IC) chip, and protective layer also can be to form simultaneously with barricade, to reduce the step of manufacturing process.
The profile that shows the making integrated circuit package body of the third embodiment of the present invention among Fig. 4 A-Fig. 4 D.Shown in Fig. 4 A, provide the top to be formed with the integrated circuit (IC) chip 302 of photo-sensitive cell 304.Form bond pad 306 in said integrated circuit chip 302 tops, and be electrically connected photo-sensitive cell.And for example shown in Fig. 4 A, protective mulch 308 is in above-mentioned bond pad 306 tops, with protection bond pad 306.Then, form sticker 310 in above-mentioned protective layer 308 tops.The material of said elements and generation type can be identical with first embodiment, therefore repeat no more.
Fig. 4 B shows that the top is formed with first substrate 312 of barricade 314.The material and the generation type of above-mentioned first substrate 312 and barricade 314 can be identical with first embodiment.Then,, engage first substrate 312, to form gap 316 between first substrate 312 and integrated circuit (IC) chip 302, shown in Fig. 4 C in the top of said integrated circuit chip 302 by above-mentioned sticker 310.
In Fig. 4 C, after engagement step, the barricade 314 that is arranged at first substrate, 302 tops can be formed between bond pad 306 and the photo-sensitive cell 304, to stop that sticker 310 overflows are to photo-sensitive cell 304.In example, the material of above-mentioned barricade 314 and generation type can be identical with the barricade of first embodiment.In preferred embodiment, after engagement step, the distance between barricade 314 and the protective layer 308 can be more than or equal to 0.5 μ m.
After finishing above-mentioned engagement step, by photoetching and etching manufacturing process, cutting said integrated circuit chip 302, and then use glue material 318, attach second substrate 320 on the lower surface of integrated circuit (IC) chip 302.Afterwards,, then, carry out scratch step (also can be called cutting step), with the sidewall that exposes bond pad 306 and the surface of first substrate 312 forming insulating barrier 322 after on the lower surface of second substrate 320.Then, form conductive layer 324, be electrically connected bond pad 306, and then use soldering-resistance layer 326 cover part conductive layers 324 in the sidewall of integrated circuit (IC) chip 302.At last, form scolder spheroid 328 after the step of conductive layer 324 tops, utilize cutting blade again, be divided into other crystal grain, to finish the making of integrated electric body packaging body 330, shown in Fig. 4 D along predetermined line of cut.The material of said elements and generation type can be identical with first embodiment, therefore, do not repeat them here.
It should be noted that the integrated circuit package body of a third embodiment in accordance with the invention, it has barricade and is arranged on first substrate.After engagement step, barricade can be between bond pad and photo-sensitive cell.Therefore, when engagement step, sticker can't overflow to the zone of photo-sensitive cell, to improve the underproof problem of integrated circuit package body that is caused because of the sticker overflow.
Fig. 5 A-Fig. 5 B shows the profile of a fourth embodiment in accordance with the invention making integrated circuit package body.In Fig. 5 A, provide the top to be formed with the integrated circuit (IC) chip 402 of photo-sensitive cell 404.Then, form bond pad 406, and be electrically connected photo-sensitive cell 404 in the top of integrated circuit (IC) chip 402.Afterwards, protective mulch 408 with protection bond pad 408, and forms sticker 410 in the top of protective layer 408 on bond pad 408.
And for example shown in Fig. 5 A, by sticker 410, first substrate 412 that is formed with first barricade 414 and second barricade 416 above engaging is in the top of said integrated circuit chip 402, to form gap 418.In a preferred embodiment, the height of above-mentioned second barricade 416 can be the height that is less than or equal to first barricade 414.After finishing above-mentioned engagement step, first barricade 414 and second barricade 416 can be formed between bond pad 406 and the photo-sensitive cell 418, and the distance between second barricade 416 and the protective layer 408 preferably can be more than or equal to 0.5 μ m.Above-mentioned first barricade 414 and second barricade 416 can be to have suitable distance, to hold sticker 410 between first barricade 414 and second barricade 416.
After finishing above-mentioned engagement step, by photoetching and etching manufacturing process, cutting said integrated circuit chip 402, and use glue material 420, attach second substrate 422 on the lower surface of integrated circuit (IC) chip 302.Afterwards,, then, carry out scratch step (also can be called cutting step), with the sidewall that exposes bond pad 406 and the surface of first substrate 412 forming insulating barrier 424 after on the lower surface of second substrate 422.Then, form conductive layer 426 on second substrate, 422 sidewalls, and extend to the surface of first substrate 412,, then use soldering-resistance layer 428 cover part conductive layers 426 to be electrically connected bond pad 406.At last, form scolder spheroid 430 after the step of conductive layer 426 tops, utilize cutting blade again, be divided into other crystal grain, to finish the making of integrated circuit package body 432, shown in Fig. 5 B along predetermined line of cut.The material of said elements and generation type can be identical with first embodiment, therefore, and at this and repeat no more.
It should be noted that the integrated circuit package body of a fourth embodiment in accordance with the invention, it has first barricade and second barricade is arranged on first substrate.After engagement step, barricade can be between bond pad and photo-sensitive cell.Therefore, when engagement step, sticker can't overflow to the zone of photo-sensitive cell, to improve because of the underproof problem of sticker integrated circuit package body that overflow is caused.Moreover integrated circuit package body has first and second barricade in the present embodiment, therefore, can more effectively stop the overflow phenomena of sticker.
What deserves to be mentioned is that in the 3rd and the 4th embodiment, protective layer also can be formed on first substrate, and protective layer also can be to form simultaneously with barricade, to reduce the step of manufacturing process.In addition, above-mentioned barricade also can be to be formed at respectively on first substrate and the integrated circuit, with when the engagement step, stops the phenomenon of sticker overflow.Moreover the foregoing description all is to show with profile, and scrutable is that above-mentioned barricade can be an annular, and centers on the photo-sensitive cell on the integrated circuit (IC) chip, is disseminated to the zone of photo-sensitive cell with the restriction sticker.
Though the present invention with preferred embodiment openly as above; right its is not in order to restriction the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; permitted change and modify when doing this, so protection scope of the present invention is as the criterion when looking the scope that the accompanying Claim book defined.
Claims (13)
1 one kinds of integrated circuit package bodies comprise:
Integrated circuit (IC) chip, its upper surface is formed with photo-sensitive cell;
Bond pad is formed at the upper surface of this integrated circuit (IC) chip, and is electrically connected this photo-sensitive cell;
Substrate is arranged on this integrated circuit (IC) chip, and and this integrated circuit (IC) chip between be separated with a gap;
First barricade be formed between this photo-sensitive cell and this bond pad, and the height of this first barricade equals the width in this gap; And
Conductive layer is formed on the sidewall of this integrated circuit (IC) chip, and is electrically connected this bond pad.
2. integrated circuit package body as claimed in claim 1 also comprises second barricade, between this bond pad and this first barricade.
3. integrated circuit package body as claimed in claim 2, wherein the height of this second barricade is less than or equal to the height of this first barricade.
4. the described integrated circuit package body of claim 2, wherein this second barricade is positioned on this integrated circuit (IC) chip.
5. integrated circuit package body as claimed in claim 2, wherein this second barricade is positioned on the substrate, and this substrate is arranged at the top of this integrated circuit (IC) chip accordingly.
6. integrated circuit package body as claimed in claim 5 also comprises:
Protective layer coats this bond pad; And
Adhesion coating is formed between this protective layer and this first barricade, and bonding this integrated circuit (IC) chip and this substrate.
7. integrated circuit package body as claimed in claim 1 also comprises the scolder spheroid, is formed on this conductive layer.
8. the manufacture method of an integrated circuit package body comprises:
Provide upper surface to be formed with the integrated circuit (IC) chip of photo-sensitive cell;
Substrate is provided, is arranged on this integrated circuit (IC) chip, and and this integrated circuit (IC) chip between be separated with a gap;
Form bond pad on this integrated circuit package body, and be electrically connected this photo-sensitive cell;
Form first barricade between this bond pad and this photo-sensitive cell, and the height of this first barricade equals the width in this gap; And
Form conductive layer on the sidewall of this integrated electrical chip, and be electrically connected this bond pad.
9. the manufacture method of integrated circuit package body as claimed in claim 8 wherein forms the mode of this first barricade between this bond pad and this photo-sensitive cell, comprising:
This first barricade is set on this substrate; And
By adhesion coating, this substrate is attached on this integrated circuit (IC) chip, to form this first barricade between this bond pad and this photo-sensitive cell.
10. the manufacture method of integrated circuit package body as claimed in claim 9, also comprise and second barricade is set on this substrate, and by attaching the step of this substrate, to form this second barricade between this bond pad and this first barricade in this integrated circuit (IC) chip top.
11. the manufacture method of integrated circuit package body as claimed in claim 8 also comprises second barricade being set on this integrated circuit, and between this bond pad and this first barricade.
12. the manufacture method of integrated circuit package body as claimed in claim 8 wherein forms the mode of this conductive layer, comprising:
Remove this integrated circuit (IC) chip of part and this protective layer,, and expose this bond pad with the formation groove; And
Form this conductive layer among this groove, be electrically connected this bond pad and this conductive layer extends on the lower surface of this integrated circuit (IC) chip.
13. the manufacture method of integrated circuit package body as claimed in claim 8 also comprises forming the scolder spheroid on this conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710091415 CN100552963C (en) | 2007-03-28 | 2007-03-28 | Integrated circuit package body and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710091415 CN100552963C (en) | 2007-03-28 | 2007-03-28 | Integrated circuit package body and preparation method thereof |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910171764A Division CN101677090A (en) | 2007-03-28 | 2007-03-28 | Integrated circuit package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101276820A CN101276820A (en) | 2008-10-01 |
| CN100552963C true CN100552963C (en) | 2009-10-21 |
Family
ID=39996023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710091415 Expired - Fee Related CN100552963C (en) | 2007-03-28 | 2007-03-28 | Integrated circuit package body and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100552963C (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI508194B (en) * | 2009-01-06 | 2015-11-11 | Xintec Inc | Electronic device package and fabrication method thereof |
| US9209124B2 (en) | 2010-05-11 | 2015-12-08 | Xintec Inc. | Chip package |
| US8952501B2 (en) | 2010-05-11 | 2015-02-10 | Xintec, Inc. | Chip package and method for forming the same |
| TWI541968B (en) * | 2010-05-11 | 2016-07-11 | 精材科技股份有限公司 | Chip package |
| CN104347576B (en) * | 2013-07-24 | 2017-06-09 | 精材科技股份有限公司 | Wafer encapsulation body and its manufacture method |
| JP6119664B2 (en) * | 2014-05-14 | 2017-04-26 | 株式会社オートネットワーク技術研究所 | Circuit assembly and electrical junction box |
| CN108231805B (en) * | 2016-12-14 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| US10867955B2 (en) * | 2018-09-27 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure having adhesive layer surrounded dam structure |
| TWI720806B (en) | 2020-02-03 | 2021-03-01 | 友達光電股份有限公司 | Light-emitting diode display |
-
2007
- 2007-03-28 CN CN 200710091415 patent/CN100552963C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101276820A (en) | 2008-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100552963C (en) | Integrated circuit package body and preparation method thereof | |
| CN100576554C (en) | Image sensing element packaging body and preparation method thereof | |
| CN103400808B (en) | The wafer level packaging structure of image sensor and method for packing | |
| CN103295985B (en) | Wafer encapsulation body and forming method thereof | |
| CN101246893A (en) | Integrated circuit package body with large conductive area and its production method | |
| US8003442B2 (en) | Integrated cirucit package and method for fabrication thereof | |
| TW464927B (en) | Metal bump with an insulating sidewall and method of fabricating thereof | |
| CN101359656B (en) | Image sensor package and fabrication method thereof | |
| CN204632759U (en) | A kind of sensor chip packaging body of chip size grade | |
| CN1573445B (en) | Liquid crystal display device and method of fabricating the same | |
| KR20010040740A (en) | Integrated circuit device | |
| JP2003516634A (en) | Manufacturing method of packaged integrated circuit device and packaged integrated circuit device manufactured by the manufacturing method | |
| CN101009332A (en) | Thin-film circuit device, method for manufacturing thin-film circuit device, and electronic apparatus | |
| CN103426832B (en) | Chip packing-body and forming method thereof | |
| TW200910435A (en) | Method of wafer-level segmenting capable of protecting contact pad | |
| CN102543922A (en) | Chip package and method for forming the same | |
| CN109285845B (en) | Array substrate, display device using the same, and method for manufacturing the same and device | |
| CN103413834B (en) | A kind of thin-film transistor and preparation method thereof, array base palte and display unit | |
| CN110459553A (en) | Lens assembly and forming method, optical sensor and encapsulating structure and packaging method | |
| CN100416802C (en) | Method and structure for a wafer level packaging | |
| CN101908478B (en) | Manufacturing method of copper electrode structure and application thereof | |
| US20070166958A1 (en) | Method of wafer level packaging and cutting | |
| CN203481209U (en) | Wafer-level packaging structure of image sensor | |
| CN101950729B (en) | Wafer level packaging of electronic component and manufacturing method thereof | |
| CN102891120B (en) | Wafer encapsulation body and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091021 Termination date: 20180328 |