CN109285845B

CN109285845B - Array substrate, display device using the same, and method for manufacturing the same and device

Info

Publication number: CN109285845B
Application number: CN201811317754.4A
Authority: CN
Inventors: 林宜欣; 黄朝伟; 陈正欣
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2018-08-03
Filing date: 2018-11-07
Publication date: 2021-06-04
Anticipated expiration: 2038-11-07
Also published as: CN109285845A; TW202008043A; TWI676839B

Abstract

An array substrate comprises a first circuit board, a second circuit board, an adhesive layer and at least one connecting electrode. The first circuit board has a first surface. The first circuit board includes at least one first pad and at least one second pad. The second circuit board has a second surface. The second circuit board comprises at least one press-fit connecting pad. The adhesive layer is positioned between the first circuit board and the second circuit board. The first edge of the first circuit board, the second edge of the second circuit board, and the adhesive edge of the adhesive layer are substantially aligned with each other. The connection electrode extends from the first surface to the second surface along the first edge, the second edge, and the adhesive edge. The connecting electrode is electrically connected to the second pad and the pressing pad.

Description

Array substrate, display device using the same, and method for manufacturing the same and device

Technical Field

The present invention relates to an electronic device and a method for manufacturing the same, and more particularly, to an array substrate and a method for manufacturing the same, and a display device using the array substrate and a method for manufacturing the same.

Background

In the fabrication of array substrates, it is complicated to form electronic devices on both opposite surfaces of a single substrate (bare substrate). If the electronic element on one surface is damaged, the entire array substrate is damaged regardless of whether the electronic element on the other surface is damaged.

Disclosure of Invention

The invention provides an array substrate and a manufacturing method thereof, wherein the manufacturing method is simple and has better manufacturing yield.

The array substrate comprises a first circuit board, a second circuit board, an adhesion layer and at least one connecting electrode. The first circuit board has a first surface. The first circuit board includes at least one first pad and at least one second pad. The second circuit board has a second surface. The second circuit board comprises at least one press-fit connecting pad. The adhesive layer is positioned between the first circuit board and the second circuit board. The first edge of the first circuit board, the second edge of the second circuit board, and the adhesive edge of the adhesive layer are substantially aligned with each other. The connection electrode extends from the first surface of the first wiring board to the second surface of the second wiring board along the first edge of the first wiring board, the second edge of the second wiring board, and the adhesive edge of the adhesive layer. The connecting electrode is electrically connected to the second pad and the pressing pad.

The manufacturing method of the array substrate of the invention comprises the following steps. A first circuit board is provided. The first circuit board includes at least one first pad and at least one second pad. A second circuit board is provided. The second circuit board comprises at least one press-fit connecting pad. And carrying out a bonding process to form an adhesive layer for bonding the first circuit board and the second circuit board. And performing a cutting process to cut at least one of the first circuit board, the adhesive layer and the second circuit board. After the cutting process, at least one connecting electrode is formed to electrically connect the second pad and the pressing pad. The connection electrode at least partially covers the first edge of the first circuit board, the second edge of the second circuit board, and the adhesive edge of the adhesive layer, and the first edge of the first circuit board, the second edge of the second circuit board, and the adhesive edge of the adhesive layer are substantially aligned with each other.

Based on the above, the array substrate of the present invention is formed by bonding the first circuit board and the second circuit board to each other through the adhesive layer. Therefore, the manufacturing method of the array substrate is simple. Also, it can be confirmed that the first wiring board and the second wiring board have good functions before the first wiring board and the second wiring board are bonded to each other. Therefore, the manufacturing yield of the array substrate can be improved. In addition, the connection electrodes for electrically connecting the first circuit board and the second circuit board to each other are formed on the first edge of the first circuit board, the second edge of the second circuit board, and the adhesive edge of the adhesive layer, and the first edge of the first circuit board, the second edge of the second circuit board, and the adhesive edge of the adhesive layer may be substantially aligned with each other by a cutting process. Therefore, the manufacturing method of the array substrate is simpler, and the manufacturing yield of the array substrate can be improved.

The invention provides a display device and a manufacturing method thereof, wherein the manufacturing method is simple and has optimal manufacturing yield.

The display device of the invention comprises the array substrate and at least one micro light-emitting element. The micro light-emitting element is arranged on the array substrate. The micro light-emitting element is electrically connected to the first pad and the second pad.

The method for manufacturing a display device of the present invention includes the following steps. Providing the array substrate. At least one micro light-emitting device is disposed on the array substrate. The micro light-emitting element is electrically connected to the first pad and the second pad.

In view of the above, the display device of the present invention is formed by the array substrate of the present invention. Therefore, the manufacturing method of the display device can be simpler and has the optimal manufacturing yield.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, without departing from the spirit or scope of the present invention.

In the drawings, the thickness of various elements and the like are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" or "overlapping" another element, it can be directly on or connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physically and/or electrically connected.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "portion" discussed below could be termed a second element, component, region, layer, or portion without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, including "at least one" or "at least one", unless the content clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element, as illustrated. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can include both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

As used herein, "about", "substantially", or "approximately" includes the stated value and the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the specified amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region shown or described as flat may generally have rough and/or nonlinear features. Further, the acute angles shown may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Drawings

Fig. 1A is a flowchart of a method for manufacturing an array substrate according to a first embodiment of the invention.

Fig. 1B to fig. 1H are schematic partial cross-sectional views illustrating a method for manufacturing an array substrate according to a first embodiment of the invention.

Fig. 1I is a partial top view of a part of a manufacturing method of an array substrate according to a first embodiment of the invention.

Fig. 1J is a schematic perspective view illustrating a part of a method for manufacturing an array substrate according to a first embodiment of the invention.

Fig. 2 is a schematic partial cross-sectional view of an array substrate according to a second embodiment of the invention.

Fig. 3 is a schematic partial cross-sectional view of an array substrate according to a third embodiment of the invention.

Fig. 4 is a schematic perspective view illustrating a part of a method for manufacturing an array substrate according to a fourth embodiment of the invention.

Fig. 5 is a schematic perspective view illustrating a part of a method for manufacturing an array substrate according to a fifth embodiment of the invention.

Fig. 6 is a schematic perspective view illustrating a part of a method for manufacturing an array substrate according to a sixth embodiment of the invention.

Fig. 7 is a schematic partial cross-sectional view of an array substrate according to a seventh embodiment of the invention.

Fig. 8 is a schematic partial cross-sectional view of a display device according to the present invention.

Description of reference numerals:

100. 200, 300, 700: array substrate

101: adhesive structure

110: first circuit board

110 a: first surface

110 b: third surface

110 c: first edge

111: first substrate

711 a: microstructure

112: element layer

113: first pad

114: second pad

115: conducting wire

T: active component

S: source electrode

D: drain electrode

G: grid electrode

CH: channel layer

120: first protective layer

121: first via hole

120 a: opening of the container

120 b: first opening

120 c: second opening

130: second circuit board

130 a: second surface

130 b: the fourth surface

130 c: second edge

131: second substrate

132: line layer

133: insulating layer

134: laminated pad

140: second protective layer

141: second via hole

140 a: opening of the container

140 b: press fit opening

150: adhesive layer

150 c: adhesive edge

150 h: thickness of

453: adhesive material

452. 552, 652: frame glue

160: connecting electrode

160 h: thickness of

270: electrode protection layer

FS: plane surface

R: edge zone

S1, S2, S3, S4, S5: step (ii) of

800: display device

810: micro light-emitting device

830: FPC (Flexible printed Circuit) of circuit board

90: cutting device

Detailed Description

Fig. 1A is a flowchart of a method for manufacturing an array substrate according to a first embodiment of the invention. Fig. 1B to fig. 1H are schematic partial cross-sectional views illustrating a method for manufacturing an array substrate according to a first embodiment of the invention. Fig. 1I is a partial top view of a part of a manufacturing method of an array substrate according to a first embodiment of the invention. Fig. 1J is a schematic perspective view illustrating a part of a method for manufacturing an array substrate according to a first embodiment of the invention.

Please refer to fig. 1A and fig. 1B. In step S1, a first circuit board 110 is provided, the first circuit board 110 includes at least one first pad 113 and at least one second pad 114. For example, the first circuit board 110 has a first surface 110a and a third surface 110b opposite to each other. The first circuit board 110 may include a first substrate 111, a device layer 112, a first pad 113, and a second pad 114. The device layer 112 is disposed on the first substrate 111, the first pads 113 and the second pads 114 are disposed on the device layer 112, and the first pads 113 and the second pads 114 can be electrically connected to other electronic devices (such as the active device T or the wires 115).

The material of the first substrate 111 may be glass, quartz, organic polymer or other insulating materials suitable for being cut, and is not limited in the present invention.

The device layer 112 may include active devices T, passive devices (not shown) or corresponding conductive lines (e.g., scan lines, data lines or other similar signal lines). For example, the device layer 112 may include at least one active device T, wherein the first pad 113 is electrically connected to the active device T to receive a corresponding voltage transmitted by the active device T. The active device T includes a source S, a drain D, a gate G and a channel layer CH. The gate G may be electrically connected to a scan line (not shown). The source S may be electrically connected to a data line (not shown). In the present embodiment, the active device T is, for example, a Low temperature polysilicon thin film transistor (LTPS TFT), which is not limited in the present invention.

In addition, in the first circuit board 110 of fig. 1B, only one active device T, one first pad 113 and one second pad 114 are exemplarily shown, but the number of the active devices T, the first pads 113 and/or the second pads 114 in the first circuit board 110 is not limited in the present invention. For example, as shown in fig. 1I, wherein fig. 1I may be a partial top view of the first circuit board 110 shown in fig. 1B, in fig. 1I, the first circuit board 110 may include a plurality of first pads 113 and a plurality of second pads 114, and each of the first pads 113 may be electrically connected to a corresponding active device T in the device layer 112.

In addition, in subsequent figures, all or some of the components (e.g., active elements T) in the element layer 112 may be omitted for clarity.

In this embodiment, the first protection layer 120 may be formed on the first surface 110a of the first circuit board 110. In the subsequent process, the first pads 113 and the plurality of second pads 114 may be protected by the first passivation layer 120 to reduce the possibility of damage.

In the present embodiment, the devices (such as the active device T), the first pads 113, the second pads 114, the wires 115 and/or the first protection layer 120 (if any) in the device layer 112 may be formed by a common semiconductor or packaging process, and thus are not described herein again.

Please refer to fig. 1A and fig. 1C. In step S2, a second circuit board 130 is provided, the second circuit board 130 including at least one bonding pad 134. For example, the second circuit board 130 has a second surface 130a and a fourth surface 130b opposite to each other. The second circuit board 130 may include a second substrate 131, a circuit layer 132, an insulating layer 133 and a bonding pad 134.

The material of the second substrate 131 may be glass, quartz, organic polymer or other insulating materials that are suitable to be cut, and is not limited in the present invention.

The circuit layer 132 and the insulating layer 133 are disposed on the second substrate 131. The bonding pads 134 may penetrate through the insulating layer 133 farthest from the second substrate 131 to electrically connect with the circuit layer 132. In the embodiment, the bonding pad 134 is, for example, an Under Bump Metallurgy (UBM), but the invention is not limited thereto.

In addition, in the second circuit board 130 of fig. 1C, only one circuit layer 132, one insulating layer 133 and one bonding pad 134 are exemplarily shown, but the number of the circuit layers 132, the insulating layers 133 and/or the bonding pads 134 in the second circuit board 130 is not limited in the present invention.

In this embodiment, a second protection layer 140 may be formed on the second surface 130a of the second circuit board 130. In the subsequent process, the bonding pad 134 on the second surface 130a may be protected by the second passivation layer 140 to reduce the possibility of damage.

In the present embodiment, the circuit layer 132, the insulating layer 133, the bonding pad 134 and/or the second passivation layer 140 (if any) can be formed by a common semiconductor or packaging process, and therefore, the details thereof are not repeated herein.

Please refer to fig. 1A, fig. 1D and fig. 1J. In step S3, a bonding process is performed to form the adhesive layer 150 for bonding the first circuit board 110 and the second circuit board 130. The material of the adhesive layer 150 may be, for example, a resin material, but the invention is not limited thereto.

For example, as shown in fig. 1J, the first circuit board 110 and the second circuit board 130 are bonded together by, for example, first turning the second circuit board 130 upside down (upside down) as shown in fig. 1C. Then, an uncured adhesive material (e.g., a resin or a glue material) is applied to the fourth surface 130b of the second circuit board 130. Then, the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 are respectively contacted with two opposite sides of the adhesive material. Thereafter, a curing process is performed to cure the adhesive material to form the adhesive structure 101 having the first wiring board 110 and the second wiring board 130 adhered by the adhesive layer 150 as shown in fig. 1D.

In other embodiments not shown, the first circuit board 110 shown in fig. 1B may be turned upside down. Then, the uncured adhesive material is coated on the third surface 110b of the first wiring board 110. Thereafter, the adhesive structure 101 having the first wiring board 110 and the second wiring board 130 adhered with the adhesive layer 150 is formed in a similar manner.

In other possible embodiments, other types of adhesive materials (e.g., double-sided tape) may be formed on the third surface 110b of the first circuit board 110 and/or the fourth surface 130b of the second circuit board 130. Then, the first wiring board 110 or the second wiring board 130 is turned upside down. Then, the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 are bonded face to face (face to face), and the adhesive material between the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 forms an adhesive layer 150, so as to form the adhesive structure 101 having the first circuit board 110 and the second circuit board 130 adhered by the adhesive layer 150.

In the present embodiment, the thickness 150h of the adhesive layer 150 is less than or equal to 10 micrometers (mum) and greater than 0 μm. Thus, the adhesive layer 150 can be cut properly. Moreover, in a subsequent process (e.g., turning over, transferring, or the like the adhesive structure 101), the thickness 150h of the adhesive layer 150 is less than or equal to 10 μm, which may reduce a shear force (shear force) between the first circuit board 110 and the second circuit board 130, and may reduce the possibility of damage to the first circuit board 110 and/or the second circuit board 130.

Please refer to fig. 1A, 1D to 1F. In step S4, a cutting process is performed to cut at least one of the first circuit board 110, the adhesive layer 150, and the second circuit board 130. For example, as shown in fig. 1E, the edge region R of the bonding structure 101 (shown in fig. 1D) shown in fig. 1D may be cut by a cutting device 90 through laser cutting, water jet cutting or other suitable cutting methods to cut at least one of the first substrate 111 of the first circuit board 110, the adhesive layer 150 and the second substrate 131 of the second circuit board 130.

In some embodiments, after the aforementioned cutting process, a micro-etching (micro-etching), a grinding (polishing) or other suitable planarization process may be further performed on the first edge 110c (shown in fig. 1F) of the first circuit board 110, the second edge 130c (shown in fig. 1F) of the second circuit board 130, and the adhesive edge 150c (shown in fig. 1F) of the adhesive layer 150 to improve the flatness (flatness) of the surface formed by the surface of the first edge 110c of the first substrate 111, the surface of the second edge 130c of the second substrate 131, and the surface of the adhesive edge 150c of the adhesive layer 150.

Referring to fig. 1F, after the cutting process is performed, the first edge 110c of the first substrate 111, the second edge 130c of the second substrate 131, and the adhesive edge 150c of the adhesive layer 150 are substantially aligned with each other, and the surface of the first edge 110c of the first substrate 111, the surface of the second edge 130c of the second substrate 131, and the surface of the adhesive edge 150c of the adhesive layer 150 may be coplanar (coplanar) with each other to form a flat plane FS.

Of course, at microscopic dimensions (e.g., nanometer or atomic dimensions), the surface of any object has roughness, only a relative size issue. Therefore, the equal range of the flat surface defined herein is covered as long as the surface of the first edge 110c of the first substrate 111, the surface of the second edge 130c of the second substrate 131, and the surface of the adhesive edge 150c of the adhesive layer 150 form a plane (e.g., a mathematically ideal virtual flat surface) after the cutting process, and the difference between the highest point and the lowest point of the surface of the first edge 110c of the first substrate 111, the surface of the second edge 130c of the second substrate 131, and the surface of the adhesive edge 150c of the adhesive layer 150 in the normal direction of the plane (i.e., the flatness of the plane) is smaller than the minimum thickness 160H (shown in fig. 1H) of the connection electrode 160 (shown in fig. 1H) formed thereon.

Please refer to fig. 1G. In some embodiments, the opening 120a may be formed on the first passivation layer 120 (if present) by etching, mechanical drilling, laser drilling, or other suitable methods, and the opening 120a may expose a portion of the wire 115 or other conductive pad electrically connected to the second pad 114. Alternatively, the opening 140a may be formed on the second passivation layer 140 (if present) by etching, mechanical drilling, laser drilling, or other suitable methods, and the opening 140a may expose a portion of the circuit layer 132 or another conductive pad electrically connected to the circuit layer 132.

Referring to fig. 1H, the connection electrode 160 is formed to electrically connect the second pad 114 and the bonding pad 134, and the connection electrode 160 at least partially covers the first edge 110c of the first substrate 111, the second edge 130c of the second substrate 131 and the bonding edge 150c of the bonding layer 150. For example, the conductive material may be formed at least on the surface of the first edge 110c of the first substrate 111, the surface of the second edge 130c of the second substrate 131, and the surface of the bonding edge 150c of the bonding layer 150 by printing (e.g., screen printing), plating (e.g., sputtering, evaporation), or other suitable methods, so that the second pads 114 can be electrically connected to the corresponding bonding pads 134.

In some embodiments, the conductive material for forming the connection electrode 160 may further partially cover the first surface 110a of the first circuit board 110 and fill the plurality of openings 120a of the first protection layer 120 to form the first via hole 121. In this way, the second pads 114 can be electrically connected to the corresponding bonding pads 134 through the corresponding first via holes 121 and the corresponding connection electrodes 160.

In some embodiments, the conductive material for forming the connection electrode 160 may further partially cover the second surface 130a of the second circuit board 130 and fill the plurality of openings 140a of the second passivation layer 140 to form the second via hole 141. In this way, the second pads 114 can be electrically connected to the corresponding bonding pads 134 through the corresponding connection electrodes 160 and the corresponding second via holes 141.

The fabrication of the array substrate 100 of the present embodiment can be substantially completed through the above processes. The array substrate 100 includes a first circuit board 110, a second circuit board 130, an adhesive layer 150, and at least one connection electrode 160. The first circuit board 110 has a first surface 110a, and the first circuit board 110 includes at least one first pad 113 and at least one second pad 114. The second circuit board 130 has a second surface 130a, and the second circuit board 130 includes at least one pressure-bonding pad 134. The adhesive layer 150 is located between the first circuit board 110 and the second circuit board 130. The first edge 110c of the first circuit board 110, the second edge 130c of the second circuit board 130, and the adhesive edge 150c of the adhesive layer 150 are substantially aligned with each other. The connection electrode 160 may extend from the first surface 110a of the first wiring board 110 to the second surface 130a of the second wiring board 130 along the first edge 110c of the first wiring board 110, the second edge 130c of the second wiring board 130, and the adhesive edge 150c of the adhesive layer 150. The connection electrode 160 is electrically connected to the second pad 114 and the bonding pad 134.

In the present embodiment, the surface of the first edge 110c of the first circuit board 110, the surface of the second edge 130c of the second circuit board 130, and the surface of the adhesive edge 150c of the adhesive layer 150 form a flat surface FS, and the connection electrode 160 at least partially covers the flat surface FS.

Fig. 2 is a schematic partial cross-sectional view of an array substrate according to a second embodiment of the invention. The array substrate 200 of the present embodiment is similar to the array substrate 100 of the first embodiment, with the difference that: the array substrate 100 further includes an electrode protection layer 270. The electrode protection layer 270 covers the connection electrode 160, and the possibility of damage to the connection electrode 160 may be reduced in a subsequent process (e.g., flipping, transferring, or the like of the array substrate 200).

In the present embodiment, after the connection electrode 160 is formed, the electrode protection layer 270 formed by a polymer material, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or other suitable dielectric materials may be formed by a common semiconductor or packaging process, and thus, the description thereof is omitted.

Fig. 3 is a schematic partial cross-sectional view of an array substrate according to a third embodiment of the invention. The array substrate 300 of the present embodiment is similar to the array substrate 200 of the second embodiment, with the difference that: the first passivation layer 120 has a first opening 120b corresponding to the first pad 113 and a second opening 120c corresponding to the second pad 114, and the second passivation layer 140 has a bonding opening 140b corresponding to the bonding pad 134.

The first opening 120b and/or the second opening 120c can be formed by etching, mechanical drilling, laser drilling or other suitable methods, and the order of forming the opening 120a, the first opening 120b and the second opening 120c is not limited in the present invention. For example, the first opening 120b and/or the second opening 120c may be formed in the same process as the opening 120 a.

The stitching opening 140b may be formed by etching, mechanical drilling, laser drilling or other suitable methods, and the order of forming the stitching opening 140b and the opening 140a is not limited by the present invention. For example, the pressing opening 140b may be formed in the same process as the opening 140 a.

Fig. 4 is a schematic perspective view illustrating a part of a method for manufacturing an array substrate according to a fourth embodiment of the invention. Specifically, fig. 4 may be a schematic perspective view of the bonding process performed in step S3 in fig. 1A.

In the present embodiment, the first circuit board 110 and the second circuit board 130 are bonded together by, for example, turning the second circuit board 130 upside down as shown in fig. 1C. Then, after the sealant 452 is formed on the fourth surface 130b of the second circuit, the uncured adhesive material 453 is coated on the fourth surface 130b of the second circuit board 130 within the region surrounded by the sealant 452. Next, the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 are respectively contacted to two opposite sides of the adhesive material 453. Thereafter, a curing process is performed to cure the adhesive material 453 to form an adhesive structure 101 similar to that shown in fig. 1D.

Fig. 5 is a schematic perspective view illustrating a part of a method for manufacturing an array substrate according to a fifth embodiment of the invention. Specifically, fig. 5 may be a schematic perspective view of the bonding process performed in step S3 in fig. 1A.

In this embodiment, the first circuit board 110 and the second circuit board 130 are bonded together, for example, by turning the second circuit board 130 shown in fig. 1C upside down. Then, the sealant 552 is formed on the fourth surface 130b of the second circuit board 130. Then, in a low pressure environment (e.g., less than 1 atm), the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 are respectively contacted to two opposite sides of the sealant 552. Then, in a room pressure (e.g., 1 atm) environment, the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 can be respectively sealed with the opposite sides of the sealant by the sealant 552 and the external atmospheric pressure, so as to form the bonding structure 101 similar to that shown in fig. 1D.

Fig. 6 is a schematic perspective view illustrating a part of a method for manufacturing an array substrate according to a sixth embodiment of the invention. Specifically, fig. 6 may be a schematic perspective view of the bonding process performed in step S3 in fig. 1A.

In this embodiment, the first circuit board 110 and the second circuit board 130 are bonded together, for example, by turning the second circuit board 130 shown in fig. 1C upside down. Then, after the sealant 652 is formed on the fourth surface 130b of the second circuit board 130, an adhesive material 654 (e.g., a double-sided adhesive tape) is formed in the range surrounded by the sealant 652. Next, the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 are respectively contacted to two opposite sides of the sealant 652 and/or the adhesive 654, so as to form the bonding structure 101 similar to that shown in fig. 1D.

Fig. 7 is a schematic partial cross-sectional view of an array substrate according to a seventh embodiment of the invention. The array substrate 700 of the present embodiment is similar to the array substrate 100 of the first embodiment, with the difference that: the third surface 110b of the first circuit board 110 (i.e., the surface of the first substrate 111 away from the device layer 112 and connected to the adhesive layer 150) may further have a plurality of microstructures 711a thereon. The microstructure on the third surface 110b can promote the adhesion between the first circuit board 110 and the adhesive layer 150.

In other embodiments (not shown), the fourth surface 130b of the second circuit board 130 (i.e., the surface of the second substrate 131 away from the device layer 112 and connected to the adhesive layer 150) may have a similar microstructure (e.g., the microstructure 711a in fig. 7), which is not limited in the disclosure.

The

array substrate

100, 200, 300, 700 or other similar array substrates of the present invention can be applied in different ways according to design requirements, and the application of the present invention to the

array substrate

100, 200, 300, 700 or other similar array substrates is not limited.

Fig. 8 is a schematic partial cross-sectional view of a display device according to the present invention. The display device 800 may include an array substrate 300 and micro light emitting devices 810, and the micro light emitting devices 810 are electrically connected to the corresponding first pads 113 and the corresponding second pads 114.

In this embodiment, the array substrate 300 included in the display device 800 is exemplified by the array substrate 300 of the third embodiment. In other embodiments, the display device 800 may also include the array substrate (e.g., the

array substrate

100, 200, 300, 700) of any of the previous embodiments or include an array substrate similar to any of the previous embodiments.

In the present embodiment, for example, the micro light emitting devices 810 may be disposed on the array substrate 300, and the micro light emitting devices 810 are electrically connected to the corresponding first pads 113 and the corresponding second pads 114 through the corresponding conductive terminals 820 by flip-chip bonding (flip-chip bonding). However, the electrical connection between the micro light-emitting device 810 and the array substrate 300 is not limited in the invention. In some embodiments, not shown, the micro light emitting elements 810 may be electrically connected to the array substrate 300 through wires.

In this embodiment, the display apparatus 800 may further include a circuit board 830. The circuit board 830 can be electrically connected to the press-fit pad 134 through the conductive terminal 840. The Circuit board 830 is, for example, a Flexible Printed Circuit (FPC), but the present invention is not limited thereto.

The size of the micro light emitting elements 810 of the previous embodiments is, for example, less than 100 microns, preferably less than 50 microns, but greater than 0 micron. The micro light emitting device 810 may be, for example, an organic light emitting device or an inorganic light emitting device, and preferably, may be an inorganic light emitting device, but is not limited thereto. The structure of the micro light emitting device 810 may be a P-N diode, a P-I-N diode, or other suitable structure. The micro light emitting device 810 may be a vertical micro light emitting device, a horizontal micro light emitting device, or a flip chip micro light emitting device. The micro light-emitting elements 810 may be organic materials (e.g., organic polymer light-emitting materials, organic small molecule light-emitting materials, organic complex light-emitting materials, or other suitable materials, or combinations thereof), inorganic materials (e.g., perovskite materials, rare earth ion light-emitting materials, rare earth fluorescent materials, semiconductor light-emitting materials, or other suitable materials, or combinations thereof), or other suitable materials, or combinations thereof.

In the foregoing embodiments, the active device T may be a Thin Film Transistor (TFT), such as a bottom gate transistor, a top gate transistor, a vertical transistor, or other suitable transistors. The gate G of the bottom-gate transistor is located below the semiconductor layer (e.g., channel layer CH), the gate G of the top-gate transistor is located above the semiconductor layer (e.g., channel layer CH), and the channel of the semiconductor layer of the three-dimensional transistor is extended out of a plane. The semiconductor layer (e.g., channel layer CH) may be a single layer or a multi-layer structure, and the material thereof may include amorphous silicon, microcrystalline silicon, nanocrystalline silicon, polycrystalline silicon, single crystal silicon, organic semiconductor material, oxide semiconductor material, carbon nanotubes/rods, perovskite material, or other suitable material or combination of the foregoing.

In addition, the active device T of the foregoing embodiment may be electrically connected to another active device (not shown) and a capacitor (not shown), which are referred to as two active devices and a capacitor (which may be referred to as 2T 1C). In other embodiments, the number of the active devices and the capacitors corresponding to each micro light emitting device 810 may vary according to design, and may be referred to as three active devices and one or two capacitors (which may be denoted as 3T1C/2C), four active devices and one or two capacitors (which may be denoted as 4T1C/2C), five active devices and one or two capacitors (which may be denoted as 5T1C/2C), six active devices and one or two capacitors (which may be denoted as 6T1C/2C), or other suitable circuit configurations.

In summary, the manufacturing method of the array substrate of the invention is simple and has a preferable manufacturing yield. Therefore, the manufacturing method of the display device formed by the array substrate can be simpler and has preferable manufacturing yield.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. An array substrate, comprising:

the first circuit board comprises a first substrate, a second substrate and a third substrate, wherein the first substrate is provided with a first surface and a third surface which are opposite to each other, and the first circuit board comprises at least one first connecting pad and at least one second connecting pad which are arranged on the first surface;

a second circuit board including a second substrate having a second surface and a fourth surface opposite to each other, the second circuit board including at least one press-fit pad disposed on the second surface, and the third surface facing the fourth surface;

the adhesive layer is positioned between the first circuit board and the second circuit board, and the third surface and the fourth surface are respectively contacted with two opposite sides of the adhesive layer, wherein a first edge of the first circuit board, a second edge of the second circuit board and an adhesive edge of the adhesive layer are cut to be level with each other; and

at least one connecting electrode extending from the first surface of the first circuit board along the first edge of the first circuit board, the second edge of the second circuit board and the adhesive edge of the adhesive layer and contacting the second surface of the second circuit board, the at least one connecting electrode being electrically connected to the at least one second pad and the at least one bonding pad,

wherein the first edge of the first circuit board, the second edge of the second circuit board and the adhesive edge of the adhesive layer form a flat surface, and the at least one connecting electrode at least partially covers and contacts the flat surface; and

and the circuit board is arranged on the second surface and is electrically connected with the at least one press-fit connecting pad.

2. The array substrate of claim 1, wherein the adhesive layer has a thickness of less than or equal to 10 μm.

3. The array substrate of claim 1, further comprising:

an electrode protection layer covering the at least one connection electrode.

4. The array substrate of claim 1, further comprising:

the first protective layer is covered on the first circuit board and provided with at least one first through hole, and the at least one connecting electrode is electrically connected to the at least one second connecting pad through the at least one first through hole.

5. The array substrate of claim 4, wherein the first passivation layer has at least one first opening corresponding to the at least one first pad and at least one second opening corresponding to the at least one second pad.

6. The array substrate of claim 1, further comprising:

and the second protective layer is covered on the second circuit board and provided with at least one second through hole, and the at least one connecting electrode is electrically connected to the at least one pressing connecting pad through the at least one second through hole.

7. The array substrate of claim 6, wherein the second passivation layer has at least one bonding opening corresponding to the at least one bonding pad.

8. A display device, comprising:

an array substrate of claim 1; and

at least one micro light emitting device disposed on the array substrate, the at least one micro light emitting device being electrically connected to the at least one first pad and the at least one second pad.

9. A manufacturing method of an array substrate includes:

providing a first circuit board, wherein the first circuit board comprises a first substrate and a second substrate, the first substrate is provided with a first surface and a third surface which are opposite to each other, and the first circuit board comprises at least one first connecting pad and at least one second connecting pad which are arranged on the first surface;

providing a second circuit board, wherein the second circuit board comprises a second substrate and a second surface and a fourth surface which are opposite to each other, the second circuit board comprises at least one press-fit connecting pad arranged on the second surface, and the third surface faces the fourth surface;

carrying out an adhesion process to form an adhesion layer for adhering the first circuit board and the second circuit board, wherein the third surface and the fourth surface are respectively contacted with two opposite sides of the adhesion layer;

performing a cutting process to cut at least one of the first circuit board, the adhesive layer and the second circuit board; and

after the cutting process, forming at least one connecting electrode to electrically connect the at least one second pad and the at least one bonding pad, wherein the at least one connecting electrode at least partially covers a first edge of the first circuit board, a second edge of the second circuit board and an adhesive edge of the adhesive layer, and the first edge of the first circuit board, the second edge of the second circuit board and the adhesive edge of the adhesive layer are aligned with each other,

wherein the first edge of the first circuit board, the second edge of the second circuit board and the adhesive edge of the adhesive layer form a flat surface, and the at least one connection electrode at least partially covers the flat surface,

and providing a circuit board arranged on the second surface and electrically connected to the at least one press-fit pad.

10. The method of claim 9, wherein the adhesive layer has a thickness less than or equal to 10 μm.

11. The method of manufacturing an array substrate of claim 9, further comprising:

forming an electrode protection layer on the at least one connection electrode.

12. The method of manufacturing an array substrate of claim 9, further comprising:

before the cutting process, a first protective layer is formed on the first circuit board.

13. The method of manufacturing an array substrate of claim 9, further comprising:

before the cutting process, a second protective layer is formed on the second circuit board.

14. A method of manufacturing a display device, comprising:

providing an array substrate of claim 1; and

at least one micro light-emitting device is disposed on the array substrate and electrically connected to the at least one first pad and the at least one second pad.