TW202008043A - Array substrate and manufacturing method thereof, display device using the same and manufacturing method thereof - Google Patents

Abstract

An array substrate including a first circuit board, a second circuit board, an adhesive layer, and at least one connection electrode is provided. The first circuit board has a first surface. The first circuit board includes at least one first pad and at least one second pad. The second circuit board has a second surface. The second circuit board includes at least one press pad. The adhesive layer is disposed between the first circuit board and the second circuit board. The first edge of the first circuit board, the second edge of the second circuit board, and the adhesive edge of the adhesive layer are substantially aligned with each other. The connection electrode extends from the first surface along the first edge, the second edge, and the adhesive edge to the second surface. The connecting electrode is electrically connected to the second pad and the pressing pad.

Description

Array substrate and manufacturing method thereof, and display device using the array substrate and manufacturing method thereof

The invention relates to an electronic device and a manufacturing method thereof, and in particular to an array substrate and a manufacturing method thereof, a display device using the array substrate and a manufacturing method thereof.

In the manufacturing process of the array substrate, it is more complicated to form electronic components on two opposite sides of a bare substrate. Moreover, as long as the electronic component on one side is damaged, regardless of whether the electronic component on the other side is damaged, the entire array substrate is damaged.

The invention provides an array substrate and a manufacturing method thereof. The manufacturing method is relatively simple, and has a better manufacturing yield.

The array substrate of the present invention includes a first circuit board, a second circuit board, an adhesive layer, and at least one connection electrode. The first circuit board has a first surface. The first circuit board includes at least one first pad and at least one second pad. The second circuit board has a second surface. The second circuit board includes at least one compression pad. The adhesive layer is located between the first circuit board and the second circuit board. The first edge of the first circuit board, the second edge of the second circuit board and the adhesive edge of the adhesive layer are substantially aligned with each other. The connection electrode extends from the first surface of the first circuit board along the first edge of the first circuit board, the second edge of the second circuit board, and the adhesive edge of the adhesive layer to the second surface of the second circuit board. The connection electrode is electrically connected to the second pad and the compression pad.

The method for manufacturing an array substrate of the present invention includes the following steps. Provide the first circuit board. The first circuit board includes at least one first pad and at least one second pad. Provide a second circuit board. The second circuit board includes at least one compression pad. The bonding process is performed to form an adhesive layer for bonding the first circuit board and the second circuit board. A cutting process is performed to cut at least one of the first circuit board, the adhesive layer and the second circuit board. After the cutting process is performed, at least one connecting electrode is formed to electrically connect the second pad and the pressing pad. The connection electrode at least partially covers the first edge of the first circuit board, the second edge of the second circuit board and the adhesive edge of the adhesive layer, and the first edge of the first circuit board, the second edge of the second circuit board and the adhesive layer The glued edges are basically aligned with each other.

Based on the above, the array substrate of the present invention bonds the first circuit board and the second circuit board to each other through the adhesive layer. Therefore, the manufacturing method of the array substrate is relatively simple. Moreover, it can be confirmed that the first circuit board and the second circuit board have a good function before bonding the first circuit board and the second circuit board to each other. Therefore, the manufacturing yield of the array substrate can be improved. In addition, connection electrodes for electrically connecting the first circuit board and the second circuit board to each other are formed on the first edge of the first circuit board, the second edge of the second circuit board, and the adhesive edge of the adhesive layer, and The first edge of the first circuit board, the second edge of the second circuit board and the adhesive edge of the adhesive layer can be substantially aligned with each other by a cutting process. Therefore, the manufacturing method of the array substrate is relatively simple, and the manufacturing yield of the array substrate can be improved.

The invention provides a display device and a manufacturing method thereof. The manufacturing method is relatively simple and has a good manufacturing yield.

The display device of the present invention includes the aforementioned array substrate and at least one micro light-emitting element. The micro light emitting element is arranged on the array substrate. The micro light-emitting device is electrically connected to the first pad and the second pad.

The manufacturing method of the display device of the present invention includes the following steps. The aforementioned array substrate is provided. At least one miniature light emitting element is arranged on the array substrate. The micro light-emitting device is electrically connected to the first pad and the second pad.

Based on the above, the display device of the present invention is constituted by the array substrate of the present invention. Therefore, the manufacturing method of the display device may also be relatively simple and have a better manufacturing yield.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of each element and the like are exaggerated for clarity. Throughout the specification, the same reference numerals denote the same elements. It should be understood that when an element such as a layer, film, region, or substrate is referred to as being “on another element”, or “connected to another element”, “overlapping another element”, it can be directly on the other element On or connected to another element, or an intermediate element may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to physical and/or electrical connections.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, and/or Or part should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Accordingly, the "first element", "component", "region", "layer", or "portion" discussed below may be referred to as the second element, component, region, layer, or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not limiting. As used herein, unless the content clearly indicates, the singular forms "a", "an", and "the" are intended to include the plural forms, including "at least one" or "at least one". "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It should also be understood that when used in this specification, the terms "including" and/or "comprising" designate the described features, regions, wholes, steps, operations, presence of elements and/or components, but do not exclude one or more The presence or addition of other features, regions as a whole, steps, operations, elements, components, and/or combinations thereof.

In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship between one element and another element, as shown. It should be understood that relative terms are intended to include different orientations of the device than those shown in the figures. For example, if the device in one drawing is turned over, the element described as being on the "lower" side of the other element will be oriented on the "upper" side of the other element. Thus, the exemplary term "lower" may include "lower" and "upper" orientations, depending on the particular orientation of the drawings. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "below" can include an orientation of above and below.

As used herein, "about", "substantially", or "approximately" includes the stated value and the average value within an acceptable deviation range for a particular value determined by one of ordinary skill in the art, taking into account the measurements and A certain amount of measurement-related errors (ie, measurement system limitations). For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Therefore, it is possible to anticipate a change in the shape of the graph as a result of, for example, manufacturing techniques and/or tolerances. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions as shown herein, but include deviations in shapes caused by manufacturing, for example. For example, an area shown or described as flat may generally have rough and/or non-linear characteristics. In addition, the acute angle shown may be round. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, and are not intended to limit the scope of the claims.

FIG. 1A is a flowchart of a method for manufacturing an array substrate according to the first embodiment of the present invention. 1B to 1H are schematic partial cross-sectional views of a method of manufacturing an array substrate according to a first embodiment of the invention. FIG. 11 is a partial schematic top view of a partial manufacturing method of an array substrate according to the first embodiment of the present invention. 1J is a schematic perspective view of a partial manufacturing method of an array substrate according to the first embodiment of the present invention.

Please refer to FIGS. 1A and 1B. In step S1, a first circuit board 110 is provided. The first circuit board 110 includes at least one first pad 113 and at least one second pad 114. For example, the first circuit board 110 has a first surface 110a and a third surface 110b opposite to each other. The first circuit board 110 may include a first substrate 111, an element layer 112, a first pad 113, and a second pad 114. The device layer 112 is located on the first substrate 111, the first pad 113 and the second pad 114 are located on the device layer 112, and the first pad 113 and the second pad 114 can be combined with other electronic devices (such as active devices) T or wire 115) electrically connected.

The material of the first substrate 111 may be glass, quartz, organic polymer, or other insulating materials suitable for cutting, which is not limited in the present invention.

The device layer 112 may include an active device T, a passive device (not shown), or corresponding wires (such as scan lines, data lines, or other similar signal lines). For example, the device layer 112 may include at least one active device T, wherein the first pad 113 is electrically connected to the active device T to receive the corresponding voltage transmitted by the active device T. The active device T includes a source S, a drain D, a gate G, and a channel layer CH. The gate G can be electrically connected to the scanning line (not shown). The source S can be electrically connected to the data line (not shown). In this embodiment, the active element T is, for example, a low temperture poly Si thin film transistor (LTPS TFT), which is not limited in the present invention.

In addition, in the first circuit board 110 of FIG. 1B, only one active element T, one first pad 113, and one second pad 114 are illustrated by way of example, but the present invention is The number of the active device T, the first pad 113 and/or the second pad 114 is not limited. For example, as shown in FIG. 1I, where FIG. 1I can be a partial top view of the first circuit board 110 shown in FIG. 1B, in FIG. 1I, the first circuit board 110 can include a plurality of first pads 113 and a plurality of second pads 114, and each first pad 113 may be electrically connected to the corresponding active device T in the device layer 112.

In addition, in the subsequent drawings, for the sake of clarity, all or part of the components (such as the active component T) in the element layer 112 may be omitted.

In this embodiment, the first protective layer 120 may be formed on the first surface 110 a of the first circuit board 110. In the subsequent process, the first pads 113 and the plurality of second pads 114 on the first surface 110a can be protected by the first protective layer 120 to reduce the possibility of damage.

In this embodiment, the element (eg, active element T) in the element layer 112, the first pad 113, the second pad 114, the wire 115, and/or the first protective layer 120 (if any) can be The semiconductor or packaging process is formed, so it will not be repeated here.

Please refer to FIGS. 1A and 1C. In step S2, a second circuit board 130 is provided, and the second circuit board 130 includes at least one compression pad 134. For example, the second circuit board 130 has a second surface 130a and a fourth surface 130b opposite to each other. The second circuit board 130 may include a second substrate 131, a circuit layer 132, an insulating layer 133, and a pressure bonding pad 134.

The material of the second substrate 131 may be glass, quartz, organic polymer, or other insulating materials suitable for cutting, which is not limited in the present invention.

The circuit layer 132 and the insulating layer 133 are located on the second substrate 131. The bonding pad 134 may penetrate the insulating layer 133 farthest from the second substrate 131 to be electrically connected to the circuit layer 132. In this embodiment, the compression pad 134 is, for example, UBM (Under Bump Metallurgy), but the invention is not limited thereto.

In addition, in the second circuit board 130 of FIG. 1C, only one circuit layer 132, one insulating layer 133, and one pressure bonding pad 134 are only exemplarily shown, but the present invention is directed to the circuit layer in the second circuit board 130 132, the number of insulating layers 133 and/or pressure bonding pads 134 is not limited.

In this embodiment, the second protective layer 140 may be formed on the second surface 130a of the second circuit board 130. In the subsequent process, the bonding pad 134 on the second surface 130a can be protected by the second protective layer 140 to reduce the possibility of damage.

In this embodiment, the circuit layer 132, the insulating layer 133, the bonding pad 134, and/or the second protective layer 140 (if any) can be formed by a general semiconductor or packaging process, so they will not be repeated here.

Please refer to FIGS. 1A, 1D and 1J. In step S3, a bonding process is performed to form an adhesive layer 150 for bonding the first circuit board 110 and the second circuit board 130. The material of the adhesive layer 150 may be a resin material, for example, but the invention is not limited thereto.

For example, as shown in FIG. 1J, the method of bonding the first circuit board 110 and the second circuit board 130 is, for example, first to upside down the second circuit board 130 shown in 1C. Then, the uncured adhesive material 151 (such as resin or glue) is coated on the fourth surface 130b of the second circuit board 130. Next, the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 are respectively in contact with opposite sides of the adhesive material 151. Afterwards, a curing process is performed to cure the adhesive material 151 to form an adhesive structure 101 having the first circuit board 110 and the second circuit board 130 adhered by the adhesive layer 150 as shown in FIG. 1D.

In other embodiments not shown, the first circuit board 110 as shown in FIG. 1B can also be turned upside down. Then, the uncured adhesive material 151 is coated on the third surface 110b of the first circuit board 110. Then, in a similar manner, an adhesive structure 101 having the first circuit board 110 and the second circuit board 130 bonded with the adhesive layer 150 is formed.

In other feasible embodiments, other types of adhesive materials (such as double-sided tape) may be formed on the third surface 110b of the first circuit board 110 and/or the fourth surface 130b of the second circuit board 130 first on. Then, the first circuit board 110 or the second circuit board 130 is turned upside down. After that, the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 are face-to-face bonded to each other, so that the third surface 110b of the first circuit board 110 is The adhesive material between the fourth surfaces 130b of the two circuit boards 130 forms an adhesive layer 150 to form an adhesive structure 101 having the first circuit board 110 and the second circuit board 130 adhered by the adhesive layer 150.

In this embodiment, the thickness 150h of the adhesive layer 150 is less than or equal to 10 microns (micrometer; μm) and greater than 0 microns. In this way, the adhesive layer 150 can be suitably cut. In addition, in subsequent processes (such as flipping, transferring, or other similar processes of the adhesive structure 101), the thickness 150h of the adhesive layer 150 is less than or equal to 10 microns to reduce the distance between the first circuit board 110 and the second circuit board 130 The shear force can reduce the possibility of damage to the first circuit board 110 and/or the second circuit board 130.

Please refer to FIGS. 1A, 1D to 1F. In step S4, a cutting process is performed to cut at least one of the first circuit board 110, the adhesive layer 150, and the second circuit board 130. For example, as shown in FIG. 1E, the edge of the adhesive structure 101 shown in FIG. 1D (shown in FIG. 1D) can be cut by laser cutting, water jet cutting, or other suitable cutting methods by the cutting device 90. The region R is cut to cut at least one of the first substrate 111 of the first circuit board 110, the adhesive layer 150, and the second substrate 131 of the second circuit board 130.

In some embodiments, after the foregoing cutting process, the first edge 110c of the first circuit board 110 (shown in FIG. 1F) and the second edge 130c of the second circuit board 130 (shown in FIG. 1F) and the adhesive edge 150c of the adhesive layer 150 (shown in FIG. 1F) are subjected to micro-etching, polishing, or other suitable planarization processes to enhance the first edge of the first substrate 111 The flatness of the surface formed by the surface of 110c, the surface of the second edge 130c of the second substrate 131, and the surface of the adhesive edge 150c of the adhesive layer 150.

1F, after the dicing process is performed, the first edge 110c of the first substrate 111, the second edge 130c of the second substrate 131, and the adhesive edge 150c of the adhesive layer 150 are substantially aligned with each other and are located on the first substrate 111 The surface of the first edge 110c, the surface of the second edge 130c of the second substrate 131, and the surface of the adhesive edge 150c of the adhesive layer 150 may be coplanar with each other to form a flat surface FS.

Of course, at the microscopic size (eg, nanometer size or atomic size), the surface of any object will have roughness, which is only a matter of relative size. Therefore, as long as the cutting process is performed, the surface located on the first edge 110c of the first substrate 111, the surface located on the second edge 130c of the second substrate 131, and the surface located on the adhesive edge 150c of the adhesive layer 150 correspond to A plane (eg, a mathematically ideal virtual flat surface), and in the normal direction of the aforementioned plane, the surface located on the first edge 110c of the first substrate 111 and the surface located on the second edge 130c of the second substrate 131 and The difference between the highest point and the lowest point of the surface of the adhesive edge 150c of the adhesive layer 150 relative to the aforementioned plane (ie, the flatness of the aforementioned plane) is smaller than the subsequent connection electrode 160 formed thereon (shown in FIG. 1H ) The minimum thickness of 160h (shown in Figure 1H) is covered by the equal range of the flat surface defined in this article.

Please refer to Figure 1G. In some embodiments, an opening 120a may be formed in the first protective layer 120 (if any) by etching, mechanical drilling, laser drilling, or other suitable methods, and the opening 120a may expose part of the wire 115 or another conductive pad electrically connected to the second pad 114. Or, an opening 140a can be formed in the second protective layer 140 (if any) by etching, mechanical drilling, laser drilling or other suitable methods, and the opening 140a can expose part of the circuit layer 132 or Another conductive pad that can be electrically connected to the circuit layer 132.

Referring to FIG. 1H, a connection electrode 160 is formed to electrically connect the second pad 114 and the compression pad 134. The connection electrode 160 at least partially covers the first edge 110c of the first substrate 111 and the second edge of the second substrate 131 The edge 130c and the adhesive edge 150c of the adhesive layer 150. For example, the conductive material may be formed at least on the surface of the first edge 110c of the first substrate 111 by printing (eg, screen printing), plating (eg, sputtering, evaporation) or other suitable methods 1. The surface formed by the surface of the second edge 130c of the second substrate 131 and the surface of the adhesive edge 150c of the adhesive layer 150, so that the second pad 114 can be electrically connected to the corresponding compression pad 134.

In some embodiments, the conductive material used to form the connection electrode 160 may further partially cover the first surface 110 a of the first circuit board 110 and fill in the plurality of openings 120 a of the first protective layer 120 to form the first One through hole 121. In this way, the second pad 114 can be electrically connected to the corresponding compression pad 134 through the corresponding first via 121 and the corresponding connection electrode 160.

In some embodiments, the conductive material used to form the connection electrode 160 may further partially cover the second surface 130a of the second circuit board 130, and fill a plurality of openings 140a of the second protective layer 140 to form the first二通孔孔141. In this way, the second pad 114 can be electrically connected to the corresponding compression pad 134 through the corresponding connection electrode 160 and the corresponding second via hole 141.

After the above process, the fabrication of the array substrate 100 of this embodiment can be substantially completed. The above-mentioned array substrate 100 includes a first circuit board 110, a second circuit board 130, an adhesive layer 150, and at least one connection electrode 160. The first circuit board 110 has a first surface 110a, and the first circuit board 110 includes at least one first pad 113 and at least one second pad 114. The second circuit board 130 has a second surface 130a, and the second circuit board 130 includes at least one compression pad 134. The adhesive layer 150 is located between the first circuit board 110 and the second circuit board 130. The first edge 110c of the first circuit board 110, the second edge 130c of the second circuit board 130, and the adhesive edge 150c of the adhesive layer 150 are substantially aligned with each other. The connection electrode 160 may extend from the first surface 110a of the first circuit board 110 along the first edge 110c of the first circuit board 110, the second edge 130c of the second circuit board 130, and the adhesive edge 150c of the adhesive layer 150 to the second circuit The second surface 130a of the board 130. The connection electrode 160 is electrically connected to the second pad 114 and the compression pad 134.

In this embodiment, the surface of the first edge 110c of the first circuit board 110, the surface of the second edge 130c of the second circuit board 130, and the surface of the adhesive edge 150c of the adhesive layer 150 form a flat surface FS, and are connected to the electrodes 160 is at least partially covered on a flat surface.

2 is a schematic partial cross-sectional view of an array substrate according to a second embodiment of the invention. The array substrate 200 of this embodiment is similar to the array substrate 100 of the first embodiment, except that the array substrate 100 further includes an electrode protection layer 270. The electrode protection layer 270 covers the connection electrode 160, and may reduce the possibility of damage to the connection electrode 160 in subsequent processes (eg, flipping, transferring, or other similar processes of the array substrate 200).

In this embodiment, after forming the connection electrode 160, a polymer material, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or other suitable dielectric materials may be formed by a general semiconductor or packaging process The formed electrode protection layer 270 will not be repeated here.

3 is a schematic partial cross-sectional view of an array substrate according to a third embodiment of the invention. The array substrate 300 of this embodiment is similar to the array substrate 200 of the second embodiment, except that the first protective layer 120 has a first opening 120b corresponding to the first pad 113 and a second corresponding to the second pad 114 The opening 120c, and the second protective layer 140 have a plurality of pressing openings 140b corresponding to the pressing pads 134.

The first opening 120b and/or the second opening 120c can be formed by etching, mechanical drilling, laser drilling, or other suitable methods, and the order of forming the opening 120a, the first opening 120b, and the second opening 120c of the present invention No restrictions. For example, the first opening 120b and/or the second opening 120c may be formed in the same process as the opening 120a.

The pressing opening 140b may be formed by etching, mechanical drilling, laser drilling, or other suitable methods, and the present invention does not limit the order of forming the pressing opening 140b and the opening 140a. For example, the press-fit opening 140b may be formed in the same process as the opening 140a.

4 is a schematic perspective view of a partial manufacturing method of an array substrate according to a fourth embodiment of the invention. Specifically, FIG. 4 may be a schematic perspective view of the bonding process performed in step S3 in FIG. 1A.

In this embodiment, the method of bonding the first circuit board 110 and the second circuit board 130 is, for example, to turn the second circuit board 130 as shown in FIG. 1C up and down first. After forming the sealant 452 on the fourth surface 130b of the second circuit, the uncured adhesive material 453 is coated on the fourth surface 130b of the second circuit board 130 and within the range surrounded by the sealant 452. Next, the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 are respectively in contact with opposite sides of the adhesive material 453. After that, a curing process is performed to cure the adhesive material 453 to form an adhesive structure 101 similar to that shown in FIG. 1D.

5 is a perspective schematic view of a partial manufacturing method of an array substrate according to a fifth embodiment of the invention. Specifically, FIG. 5 can be a schematic perspective view of the bonding process performed in step S3 in FIG. 1A.

In this embodiment, the method of bonding the first circuit board 110 and the second circuit board 130 is, for example, to turn the second circuit board 130 as shown in FIG. 1C up and down first. After forming the sealant 552 on the fourth surface 130b of the second circuit board 130. Next, in an environment with a low pressure (eg, less than 1 atmosphere), the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 are respectively in contact with the opposite sides of the sealant 552 . Afterwards, under the environment of room pressure (eg, 1 atmosphere), the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 can be respectively The opposite sides of the glue are tightly bonded to form an adhesive structure 101 similar to that shown in FIG. 1D.

6 is a schematic perspective view of a partial manufacturing method of an array substrate according to a sixth embodiment of the invention. Specifically, FIG. 6 may be a perspective schematic view of the bonding process performed in step S3 in FIG. 1A.

In this embodiment, the method of bonding the first circuit board 110 and the second circuit board 130 is, for example, to turn the second circuit board 130 as shown in FIG. 1C up and down first. Then, after forming the frame glue 652 on the fourth surface 130b of the second circuit board 130, an adhesive material 654 (eg, double-sided tape) is formed within the range surrounded by the frame glue 652. Next, make the third surface 110b of the first circuit board 110 and the fourth surface 130b of the second circuit board 130 contact the opposite sides of the sealant 652 and/or the adhesive material 654, respectively, to form a shape similar to that shown in FIG. 1D的粘结构101。 The adhesive structure 101.

7 is a schematic partial cross-sectional view of an array substrate according to a seventh embodiment of the invention. The array substrate 700 of this embodiment is similar to the array substrate 100 of the first embodiment, the difference is that: the third surface 110b of the first circuit board 110 (ie, the first substrate 111 is far from the element layer 112 and is in contact with the adhesive layer 150 Can have more microstructures 711a on its surface). The microstructure on the third surface 110b can enhance the adhesion between the first circuit board 110 and the adhesive layer 150.

In other embodiments not shown, the fourth surface 130b of the second circuit board 130 (that is, the surface of the second substrate 131 away from the device layer 112 and in contact with the adhesive layer 150) may have a similar microstructure ( For example, the microstructure 711a in FIG. 7 is not limited in the present invention.

Based on the above, the array substrate of the present invention bonds the first circuit board and the second circuit board to each other through the adhesive layer. Therefore, the manufacturing method of the array substrate is relatively simple. Moreover, it can be confirmed that the first circuit board and the second circuit board have a good function before bonding the first circuit board and the second circuit board to each other. Therefore, the manufacturing yield of the array substrate can be improved. In addition, connection electrodes for electrically connecting the first circuit board and the second circuit board to each other are formed on the first edge of the first circuit board, the second edge of the second circuit board, and the adhesive edge of the adhesive layer, and The first edge of the first circuit board, the second edge of the second circuit board and the adhesive edge of the adhesive layer can be substantially aligned with each other by a cutting process. Therefore, the manufacturing method of the array substrate is relatively simple, and the manufacturing yield of the array substrate can be improved.

The array substrate 100, 200, 300, 700 or other similar array substrates of the present invention can have different applications according to design requirements. The application of the present invention to the array substrate 100, 200, 300, 700 or other similar array substrates The way is not limited.

8 is a schematic partial cross-sectional view of a display device according to the present invention. The display device 800 may include an array substrate 300 and a micro light emitting element 810, and the micro light emitting element 810 is electrically connected to the corresponding first pad 113 and the corresponding second pad 114.

In this embodiment, the array substrate 300 included in the display device 800 takes the array substrate 300 of the third embodiment as an example. In other embodiments, the display device 800 may also include the array substrate of any of the foregoing embodiments (eg, array substrates 100, 200, 300, 700) or include an array substrate similar to any of the foregoing embodiments.

In this embodiment, for example, the micro light emitting element 810 may be disposed on the array substrate 300, and the micro light emitting element 810 is electrically connected through the corresponding conductive terminal 820 by flip-chip bonding To the corresponding first pad 113 and the corresponding second pad 114. However, the present invention does not limit the electrical connection between the micro light-emitting element 810 and the array substrate 300. In some non-illustrated embodiments, the micro light-emitting element 810 can be electrically connected to the array substrate 300 through wires.

In this embodiment, the display device 800 may further include a circuit board 830. The circuit board 830 can be electrically connected to the compression pad 134 through the conductive terminal 840. The circuit board 830 is, for example, a flexible printed circuit (FPC), but the invention is not limited thereto.

The size of the miniature light emitting element 810 of the foregoing embodiment is, for example, less than 100 microns, preferably, less than 50 microns, but greater than 0 microns. The micro light-emitting element 810 may be, for example, an organic light-emitting element or an inorganic light-emitting element, preferably, an inorganic light-emitting element, but is not limited thereto. The structure of the micro light-emitting element 810 may be a P-N diode, a P-I-N diode, or other suitable structures. The type of the micro light emitting element 810 may be a vertical micro light emitting element, a horizontal micro light emitting element, or a flip chip micro light emitting element. The micro light-emitting element 810 may be an organic material (for example: organic polymer light-emitting material, organic small molecule light-emitting material, organic complex light-emitting material, or other suitable material, or a combination of the foregoing materials), an inorganic material (for example: perovskite Materials, rare-earth ion luminescent materials, rare-earth fluorescent materials, semiconductor light-emitting materials, or other suitable materials, or a combination of the foregoing materials), or other suitable materials, or a combination of the foregoing materials.

In the foregoing embodiments, the active device T may use thin film transistors (TFTs), such as bottom gate transistors, top gate transistors, three-dimensional transistors, or other suitable transistors. The gate G of the bottom gate transistor is located below the semiconductor layer (eg channel layer CH), the gate G of the top gate transistor is above the semiconductor layer (eg channel layer CH), and the three-dimensional transistor The semiconductor layer channel of the crystal extends not in a plane. The semiconductor layer (eg, channel layer CH) can be a single-layer or multi-layer structure, and its materials include amorphous silicon, microcrystalline silicon, nanocrystalline silicon, polycrystalline silicon, single crystal silicon, organic semiconductor materials, oxide semiconductor materials, nano Rice carbon tubes/rods, perovskite materials, or other suitable materials or combinations of the foregoing.

In addition, the active element T of the foregoing embodiment can be electrically connected to another active element (not shown) and a capacitor (not shown), which are simply referred to as two active elements and a capacitor (which can be expressed as 2T1C). In other embodiments, the number of active elements and capacitors corresponding to each micro light-emitting element 810 can be changed according to design, and can be referred to as three active elements and one or two capacitors (which can be expressed as 3T1C/2C, for example) ), four active components and one or two capacitors (can be expressed as 4T1C/2C), five active components and one or two capacitors (can be expressed as 5T1C/2C), six active components and one or two capacitors (Can be expressed as 6T1C/2C), or other suitable circuit configuration.

Based on the above, the display device of the present invention is constituted by the array substrate of the present invention. Therefore, the manufacturing method of the display device may also be relatively simple and have a better manufacturing yield.

In summary, the manufacturing method of the array substrate of the present invention is relatively simple, and has a better manufacturing yield. Therefore, the manufacturing method of the display device composed of the array substrate of the present invention can also be relatively simple, and has a better manufacturing yield.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

100, 200, 300, 700 ‧‧‧ array substrate 101‧‧‧ bonded structure 110‧‧‧ first circuit board 110a‧‧‧ first surface 110b‧‧‧ third surface 110c‧‧‧first edge 111‧‧ ‧First substrate 711a‧‧‧Microstructure 112‧‧‧Element layer 113‧‧‧First pad 114‧‧‧Second pad 115‧‧‧ Lead T‧‧‧Active element S‧‧‧Source D ‧‧‧Drain G‧‧‧Gate CH‧‧‧Channel layer 120‧‧‧First protective layer 121‧‧‧First via 120a‧‧‧Opening 120b‧‧‧First opening 120c‧‧‧ Two openings 130‧‧‧ Second circuit board 130a‧‧‧Second surface 130b‧‧‧Fourth surface 130c‧‧‧Second edge 131‧‧‧Second substrate 132‧‧‧Wiring layer 133‧‧‧Insulation layer 134‧‧‧Pressing pad 140‧‧‧Second protective layer 141‧‧‧Second via 140a‧‧‧Opening 140b‧‧‧Pressing opening 150‧‧‧Adhesive layer 150c‧‧‧Adhesive edge 150h‧ ‧‧Thickness 151, 453‧‧‧ Adhesive materials 452, 552, 652 ‧‧‧‧ Frame glue 160‧‧‧ Connected electrode 160h Zone S1, S2, S3, S4, S5 ‧‧‧ step 800 ‧ ‧ ‧ display device 810 ‧ ‧ ‧ mini light-emitting element 830 ‧ ‧ ‧ circuit board FPC90 ‧ ‧ ‧ cutting device

FIG. 1A is a flowchart of a method for manufacturing an array substrate according to the first embodiment of the present invention. 1B to 1H are schematic partial cross-sectional views of a method of manufacturing an array substrate according to a first embodiment of the invention. FIG. 11 is a partial schematic top view of a partial manufacturing method of an array substrate according to the first embodiment of the present invention. 1J is a schematic perspective view of a partial manufacturing method of an array substrate according to the first embodiment of the present invention. 2 is a schematic partial cross-sectional view of an array substrate according to a second embodiment of the invention. 3 is a schematic partial cross-sectional view of an array substrate according to a third embodiment of the invention. 4 is a schematic perspective view of a partial manufacturing method of an array substrate according to a fourth embodiment of the invention. 5 is a perspective schematic view of a partial manufacturing method of an array substrate according to a fifth embodiment of the invention. 6 is a schematic perspective view of a partial manufacturing method of an array substrate according to a sixth embodiment of the invention. 7 is a schematic partial cross-sectional view of an array substrate according to a seventh embodiment of the invention. 8 is a schematic partial cross-sectional view of a display device according to the present invention.

S1, S2, S3, S4, S5 ‧‧‧‧Manufacturing method of array substrate

Claims (17)

An array substrate includes: a first circuit board with a first surface, and the first circuit board includes at least a first pad and at least a second pad; a second circuit board with a second surface And the second circuit board includes at least one press pad; an adhesive layer is located between the first circuit board and the second circuit board, wherein a first edge of the first circuit board and the second circuit A second edge of the board and an adhesive edge of the adhesive layer are substantially aligned with each other; and at least one connecting electrode from the first surface of the first circuit board along the first edge of the first circuit board, the The second edge of the second circuit board and the adhesive edge of the adhesive layer extend to the second surface of the second circuit board, and the at least one connecting electrode is electrically connected to the at least one second pad and the at least one One press-fit pad. The array substrate according to item 1 of the patent application scope, wherein the first edge of the first circuit board, the second edge of the second circuit board, and the adhesive edge of the adhesive layer form a flat surface, and the At least one connecting electrode at least partially covers the flat surface. The array substrate as described in item 1 of the patent application range, wherein the thickness of the adhesive layer is less than or equal to 10 microns. The array substrate as described in item 1 of the patent application further includes: an electrode protection layer covering the at least one connection electrode. The array substrate as described in item 1 of the patent application scope further includes: a first protective layer covering the first circuit board, the first protective layer having at least one first via hole, and the at least one connecting electrode The at least one first via is electrically connected to the at least one second pad. The array substrate as claimed in item 5 of the patent application range, wherein the first protective layer has at least one first opening corresponding to the at least one first pad and at least one second corresponding to the at least one second pad Opening. The array substrate as described in item 1 of the patent application scope further includes: a second protective layer covering the second circuit board, the second protective layer having at least one second via hole, and the at least one connecting electrode The at least one second via is electrically connected to the at least one compression pad. The array substrate according to item 7 of the patent application range, wherein the second protective layer has at least one pressing opening corresponding to the at least one pressing pad. A display device, including: the array substrate of claim 1; and at least one micro light-emitting element disposed on the array substrate, the at least one micro light-emitting element is electrically connected to the at least one first pad and the at least one first Two pads. The display device as described in item 9 of the patent application scope further includes: a circuit board electrically connected to the at least one compression pad. A method for manufacturing an array substrate includes: providing a first circuit board, the first circuit board including at least a first pad and at least a second pad; providing a second circuit board, the second circuit board including at least A pressure bonding pad; performing a bonding process to form an adhesive layer for bonding the first circuit board and the second circuit board; performing a cutting process to cut the first circuit board, the adhesive layer and the second At least one of the circuit boards; and after performing the cutting process, forming at least one connection electrode to electrically connect the at least one second pad and the at least one compression pad, the at least one connection electrode is at least partially covered A first edge of the first circuit board, a second edge of the second circuit board and an adhesive edge of the adhesive layer, and the first edge of the first circuit board and the first edge of the second circuit board The two edges and the adhesive edge of the adhesive layer are substantially aligned with each other. The method for manufacturing an array substrate as described in item 11 of the patent application range, wherein the first edge of the first circuit board, the second edge of the second circuit board and the adhesive edge of the adhesive layer form a flat surface And the at least one connecting electrode at least partially covers the flat surface. The method for manufacturing an array substrate as described in item 11 of the patent application range, wherein the thickness of the adhesive layer is less than or equal to 10 microns. The method for manufacturing an array substrate as described in item 11 of the patent application scope further includes: forming an electrode protection layer on the at least one connection electrode. The method for manufacturing an array substrate as described in item 11 of the scope of the patent application further includes: before performing the dicing process, forming a first protective layer on the first circuit board. The method for manufacturing an array substrate as described in item 11 of the scope of patent application further includes: forming a second protective layer on the second circuit board before performing the dicing process. A manufacturing method of a display device, comprising: providing an array substrate as claimed in claim 1; and arranging at least one miniature light emitting element on the array substrate, and the at least one miniature light emitting element is electrically connected to the at least one first pad and The at least one second pad.

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