TWI576973B - Chip package and method for forming the same - Google Patents

Description

Chip package and method of manufacturing same

The present invention relates to a chip package and a method of fabricating the same, and more particularly to a chip package having a sense wafer.

The process of the conventional chip package involves a multi-pass patterning process and a material deposition process, which not only consumes production costs but also requires a long process time.

Therefore, there is a need for more simplified and fast chip packaging techniques.

Embodiments of the present invention provide a chip package including a substrate having an upper surface and a lower surface. A device region or sensing region is defined within the substrate, and a conductive pad is located on the upper surface of the substrate. At least two depressions, including an upper depression and a lower depression, extend from the upper surface of the base toward the lower surface of the base, wherein the bottom of the upper recess and the sidewall of the lower recess are adjacent to the same material to collectively form a side wall of the base. A conductive layer is electrically connected to the conductive pad and extends from the upper surface of the substrate to the sidewall of the substrate. An insulating layer is between the conductive layer and the semiconductor substrate.

Embodiments of the present invention provide a method of fabricating a chip package, including providing a substrate having an upper surface and a lower surface, wherein the substrate includes at least one device region or sensing region, and at least one conductive pad is disposed on the substrate surface. Forming at least two depressions in the substrate, including an upper depression and a depression The depression, wherein the bottom of the upper depression and the sidewall of the lower depression are adjacent to the same material, and wherein the sidewalls and the bottom of the depressions together form a side wall of the substrate. An insulating layer is formed on the upper surface of the substrate and in the recess. A conductive layer is formed on the insulating layer, wherein the conductive layer is electrically connected to the conductive pad and extends from the upper surface of the substrate to the sidewall of the substrate. The substrate is diced to form a plurality of discrete wafer packages.

100‧‧‧Semiconductor substrate

100a‧‧‧ upper surface

100b‧‧‧ lower surface

101‧‧‧ dielectric layer

102‧‧‧Device area/sensing area

104‧‧‧Electrical mat

111, 112, 113, 114‧‧‧ side

116‧‧‧Insulation

118‧‧‧ Conductive layer

120‧‧‧ boards

122‧‧‧Contact pads

124‧‧‧ solder balls

126‧‧‧Conductive structure/wiring

302‧‧‧passivation protective layer

304a, 304b, 304c, 306a‧‧‧

305‧‧‧ recessed passage

1A to 1D are cross-sectional views showing a step of forming a chip package in accordance with an embodiment of the present invention.

2A through 2C are cross-sectional views showing a chip package in accordance with various embodiments of the present invention.

3A through 3E are schematic plan views showing a chip package in accordance with various embodiments of the present invention.

The manner of making and using the embodiments of the present invention will be described in detail below. It should be noted, however, that the present invention provides many inventive concepts that can be applied in various specific forms. The specific embodiments discussed herein are merely illustrative of specific ways of making and using the invention, and are not intended to limit the scope of the invention. Moreover, repeated numbers or labels may be used in different embodiments. These repetitions are merely for the purpose of simplicity and clarity of the invention and are not to be construed as a limitation of the various embodiments and/or structures discussed. Furthermore, when a first material layer is referred to or on a second material layer, the first material layer is in direct contact with or separated from the second material layer by one or more other material layers.

The chip package of one embodiment of the present invention can be used to package micro-electromechanical System chip. However, the application is not limited thereto. For example, in the embodiment of the chip package of the present invention, it can be applied to various active or passive elements, digital circuits or analog circuits. The electronic components of an integrated circuit, for example, are related to opto electronic devices, micro electro mechanical systems (MEMS), micro fluidic systems, or utilizing heat, light, or A physical sensor that measures physical quantities such as pressure. In particular, a wafer scale package (WSP) process can be used for image sensing components, light-emitting diodes (LEDs), solar cells, RF circuits, Semiconductor wafers such as accelerators, gyroscopes, micro actuators, surface acoustic wave devices, process sensors, or ink printer heads Package.

The above wafer level packaging process mainly refers to cutting into a separate package after the packaging step is completed in the wafer stage. However, in a specific embodiment, for example, the separated semiconductor wafer is redistributed in a supporting crystal. On the circle, the encapsulation process can also be called a wafer level packaging process. In addition, the above wafer level packaging process is also applicable to a chip package in which a plurality of wafers having integrated circuits are arranged by a stack to form multi-layer integrated circuit devices.

1A to 1D are cross-sectional views showing a step of forming a chip package in accordance with an embodiment of the present invention.

As shown in FIG. 1A, a semiconductor substrate 100 having a Upper surface 100a and lower surface 100b. For example, the semiconductor substrate 100 is a germanium substrate. In one embodiment, the semiconductor substrate 100 is a germanium wafer to facilitate wafer level packaging.

As shown in FIG. 1A, a device region or sensing region 102 is defined in the semiconductor substrate 100. Electronic components can be formed within the device area or sensing area 102. In an embodiment, the semiconductor substrate 100 includes a plurality of device regions or sensing regions 102 therein. For example, in an embodiment, the device area or sensing area 102 is a sensing area (eg, a fingerprint identification area). Electronic components within the device region or sensing region 102 may be disposed on the upper surface 100a of the semiconductor substrate 100. In another embodiment, the electronic components within the device region or sensing region 102 can have a portion over the upper surface 100a of the semiconductor substrate 100. In still another embodiment, electronic components within the device region or sensing region 102 may be completely formed within the semiconductor substrate 100 and exposed from the upper surface 100a of the semiconductor substrate 100.

As shown in FIG. 1A, a dielectric layer 101 and a conductive pad 104 may be formed on the upper surface 100a of the semiconductor substrate 100. The conductive pad 104 is electrically connected to the electronic components in the device region or the sensing region 102 through an interconnect structure (not shown) formed in the dielectric layer 101. In an embodiment, a passivation layer 302 may be formed on the upper surface 100a of the semiconductor substrate 100. The passivation protective layer 302 can be patterned to expose the device region or sensing region 102 and the conductive pads 104. The passivation protective layer 302 may include, but is not limited to, a nitride, an oxide, an oxynitride, or a combination thereof. In another embodiment, the passivation protection layer 302 can remain on the device or sensing region 102 without being removed. Accordingly, the passivation protective layer 302 on the device region or sensing region 102 is shown in dashed lines in the drawings to indicate that it may or may not remain on the device region or sensing region 102.

Next, as shown in FIG. 1B, the passivation protective layer 302 and the dielectric layer 101 may be patterned to expose the semiconductor substrate 100 underneath. In one embodiment, a portion of the passivation protection layer 302 and the dielectric layer 101 are removed by an etching process. The etching process may include a dry etching process, a wet etching process, or a combination thereof. After performing the above etching process, a portion of the semiconductor substrate 100 may be removed.

Next, as shown in FIG. 1B, a recess or notch 304a is formed which extends in a direction from the upper surface 100a of the semiconductor substrate 100 toward the lower surface 100b of the semiconductor substrate 100. In an embodiment, the semiconductor substrate 100 can be selectively thinned prior to forming the recess 304a. In one embodiment, a portion of the semiconductor substrate 100 is removed from the upper surface 100a, such as through a patterning process (including a lithography process and an etch process) to form recesses 304a. Next, another portion of the semiconductor substrate 100 can be further removed, such as through a patterning process (including a lithography process and an etch process) to form a recess (or recess) 304b. The recess 304b extends in a direction from the bottom of the recess 304a toward the lower surface 100b of the semiconductor substrate 100. In one embodiment, the upper recess 304a and the lower recess 304b are connected to each other to form a recess channel 305 extending to two corners of the upper surface 100a of the semiconductor substrate 100, as shown in FIG. 3A. In one embodiment, the bottom of the upper recess 304a and the sidewall of the lower recess 304b are adjacent to the same material, for example, the bottom of the upper recess 304a and the sidewall of the lower recess 304b are adjacent to the semiconductor substrate 100.

The embodiments of the present invention are not limited thereto. In another embodiment, more recesses may be formed within the semiconductor substrate 100. All of the recessed sidewalls and bottom portion may form a sidewall of the semiconductor substrate 100. Additionally, the sidewalls of the recess (eg, recess 304a and/or recess 304b) may be perpendicular to the upper surface 100a of the semiconductor substrate 100. Or inclined to the upper surface 100a of the semiconductor substrate 100. Furthermore, the bottom of the recess 304a and the bottom of the recess 304b are not limited to be parallel to the upper surface 100a of the semiconductor substrate 100.

Next, as shown in FIG. 1C, an insulating material is deposited on the upper surface 100a of the semiconductor substrate 100, the sidewalls and the bottom of the recess 304a, and the sidewalls and the bottom of the recess 304b, and is patterned into an insulating layer 116. In an embodiment, the insulating layer 116 may have an opening to expose the device region or the sensing region 102. In another embodiment, the insulating layer 116 can cover the device region or the sensing region 102. Accordingly, the insulating layer 116 on the device region or sensing region 102 is shown in dashed lines in the drawings to indicate that it may or may not be located on the device region or sensing region 102.

Next, a patterned conductive layer 118 is formed on the insulating layer 116. In an embodiment, the insulating layer 116 may be an oxide, a nitride, an oxynitride or a combination thereof, and may be formed by a chemical vapor deposition process, but is not limited thereto. The patterned conductive layer 118 can comprise copper, aluminum, nickel, gold, platinum, or a combination thereof.

As shown in FIG. 1C, the conductive layer 118 is electrically connected to the conductive pad 104 and extends from the upper surface 100a of the semiconductor substrate 100 to the sidewalls and bottom of the recess 304a and the recess 304b.

Next, as shown in FIG. 1C, in one embodiment, the semiconductor substrate 100 is diced along predetermined scribe lines (not shown) of the semiconductor substrate 100 to form a plurality of discrete wafer packages. Since the conductive layer 118 electrically connected to the conductive pad 104 extends to the sidewall of the chip package (ie, the conductive layer 118 extends from the upper surface 100a of the semiconductor substrate 100 to the sidewall of the semiconductor substrate 100), the conductive path may be from the semiconductor substrate Upper surface of 100 100a is guided downward through the sidewall of the semiconductor substrate 100.

As shown in FIG. 1D, in an embodiment, the formed chip package may be further disposed on a circuit board 120. In an embodiment, the circuit board 120 includes a contact pad 122 thereon. The contact pads 122 are electrically connected to the wires in the circuit board 120 and serve as a contact point for electrically connecting to the device region or the sensing region 102 in the chip package. As shown in the embodiment of FIG. 1D, a conductive structure (eg, bonding wire) 126 is formed on the sidewalls of the contact pads 122 on the circuit board 120 and the recesses (eg, recesses 304b) located within the semiconductor substrate 100 and / or between the conductive layers 118 on the bottom.

A conductive structure (eg, wiring) 126 is formed between the contact pads 122 and the conductive layer 118 on the lower portion of the semiconductor substrate 100. As such, the conductive structure (eg, wiring) 126 can be substantially lower than the upper surface 100a of the semiconductor substrate 100, and thus the overall height of the formed chip package can be significantly reduced.

The embodiments of the present invention are not limited thereto. 2A through 2C are schematic cross-sectional views of a chip package in accordance with various embodiments of the present invention, wherein like or similar reference numerals are used to designate the same or similar elements.

As shown in FIG. 2A, the sidewall of the recess 304b is inclined to the upper surface 100a of the semiconductor substrate 100. As a result, the reliability of the conductive layer 118 formed on the sidewall of the recess 304b can be improved. Additionally, a conductive structure (e.g., wiring) 126 can be formed between the contact pads 122 on the circuit board 120 and the sidewalls of the recess 304a and/or the conductive layer 118 on the bottom. In another embodiment, more than two recesses may be formed in the semiconductor substrate 100 to form a step-like sidewall. The electrically conductive structure (e.g., wiring) 126 can directly contact the conductive layer 118 on the sidewalls and/or bottom of any of the plurality of depressions, such as depressions 304a, 304b in Figure 2C. And 304c.

It can be understood that the embodiments of the present invention are not limited to the use of wires as the conductive structure connecting the circuit board and the wafer. In another embodiment, other conductive structures (eg, conductive layers, conductive bumps, solder balls, or solder wires) may be employed in place of the wires 126. For example, in the embodiment of FIG. 2B, solder balls 124 are used in place of wiring 126. Accordingly, any electrically conductive structure suitable for forming a conductive path between contact pad 122 and conductive layer 118 is encompassed within the scope of embodiments of the present invention.

3A through 3E are schematic plan views of a chip package in accordance with various embodiments of the present invention, wherein the same or similar reference numerals are used to designate the same or similar elements.

As shown in FIG. 3A, the recess 304a and the recess 304b extend across the entire length of one side 111 of the semiconductor substrate 100. While FIG. 3A depicts the recess 304a and the recess 304b all extending across the entire length of the side edge 111, in other embodiments, only the recess 304a (lower recess) may extend across the full length of the side edge 111. FIG. 3B depicts a different embodiment in which the recess 304a extends further along at least a portion of the length of the adjacent one side 112. FIG. 3C depicts another embodiment in which the recess 304a extends further along at least a portion of the length of the adjacent two sides 112 and 114. In other embodiments, the recesses 304a may extend continuously across the entire length of two, three, or even four sides of the semiconductor substrate 100.

As shown in FIG. 3D, two separate recesses 304a and recesses 306a are formed on opposite side edges 111 and 113 of the semiconductor substrate 100. The recess 304a and the recess 306a extend across the entire length of the side 111 and the opposite side 113 of the semiconductor substrate 100, respectively. Similarly, the recess 304a and the recess 306a can each be further The step extends to one or both of the adjacent sides. For example, as shown in FIG. 3E, the recess 304a further extends along a portion of the length of the adjacent side 112. Therefore, although not shown in the drawings, those of ordinary skill in the art can appreciate that the recess 304a and the recess 306a may have other recesses as long as the recess extends across the entire length or width of one side of the semiconductor substrate 100. Configuration method.

According to the above embodiment of the present invention, a recess is formed on a front surface of the wafer (ie, a side on which the device region or the sensing region is formed), and a conductive layer electrically connected to the device region or the sensing region is along the sidewall of the recess form. The required conductive wiring can be formed smoothly, and the patterning process steps required in the wafer packaging process can be greatly reduced. As a result, process time and production costs can be significantly reduced. In addition, the overall height of the formed chip package can be significantly reduced.

Moreover, the recesses span the full width or length of the semiconductor substrate 100 to increase the layout flexibility of the output signals of the chip package.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Semiconductor substrate

100a‧‧‧ upper surface

100b‧‧‧ lower surface

102‧‧‧Device area/sensing area

104‧‧‧Electrical mat

116‧‧‧Insulation

118‧‧‧ Conductive layer

120‧‧‧ boards

122‧‧‧Contact pads

126‧‧‧Conductive structure/wiring

302‧‧‧passivation protective layer

304a, 304b‧‧‧ dent

Claims (26)

A chip package comprising: a substrate having an upper surface and a lower surface; a device region or a sensing region defined in the substrate; a conductive pad on the upper surface of the substrate; at least two recesses The upper surface of the substrate extends toward the lower surface of the substrate, wherein the bottom of the upper recess and the sidewall of the lower recess are adjacent to the same material to form a side wall of the substrate; And a conductive layer electrically connected to the conductive pad and extending from the upper surface of the substrate to the sidewall of the substrate; and a first insulating layer between the conductive layer and the substrate. The chip package of claim 1, wherein the sidewall of the substrate has at least a portion inclined to the upper surface of the substrate. The chip package of claim 1, wherein the substrate comprises a semiconductor substrate and a second insulating layer, the second insulating layer is formed on the surface of the semiconductor substrate, and at least the bottom of the upper recess and the lower portion The sidewalls of the recess are adjacent to the semiconductor substrate. The chip package of claim 1, further comprising a circuit board, wherein the substrate is disposed on the circuit board, and the conductive layer is electrically connected to a contact pad on the circuit board through a conductive structure . The chip package of claim 4, wherein the conductive structure is a solder ball or a wire. The chip package of claim 5, wherein the conductive junction The solder ball is constructed and located at a corner between the substrate and the circuit board. The chip package of claim 5, wherein the conductive structure is the wire and is disposed on the conductive layer above the sidewall of the substrate. The chip package of claim 7, wherein the wiring is disposed on the conductive layer above a bottom of one of the recesses. The chip package of claim 4, wherein the conductive structure is disposed between the circuit board and the upper surface of the substrate. The chip package of claim 1, wherein the substrate comprises a semiconductor substrate and a second insulating layer adjacent to the semiconductor substrate and connected to each other. The chip package of claim 1, wherein the device area or the sensing area comprises a fingerprint identification area. The chip package of claim 1, wherein one of the depressions extends across a full length of one side of the substrate. The chip package of claim 12, wherein one of the depressions extends further along at least a portion of the length of the other side adjacent the side edge. The chip package of claim 12, wherein one of the depressions extends further along at least a portion of a length of two side edges adjacent the side edge. A method of fabricating a chip package, comprising: providing a substrate having an upper surface and a lower surface, wherein the substrate comprises at least one device region or sensing region, and at least one conductive pad is disposed on the upper surface of the substrate ; Forming at least two depressions in the substrate, including an upper depression and a lower depression, wherein the bottom of the upper depression and the sidewall of the lower depression are adjacent to the same material, and the sidewalls and the bottom of the depressions together form a side wall of the substrate Forming a first insulating layer on the upper surface of the substrate and the recesses; forming a conductive layer on the first insulating layer electrically connected to the conductive pad, and from the upper surface of the substrate Extending to the sidewall of the substrate; and cutting the substrate to form a plurality of discrete wafer packages. The method of manufacturing a chip package according to claim 15, further comprising thinning the substrate before forming the recesses. The method of manufacturing a chip package according to claim 15, further comprising: providing a circuit board having a contact pad; disposing the substrate on the circuit board; and forming a conductive structure, the electrical property thereof The contact pad and the conductive layer are connected. The method of manufacturing a chip package according to claim 17, wherein the conductive structure is a solder ball or a wire. The method of manufacturing a chip package according to claim 17, wherein the conductive structure is disposed between the circuit board and the upper surface of the substrate. The method of fabricating a chip package according to claim 19, wherein the conductive structure directly contacts the conductive layer above a bottom of one of the recesses. The method of manufacturing a chip package according to claim 15, wherein the substrate comprises a semiconductor substrate and a second insulating layer, wherein the second insulating layer is formed on the surface of the semiconductor substrate, and at least the upper recess bottom And the sidewall of the lower recess is adjacent to the semiconductor substrate. The method of manufacturing a chip package according to claim 17, wherein the substrate comprises a semiconductor substrate and a second insulating layer, the second insulating layer is formed on the surface of the semiconductor substrate, and the step of forming the recesses comprises Removing the second insulating layer and a portion of the semiconductor substrate to form the upper recess; and removing another portion of the semiconductor substrate to form the lower recess to connect with the upper recess. The method of manufacturing a chip package according to claim 15, wherein the depressions are formed by an etching process. The method of fabricating a chip package of claim 15, wherein one of the depressions extends across a full length of one side of the substrate. The method of fabricating a chip package of claim 24, wherein one of the depressions extends further along at least a portion of a length of the other side adjacent the side edge. The method of fabricating a chip package according to claim 24, wherein one of the depressions extends along at least a portion of a length of two side edges adjacent to the side.