TW201501261A - Quad flat no leads package and method of manufacture - Google Patents

Quad flat no leads package and method of manufacture Download PDF

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Publication number
TW201501261A
TW201501261A TW102122115A TW102122115A TW201501261A TW 201501261 A TW201501261 A TW 201501261A TW 102122115 A TW102122115 A TW 102122115A TW 102122115 A TW102122115 A TW 102122115A TW 201501261 A TW201501261 A TW 201501261A
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Taiwan
Prior art keywords
pad
region
recess
mounting region
wafer
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TW102122115A
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Chinese (zh)
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TWI480995B (en
Inventor
張永霖
陳美娜
賴雅怡
王愉博
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矽品精密工業股份有限公司
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Priority to TW102122115A priority Critical patent/TWI480995B/en
Priority to CN201310261637.1A priority patent/CN104241232B/en
Publication of TW201501261A publication Critical patent/TW201501261A/en
Application granted granted Critical
Publication of TWI480995B publication Critical patent/TWI480995B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item

Abstract

Disclosed is a quad fiat no leads (QFN) package and its method of manufacture, the method comprising providing a substrate having upper and lower surfaces, the upper surface having a chip mounting area defined thereon, a first solder pad disposing area surrounding the chip mounting area, and a second solder pad disposing area surrounding the first solder pad disposing area, wherein a gap exists between the first and second solder pad disposing areas; forming a recessed portion on the lower surface at a position corresponding to the first solder pad disposing area and close to the peripheral of the gap; forming a plurality of first and second solder pads respectively on the first and second solder pad disposing areas; disposing a chip in the chip mounting area and electrically connecting the chip to the first and second solder pads respectively via a plurality of solder wires; forming an encapsulant on the upper surface of the substrate and filling the encapsulant into the recessed portion; and forming an opening penetrating through the upper and lower surfaces at a position corresponding to the gap.

Description

四方扁平無接腳封裝件及其製法 Quad flat no-pin package and its preparation method

本發明係有關於一種封裝件及其製法，尤指一種四方扁平無接腳封裝件及其製法。 The invention relates to a package and a preparation method thereof, in particular to a quad flat no-pin package and a preparation method thereof.

四方扁平無接腳(Quad Flat No Lead，簡稱QFN)封裝件為一種使晶片座和導腳底面外露於封裝膠體底部表面的封裝單元，一般係採用表面黏著技術(surface mount technology，簡稱SMT)將四方扁平無接腳封裝件接置於印刷電路板上，藉此以形成一具有特定功能之電路模組。 The Quad Flat No Lead (QFN) package is a package unit that exposes the wafer holder and the bottom surface of the lead to the bottom surface of the encapsulant. Generally, the surface mount technology (SMT) will be used. The quad flat no-pin package is placed on the printed circuit board to form a circuit module having a specific function.

第1圖所示者，係習知之四方扁平無接腳封裝件之剖面圖。如圖所示，其係以導線架做為封裝件的承載件，該導線架的中央具有一晶片座(die pad)100，該晶片座100之上表面外緣及圍繞該晶片座100之基材100a之上表面內緣係分別具有複數第一銲墊102c及複數第二銲墊102d，該第一銲墊102c與該第二銲墊102d之間係預設有貫通該導線架之上下表面的開口108。此外，該晶片座100之下表面外緣係具有凹部104，該凹部104係用於提供封裝膠體106與該晶片座100之間的額外結合力。晶片101係藉 由例如銀膠的黏著層以設置於該晶片座100之上表面的中央部分，接著，利用複數銲線105將晶片101分別電性連接至該第一銲墊102c及該第二銲墊102d，此時，在對應該第一銲墊102c之該晶片座100的下表面具有該凹部104的情況下，因打線時尚未包覆有該封裝膠體106，所以整體結構的剛性較為不足，使得設置該銲線105時的壓力會造成該晶片座100的偏移，從而造成該銲線105的短路。 The figure shown in Fig. 1 is a cross-sectional view of a conventional quad flat no-pin package. As shown in the figure, the lead frame is used as a carrier for the package. The lead frame has a die pad 100 at the center thereof, and an outer edge of the upper surface of the wafer holder 100 and a base surrounding the wafer holder 100. The upper surface of the upper surface of the material 100a has a plurality of first pads 102c and a plurality of second pads 102d. The first pads 102c and the second pads 102d are pre-formed through the upper surface of the lead frame. Opening 108. In addition, the outer edge of the lower surface of the wafer holder 100 has a recess 104 for providing additional bonding force between the encapsulant 106 and the wafer holder 100. Wafer 101 is borrowed The wafer 101 is electrically connected to the first pad 102c and the second pad 102d by a plurality of bonding wires 105, respectively, by an adhesive layer such as a silver paste, which is disposed on a central portion of the upper surface of the wafer holder 100. At this time, in the case where the concave portion 104 is provided on the lower surface of the wafer holder 100 corresponding to the first pad 102c, since the encapsulant 106 is not covered by the wire bonding, the rigidity of the entire structure is insufficient, so that the rigidity is set. The pressure at the bonding wire 105 causes an offset of the wafer holder 100, causing a short circuit of the bonding wire 105.

因此，如何避免上述習知技術中之種種問題，實已成為目前亟欲解決的課題。 Therefore, how to avoid various problems in the above-mentioned prior art has become a problem that is currently being solved.

有鑒於上述習知技術之缺失，本發明提供一種四方扁平無接腳封裝件之製法，係包括：提供一基材，該基材係具有上表面及下表面，且該上表面係具有晶片安裝區域、圍繞該晶片安裝區域的第一銲墊設置區域、及圍繞該第一銲墊設置區域的第二銲墊設置區域，且該第一銲墊設置區域與該第二銲墊設置區域之間係具有間隙；於該下表面形成未貫通該基材之凹部，且該凹部之位置係對應該第一銲墊設置區域靠近該間隙之外緣；在該第一銲墊設置區域及該第二銲墊設置區域中分別形成複數第一銲墊和複數第二銲墊；將晶片設置在該晶片安裝區域中，且藉由複數銲線將該晶片分別電性連接到該第一銲墊和該第二銲墊；於該基材之上表面上形成包覆該晶片、該銲線、該第一銲墊和該第二銲墊的封裝膠體，且將該封裝膠體填入該凹部中；以及在對應該間隙的位置處形成貫穿該上表面與下表面的 開口，且該開口係外露該凹部中的封裝膠體之側表面。 In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for manufacturing a quad flat no-pin package, comprising: providing a substrate having an upper surface and a lower surface, and the upper surface has a wafer mounting a region, a first pad mounting region surrounding the wafer mounting region, and a second pad mounting region surrounding the first pad pad region, and between the first pad pad region and the second pad pad region Having a gap; forming a recess that does not penetrate the substrate on the lower surface, and the position of the recess is corresponding to the outer edge of the gap in the first pad setting region; and the second pad setting region and the second portion Forming a plurality of first pads and a plurality of second pads respectively in the pad setting region; disposing the wafer in the wafer mounting region, and electrically connecting the wafers to the first pads and the wires respectively by a plurality of bonding wires a second solder pad; forming an encapsulant covering the wafer, the bonding wire, the first bonding pad and the second bonding pad on the upper surface of the substrate, and filling the encapsulant into the recess; In the corresponding gap At formed penetrating the upper surface and the lower surface Opening, and the opening exposes a side surface of the encapsulant in the recess.

又，本發明提供一種四方扁平無接腳封裝件，係包括：基材，係具有上表面及下表面，且該上表面係具有晶片安裝區域、圍繞該晶片安裝區域的第一銲墊設置區域、及圍繞該第一銲墊設置區域的第二銲墊設置區域，且該第一銲墊設置區域與該第二銲墊設置區域之間係具有間隙；複數第一銲墊及複數第二銲墊，係分別形成在該第一銲墊設置區域及該第二銲墊設置區域中；凹部，係形成在該下表面，該凹部之位置係位在對應該第一銲墊設置區域靠近該間隙之外緣，另該凹部並未貫通該基材；晶片，係設置在該晶片安裝區域中；複數銲線，係將該晶片分別電性連接到該第一銲墊及該第二銲墊；封裝膠體，係形成於該基材之上表面上，以包覆該晶片、該銲線、及該第一銲墊和該第二銲墊，且填入該凹部中；以及開口，係對應貫穿該上表面與下表面，且該開口係外露該凹部中的封裝膠體之側表面。 Moreover, the present invention provides a quad flat no-pin package comprising: a substrate having an upper surface and a lower surface, the upper surface having a wafer mounting region and a first pad mounting region surrounding the wafer mounting region And a second pad setting region surrounding the first pad pad region, and the first pad pad region and the second pad pad region have a gap; the plurality of first pads and the plurality of second pads Pads are respectively formed in the first pad setting area and the second pad setting area; a recess is formed on the lower surface, and the position of the recess is located adjacent to the gap corresponding to the first pad setting area The outer edge, the recess does not penetrate the substrate; the wafer is disposed in the wafer mounting region; the plurality of bonding wires are electrically connected to the first pad and the second pad respectively; The encapsulant is formed on the upper surface of the substrate to cover the wafer, the bonding wire, and the first pad and the second pad, and is filled in the recess; and the opening is correspondingly penetrated The upper surface and the lower surface, and the opening Based encapsulant exposed side surface of the recess.

由上可知，由於本發明係於打線形成該等銲線之後，才形成貫穿之開口，所以晶片座不會於打線時偏移，進而能增進打線品質與良率。 As can be seen from the above, since the present invention forms an opening through which the wire is formed after the wire is formed, the wafer holder does not shift at the time of wire bonding, and the wire quality and yield can be improved.

100‧‧‧晶片座 100‧‧‧ Wafer holder

100a、300‧‧‧基材 100a, 300‧‧‧ substrate

300a‧‧‧上表面 300a‧‧‧ upper surface

300b‧‧‧下表面 300b‧‧‧ lower surface

301a‧‧‧晶片安裝區域 301a‧‧‧ wafer mounting area

101、301‧‧‧晶片 101, 301‧‧‧ wafer

302a‧‧‧第一銲墊設置區域 302a‧‧‧First pad setting area

302b‧‧‧第二銲墊設置區域 302b‧‧‧Second pad setting area

102c、302c‧‧‧第一銲墊 102c, 302c‧‧‧ first pad

102d、302d‧‧‧第二銲墊 102d, 302d‧‧‧second solder pad

303a‧‧‧間隙 303a‧‧‧ gap

104、304‧‧‧凹部 104, 304‧‧‧ recess

105、305‧‧‧銲線 105, 305‧‧‧ welding line

106、306‧‧‧封裝膠體 106, 306‧‧‧Package colloid

307‧‧‧金屬層 307‧‧‧metal layer

108、308‧‧‧開口 108, 308‧‧‧ openings

311‧‧‧側表面 311‧‧‧ side surface

第1圖係說明習知之四方平面無引腳封裝件之剖面圖；第2A至2F圖所示者係本發明之四方扁平無接腳封裝件之製法的一實施例的剖面圖；以及 第3A至3B圖所示者係本發明之四方扁平無接腳封裝件之製法的另一實施例的剖面圖。 1 is a cross-sectional view showing a conventional quad flat no-lead package; and FIGS. 2A to 2F are cross-sectional views showing an embodiment of a method of fabricating the quad flat unpinped package of the present invention; 3A to 3B are cross-sectional views showing another embodiment of the method of fabricating the quad flat no-pin package of the present invention.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered.

同時，本說明書中所引用之如「上」、「外緣」、「內緣」、「對應」及「側」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 In the meantime, the terms "upper", "outer edge", "inner edge", "corresponding" and "side" are used in this specification for convenience of description and are not intended to limit the invention. Changes in the scope of implementation, changes or adjustments in their relative relationship, are considered to be within the scope of the present invention.

第2A至2F圖係說明本發明之四方扁平無接腳封裝件之製法的剖視圖。 2A to 2F are cross-sectional views illustrating the method of fabricating the quad flat no-pin package of the present invention.

如第2A圖所示，首先，提供一基材300，該基材300係具有上表面300a及下表面300b，且該上表面300a係具有晶片安裝區域301a、圍繞該晶片安裝區域301a的第一銲墊設置區域302a及圍繞該第一銲墊設置區域302a的第二 銲墊設置區域302b，且該第一銲墊設置區域302a與該第二銲墊設置區域302b之間係具有間隙303a。 As shown in FIG. 2A, first, a substrate 300 having an upper surface 300a and a lower surface 300b having a wafer mounting region 301a and a first surrounding the wafer mounting region 301a is provided. a pad setting area 302a and a second surrounding the first pad setting area 302a The pad pad region 302b is provided with a gap 303a between the first pad pad region 302a and the second pad pad region 302b.

如第2B圖所示，在該下表面300b處形成未貫通該基材300之凹部304，且該凹部304之位置係對應該第一銲墊設置區域302a靠近該間隙303a之外緣。 As shown in FIG. 2B, a recess 304 that does not penetrate the substrate 300 is formed at the lower surface 300b, and the position of the recess 304 corresponds to the outer edge of the gap 303a corresponding to the first pad installation region 302a.

在本發明的另一實施例中，該凹部304可選擇性地延伸進入至對應於該晶片安裝區域301a的該下表面300b處，或是可選擇性地延伸進入至對應於該間隙303a及該第二銲墊設置區域302b的該下表面300b處。 In another embodiment of the present invention, the recess 304 can be selectively extended into the lower surface 300b corresponding to the wafer mounting region 301a, or can be selectively extended to correspond to the gap 303a and the The second pad is disposed at the lower surface 300b of the region 302b.

在本發明的又另一實施例中，該凹部304可選擇性地呈圍繞狀，且該凹部304可從該第一銲墊設置區域302a靠近該間隙303a的外緣延伸至該晶片安裝區域301a靠近該第一銲墊設置區域302a的外緣。 In still another embodiment of the present invention, the recess 304 may be selectively surrounded, and the recess 304 may extend from the first pad setting region 302a near the outer edge of the gap 303a to the wafer mounting region 301a. Adjacent to the outer edge of the first pad setting region 302a.

如第2C圖所示，在該第一銲墊設置區域302a及該第二銲墊設置區域302b中分別形成複數第一銲墊302c和複數第二銲墊302d。 As shown in FIG. 2C, a plurality of first pads 302c and a plurality of second pads 302d are formed in the first pad mounting region 302a and the second pad mounting region 302b, respectively.

該等第一銲墊302c和第二銲墊302d可藉由使用例如為光阻(未圖示)及曝光顯影之方法在該第一銲墊設置區域302a及該第二銲墊設置區域302b處形成光阻開口(未圖示)，其後再以例如為電鍍或濺鍍之方法形成該等第一銲墊302c和第二銲墊302d，但本發明並不限於此。 The first pad 302c and the second pad 302d can be at the first pad setting region 302a and the second pad setting region 302b by using, for example, a photoresist (not shown) and exposure development. A photoresist opening (not shown) is formed, and thereafter the first pad 302c and the second pad 302d are formed by, for example, plating or sputtering, but the present invention is not limited thereto.

此外，形成該第一銲墊302c和該第二銲墊302d之材質可為鎳(Ni)、鈀(Pd)或金(Au)，但本發明並不限於此。 In addition, the material of the first pad 302c and the second pad 302d may be nickel (Ni), palladium (Pd) or gold (Au), but the invention is not limited thereto.

本發明復可在形成該第一銲墊302c和該第二銲墊302d時，在對應該第一銲墊設置區域302a、第二銲墊設置區域302b、該晶片安裝區域301a之該下表面300b及該凹部304底面與靠近該晶片安裝區域301a的側表面上形成例如為線路的金屬層307。 The present invention can be applied to the first pad 302c and the second pad 302d in correspondence with the first pad setting region 302a, the second pad mounting region 302b, and the lower surface 300b of the wafer mounting region 301a. A metal layer 307, such as a line, is formed on the bottom surface of the recess 304 and the side surface adjacent to the wafer mounting region 301a.

如第2D圖所示，將晶片301設置在該晶片安裝區域301a中，且藉由複數銲線305將該晶片301分別電性連接到該第一銲墊302c和該第二銲墊302d。此時，對應於該間隙303a之該基材300可提供足夠之支撐力，以避免於打線時承載該第一銲墊302c和該第二銲墊302d的基材300變形與偏移，進而避免打線失敗。 As shown in FIG. 2D, the wafer 301 is disposed in the wafer mounting region 301a, and the wafer 301 is electrically connected to the first pad 302c and the second pad 302d, respectively, by a plurality of bonding wires 305. At this time, the substrate 300 corresponding to the gap 303a can provide sufficient supporting force to avoid deformation and offset of the substrate 300 carrying the first pad 302c and the second pad 302d during wire bonding, thereby avoiding The line failed.

該等銲線305之材料係可使用例如為金或其合金的導電性材料，但本發明並不限於此。 The material of the bonding wires 305 may be a conductive material such as gold or an alloy thereof, but the present invention is not limited thereto.

如第2E圖所示，在該基材300之上表面300a上形成包覆該晶片301、該銲線305、該第一銲墊302c和該第二銲墊302d的封裝膠體306，且將該封裝膠體306填入該凹部304中。 As shown in FIG. 2E, an encapsulant 306 covering the wafer 301, the bonding wire 305, the first bonding pad 302c, and the second bonding pad 302d is formed on the upper surface 300a of the substrate 300, and The encapsulant 306 is filled into the recess 304.

如第2F圖所示，在對應該間隙303a的位置處形成貫穿該上表面300a與下表面300b的開口308，且該開口308係外露該凹部304中的封裝膠體306之側表面311。此外，可使用蝕刻、雷射、或刀具切割形成該開口308，但本發明並不限於此。 As shown in FIG. 2F, an opening 308 penetrating the upper surface 300a and the lower surface 300b is formed at a position corresponding to the gap 303a, and the opening 308 exposes the side surface 311 of the encapsulant 306 in the recess 304. Further, the opening 308 may be formed using etching, laser, or cutter cutting, but the invention is not limited thereto.

本發明復提供之一種四方扁平無接腳封裝件，係包括基材300，該基材300係具有上表面300a及下表面300b， 且該上表面300a之中央區域係具有晶片安裝區域301a、圍繞該晶片安裝區域301a的第一銲墊設置區域302a、及圍繞該第一銲墊設置區域302a的第二銲墊設置區域302b，且該第一銲墊設置區域302a與該第二銲墊設置區域之間係具有間隙303a。 A quad flat no-pin package provided by the present invention includes a substrate 300 having an upper surface 300a and a lower surface 300b. The central region of the upper surface 300a has a wafer mounting region 301a, a first pad mounting region 302a surrounding the wafer mounting region 301a, and a second pad mounting region 302b surrounding the first pad mounting region 302a, and A gap 303a is formed between the first pad setting region 302a and the second pad setting region.

本實施例係包括複數第一銲墊302c及複數第二銲墊302d，其係分別形成在該第一銲墊設置區域302a及該第二銲墊設置區域302b中。該等第一銲墊302c和第二銲墊302d可藉由使用例如為光阻(未圖示)及曝光顯影之方法在該第一銲墊設置區域302a及該第二銲墊設置區域302b處形成光阻開口(未圖示)，其後再以例如為電鍍或濺鍍之方法形成該等第一銲墊302c和第二銲墊302d，但本發明並不限於此。其中，形成該第一銲墊302c和該第二銲墊302d之材質係為鎳(Ni)、鈀(Pd)或金(Au)，但本發明並不限於此。 The embodiment includes a plurality of first pads 302c and a plurality of second pads 302d formed in the first pad setting region 302a and the second pad setting region 302b, respectively. The first pad 302c and the second pad 302d can be at the first pad setting region 302a and the second pad setting region 302b by using, for example, a photoresist (not shown) and exposure development. A photoresist opening (not shown) is formed, and thereafter the first pad 302c and the second pad 302d are formed by, for example, plating or sputtering, but the present invention is not limited thereto. The material of the first pad 302c and the second pad 302d is nickel (Ni), palladium (Pd) or gold (Au), but the invention is not limited thereto.

本實施例復包括金屬層307，係形成在對應該第一銲墊設置區域302a、第二銲墊設置區域302b、該晶片安裝區域301a之該下表面300b及該凹部304底面與靠近該晶片安裝區域301a的側表面上。 The embodiment further includes a metal layer 307 formed on the first pad disposed region 302a, the second pad disposed region 302b, the lower surface 300b of the wafer mounting region 301a, and the bottom surface of the recess 304 and mounted adjacent to the wafer. On the side surface of the area 301a.

本實施例係包括複數凹部304，其係形成在該下表面300b，該凹部304之位置係位在對應該第一銲墊設置區域302a靠近該間隙303a之外緣，另該凹部304並未貫通該基材300。 The embodiment includes a plurality of recesses 304 formed on the lower surface 300b. The position of the recesses 304 is located adjacent to the outer edge of the gap 303a corresponding to the first pad setting region 302a, and the recess 304 is not penetrated. The substrate 300.

在本發明的另一實施例中，該凹部304可選擇性地延 伸進入至對應於該晶片安裝區域301a的該下表面300b處，或是可選擇性地延伸進入至對應於該間隙303a及該第二銲墊設置區域302b的該下表面300b處。 In another embodiment of the invention, the recess 304 is selectively extendable Extending into the lower surface 300b corresponding to the wafer mounting region 301a, or selectively extending into the lower surface 300b corresponding to the gap 303a and the second pad setting region 302b.

在本發明的又另一實施例中，該凹部304可選擇性地呈圍繞狀，且該凹部304可從該第一銲墊設置區域302a靠近該間隙303a的外緣延伸至該晶片安裝區域301a靠近該第一銲墊設置區域302a的外緣。 In still another embodiment of the present invention, the recess 304 may be selectively surrounded, and the recess 304 may extend from the first pad setting region 302a near the outer edge of the gap 303a to the wafer mounting region 301a. Adjacent to the outer edge of the first pad setting region 302a.

本實施例係包括晶片301，其係設置在該晶片安裝區域301a中，及複數銲線305，其係將該晶片301分別電性連接到該第一銲墊302c及該第二銲墊302b。 The present embodiment includes a wafer 301 disposed in the wafer mounting region 301a and a plurality of bonding wires 305 electrically connected to the first bonding pad 302c and the second bonding pad 302b, respectively.

該等銲線305之材料係可使用例如為金或其合金的導電性材料，但本發明並不限於此。 The material of the bonding wires 305 may be a conductive material such as gold or an alloy thereof, but the present invention is not limited thereto.

本實施例係包括封裝膠體306，係形成於該基材300之上表面300a上，以包覆該晶片301、該銲線305、及該第一銲墊302c和該第二銲墊302d，且填入該凹部304中。 The embodiment includes an encapsulant 306 formed on the upper surface 300a of the substrate 300 to cover the wafer 301, the bonding wire 305, the first bonding pad 302c and the second bonding pad 302d, and The recess 304 is filled in.

本實施例係包括開口308，其係對應該間隙303a貫穿該上表面300a與下表面300b，且該開口308係外露該凹部304中的封裝膠體306之側表面311。 The embodiment includes an opening 308 through which the gap 303a extends through the upper surface 300a and the lower surface 300b, and the opening 308 exposes the side surface 311 of the encapsulant 306 in the recess 304.

此外，可使用蝕刻、雷射、或刀具切割形成該開口308，但本發明並不限於此。 Further, the opening 308 may be formed using etching, laser, or cutter cutting, but the invention is not limited thereto.

又，本發明進一步提供另一個實施例，請參照第3A至3B圖，其與上述第2A至2F圖之實施例的差異係在於，該下表面300b及該凹部304的表面上未形成該金屬層307。 Furthermore, the present invention further provides another embodiment. Referring to FIGS. 3A to 3B, the difference from the embodiment of FIGS. 2A to 2F is that the metal is not formed on the surface of the lower surface 300b and the recess 304. Layer 307.

綜上所述，相較於習知技術，由於本發明係於打線形 成該等銲線之後，才形成貫穿之開口，所以整體結構具有較佳之剛性，使得晶片座不會於打線時偏移，進而能增進打線品質與良率。 In summary, the present invention is based on the prior art. After the wire is formed, the through opening is formed, so that the overall structure has better rigidity, so that the wafer holder does not shift when the wire is wound, thereby improving the quality and yield of the wire.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

300‧‧‧基材 300‧‧‧Substrate

300a‧‧‧上表面 300a‧‧‧ upper surface

300b‧‧‧下表面 300b‧‧‧ lower surface

301‧‧‧晶片 301‧‧‧ wafer

302c‧‧‧第一銲墊 302c‧‧‧First pad

302d‧‧‧第二銲墊 302d‧‧‧Second pad

304‧‧‧凹部 304‧‧‧ recess

305‧‧‧銲線 305‧‧‧welding line

306‧‧‧封裝膠體 306‧‧‧Package colloid

307‧‧‧金屬層 307‧‧‧metal layer

308‧‧‧開口 308‧‧‧ openings

311‧‧‧側表面 311‧‧‧ side surface

Claims (11)

一種四方扁平無接腳封裝件之製法，係包括：提供一基材，該基材係具有上表面及下表面，且該上表面係具有晶片安裝區域、圍繞該晶片安裝區域的第一銲墊設置區域、及圍繞該第一銲墊設置區域的第二銲墊設置區域，且該第一銲墊設置區域與該第二銲墊設置區域之間係具有間隙；於該下表面形成未貫通該基材之凹部，且該凹部之位置係對應該第一銲墊設置區域靠近該間隙之外緣；在該第一銲墊設置區域及該第二銲墊設置區域中分別形成複數第一銲墊和複數第二銲墊；將晶片設置在該晶片安裝區域中，且藉由複數銲線將該晶片分別電性連接到該第一銲墊和該第二銲墊；於該基材之上表面上形成包覆該晶片、該銲線、該第一銲墊和該第二銲墊的封裝膠體，且將該封裝膠體填入該凹部中；以及在對應該間隙的位置處形成貫穿該上表面與下表面的開口，且該開口係外露該凹部中的封裝膠體之側表面。 A method for fabricating a quad flat no-pin package includes providing a substrate having an upper surface and a lower surface, the upper surface having a wafer mounting region and a first pad surrounding the wafer mounting region a second region and a second pad disposed region surrounding the first pad pad region, and a gap between the first pad pad region and the second pad pad region; a recessed portion of the substrate, wherein the recess is located adjacent to the outer edge of the gap; and the plurality of first pads are respectively formed in the first pad disposed region and the second pad disposed region And a plurality of second pads; the wafer is disposed in the wafer mounting region, and the wafer is electrically connected to the first pad and the second pad respectively by a plurality of bonding wires; on the surface of the substrate Forming an encapsulant covering the wafer, the bonding wire, the first bonding pad and the second bonding pad, and filling the encapsulant into the recess; and forming a through surface at a position corresponding to the gap With the opening of the lower surface, The openings on the exposed side surfaces of the recess of the encapsulant. 如申請專利範圍第1項所述之四方扁平無接腳封裝件之製法，在形成該第一銲墊和該第二銲墊時，復包括在對應該第一銲墊設置區域、第二銲墊設置區域、該 晶片安裝區域之該下表面及該凹部底面與靠近該晶片安裝區域的側表面上形成金屬層。 The method for manufacturing a quad flat no-pin package according to claim 1, wherein when the first pad and the second pad are formed, the first pad is disposed corresponding to the second pad Pad setting area, the A metal layer is formed on the lower surface of the wafer mounting region and the bottom surface of the recess and the side surface adjacent to the wafer mounting region. 如申請專利範圍第1項所述之四方扁平無接腳封裝件之製法，其中，該凹部係呈圍繞狀。 The method for manufacturing a quad flat no-pin package according to claim 1, wherein the recess is surrounded. 如申請專利範圍第1項所述之四方扁平無接腳封裝件之製法，其中，形成該第一銲墊和該第二銲墊之材質係為鎳(Ni)、鈀(Pd)或金(Au)。 The method for manufacturing a quad flat no-pin package according to claim 1, wherein the first pad and the second pad are made of nickel (Ni), palladium (Pd) or gold ( Au). 如申請專利範圍第1項所述之四方扁平無接腳封裝件之製法，其中，該凹部係從該第一銲墊設置區域靠近該間隙的外緣延伸至該晶片安裝區域靠近該第一銲墊設置區域的外緣。 The method of manufacturing the quad flat no-pin package according to claim 1, wherein the recess extends from the first pad mounting region adjacent to an outer edge of the gap to the wafer mounting region adjacent to the first solder The outer edge of the pad setting area. 如申請專利範圍第1項所述之四方扁平無接腳封裝件之製法，其中，形成該開口之方式係使用蝕刻、雷射或刀具切割。 A method of fabricating a quad flat no-pin package as described in claim 1, wherein the opening is formed by etching, laser or cutter cutting. 一種四方扁平無接腳封裝件，係包括：基材，係具有上表面及下表面，且該上表面係具有晶片安裝區域、圍繞該晶片安裝區域的第一銲墊設置區域、及圍繞該第一銲墊設置區域的第二銲墊設置區域，且該第一銲墊設置區域與該第二銲墊設置區域之間係具有間隙；複數第一銲墊及複數第二銲墊，係分別形成在該第一銲墊設置區域及該第二銲墊設置區域中；凹部，係形成在該下表面對應該第一銲墊設置區域靠近該間隙之外緣，另該凹部並未貫通該基材； 晶片，係設置在該晶片安裝區域中；複數銲線，係將該晶片分別電性連接到該第一銲墊及該第二銲墊；封裝膠體，係形成於該基材之上表面上，以包覆該晶片、該銲線、及該第一銲墊和該第二銲墊，且填入該凹部中；以及開口，係對應該間隙貫穿該上表面與下表面，且該開口係外露該凹部中的封裝膠體之側表面。 A quad flat no-pin package includes: a substrate having an upper surface and a lower surface, the upper surface having a wafer mounting region, a first pad mounting region surrounding the wafer mounting region, and surrounding the a second pad setting area of the pad mounting area, and a gap between the first pad setting area and the second pad setting area; the plurality of first pads and the plurality of second pads are respectively formed In the first pad setting area and the second pad setting area; the recess is formed in the lower surface facing the first pad setting area close to the outer edge of the gap, and the recess does not penetrate the substrate ; a wafer is disposed in the wafer mounting region; the plurality of bonding wires are electrically connected to the first bonding pad and the second bonding pad respectively; and the encapsulant is formed on the upper surface of the substrate, Coating the wafer, the bonding wire, and the first bonding pad and the second bonding pad, and filling the concave portion; and the opening, the gap corresponding to the upper surface and the lower surface, and the opening is exposed The side surface of the encapsulant in the recess. 如申請專利範圍第7項所述之四方扁平無接腳封裝件，復包括金屬層，係形成在對應該第一銲墊設置區域、第二銲墊設置區域、該晶片安裝區域之該下表面及該凹部底面與靠近該晶片安裝區域的側表面上。 The quad flat no-pin package according to claim 7, further comprising a metal layer formed on the first pad corresponding region, the second pad disposed region, and the lower surface of the wafer mounting region And a bottom surface of the recess and a side surface adjacent to the wafer mounting region. 如申請專利範圍第7項所述之四方扁平無接腳封裝件，其中，該凹部係呈圍繞狀。 The quad flat no-pin package of claim 7, wherein the recess is rounded. 如申請專利範圍第7項所述之四方扁平無接腳封裝件，其中，形成該第一銲墊和該第二銲墊之材質係為鎳(Ni)、鈀(Pd)或金(Au)。 The quad flat no-pin package according to claim 7, wherein the first pad and the second pad are made of nickel (Ni), palladium (Pd) or gold (Au). . 如申請專利範圍第7項所述之四方扁平無接腳封裝件，其中，該凹部係從該第一銲墊設置區域靠近該間隙的外緣延伸至該晶片安裝區域靠近該第一銲墊設置區域的外緣。 The quad flat no-pin package of claim 7, wherein the recess extends from the first pad mounting region adjacent the outer edge of the gap to the wafer mounting region adjacent to the first pad The outer edge of the area.
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