TW201442581A - Printed circuit board and method for manufacturing same - Google Patents

Abstract

The present invention relates to a method for manufacturing a printed circuit board. The method includes steps below. A substrate is provided. At least one through hole is formed in a waste area of the substrate. The through hole includes a first oblique wall. A second plated copper layer and a forth plated copper layer are formed on two opposite sides of the product area of the substrate. A third plated copper layer is formed on the first oblique wall. The third plated copper layer connects between the second plated copper layer and the forth plated copper layer. A first edge area conductive layer, a second edge area conductive layer and a third edge area conductive layer are formed by etching process. The first edge area conductive layer is corresponded with the second plated copper layer. The second edge area conductive layer is corresponded with the forth plated copper layer. The third edge area conductive layer is corresponded with the third plated copper layer. Then the product area is separated from the substrate to form a print circuit board. The wall of the print circuit board includes the first oblique wall. A printed circuit board manufacturing by the above method is also provided in the present disclosure.

Description

Circuit board and manufacturing method thereof

The present invention relates to the field of circuit boards, and in particular, to a circuit board and a method of fabricating the same.

The circuit board generally includes a product part and a waste part, and the product part is an area having a circuit function, and the waste part is a part that needs to be removed after the circuit board is hit. The product part includes a first surface and a second surface opposite to each other, that is, upper and lower surfaces. Generally, the exposed surface of the first surface and the second surface of the product portion does not have a bare copper surface, that is, the first surface of the product portion and the edge of the second surface are covered with an insulating layer. With the diversified needs of mobile consumer electronics products, the first surface of the product part and the edge of the second surface have exposed copper surfaces in the circuit board design, and such designs require a circuit board. A side copper surface is also formed on the side of the product portion connecting the first surface and the second surface, and the side copper surface connects the exposed surface of the first surface of the product portion and the exposed surface of the second surface. When manufacturing a circuit board of such a design, it is necessary to perform electroplating on the side of the product part to form the side copper surface. The current manufacturing method is as follows: first, the circuit board is firstly punched, so that The product portion is partially separated from the scrap portion to expose the side of the product portion to be plated, and then, the side to be plated of the product portion and the portion to be plated on the edge of the first surface and the second surface are plated. Finally, the product department is separated from the waste department by the second fishing type. However, in this method, when the circuit board is subjected to the second fishing type, the plating position of the product part is liable to cause defects such as drawing and burrs of copper, which may affect the solder yield.

In view of the above, it is necessary to provide a circuit board and a manufacturing method thereof to reduce defects such as brushed wire and burrs of copper in the plating position of the product part of the circuit board.

A method for manufacturing a circuit board, comprising the steps of: providing a circuit substrate, wherein the circuit substrate comprises a first conductive layer and a second conductive layer respectively located on outermost sides of the circuit substrate; the circuit substrate comprises a product part and a waste part Defining a boundary between the waste portion and the product portion as a boundary line; the product portion includes at least one first plate edge to be plated region and at least one second plate edge to be plated region, the at least one first plate edge The to-be-plated area is located in the first conductive layer, and the at least one second board side to be plated area is located in the second conductive layer, the first board side to be plated area and the second board side to be plated area Positioning one by one; forming at least one through hole in the waste portion of the circuit substrate, the through hole having a first sidewall, the first sidewall being inclined with respect to the circuit substrate; and the first conductive layer Forming a second copper plating layer on a plate to be plated, forming a fourth copper plating layer on the second plate side of the second conductive layer, and forming a connection between the first side wall and the intermediate portion Two copper plating layers and a third copper plating layer of the fourth copper plating layer; etching and controlling the etching time to remove the first conductive layer and the second conductive layer of the circuit substrate where the copper plating layer is not formed, thereby Forming a first plate edge conductive region at a position corresponding to the plated region, forming a second plate edge conductive region at a position corresponding to the second plate edge to be plated region, and forming a third plate on the first sidewall of the through hole An edge conducting region, wherein the third board edge conductive region is respectively connected to the first board edge conductive region and the second board edge conductive region; and separating the product portion from the scrap portion to thereby The portion is formed to form a circuit board, wherein a sidewall of the circuit board includes the first sidewall.

A circuit board comprising a third conductive circuit layer and a fourth conductive circuit layer respectively located on two sides of the circuit board, the third conductive circuit layer comprising a first conductive pattern and a first board edge conductive region, The fourth conductive circuit layer includes a second conductive pattern and a second board edge conductive region, the circuit board further has a first sidewall, the first sidewall is inclined with respect to the circuit board, and the first sidewall is formed with the The third board edge conductive region, the third board edge conductive region, the first board edge conductive region and the second board edge conductive region are connected.

The circuit board manufacturing method provided by the technical solution forms a trapezoidal through hole on the circuit substrate, the through hole has a sloped first side surface, and a third board edge conductive area is formed on the first side surface. And forming a first board edge conductive region and a second board edge conductive region connected to the third board edge conductive region, and then separating the product portion from the scrap portion, and retaining the first part when separating One side wall, and thus, when the through hole is formed, the edge of the product portion is not plated with copper, so that the phenomenon of drawing and burrs of copper does not occur, and although the copper is plated when the waste portion is separated, the product is in the position of the through hole. The portion has been separated from the scrap portion by the through hole, so that the separated portion is not required to be cut, that is, the separated scrap portion does not contact the conductive region on the first side wall, and therefore does not appear. Brushed and burrs of copper.

10. . . Circuit substrate

101. . . First conductive layer

102. . . First insulating layer

103. . . First conductive circuit layer

104. . . Second insulating layer

105. . . Second conductive circuit layer

106. . . Third insulating layer

107. . . Second conductive layer

110. . . Product department

120. . . Waste department

121. . . Junction line

1011. . . First plate side to be plated area

1071. . . Second board side to be plated area

1012. . . First side

1013. . . Second side

131. . . Through hole

1311. . . First opening

1312. . . Second opening

1315. . . First side wall

1316. . . Second side wall

1317. . . Third side wall

1318. . . Fourth side wall

1313. . . First bottom

1314. . . Second bottom

141. . . First copper layer

142. . . Second copper layer

143. . . Third copper layer

144. . . Fifth copper layer

151. . . Photoresist layer

161. . . First copper exposed area

162. . . Second copper exposed area

163. . . Third copper exposed area

164. . . Fourth copper exposed area

165. . . Fifth copper exposed area

171. . . First copper plating

172. . . Second copper plating

173. . . Third copper plating

174. . . Fourth copper plating

175. . . Fifth copper plating

108. . . Third conductive circuit layer

1081. . . First conductive pattern

1082. . . First board edge conductive area

109. . . Fourth conductive circuit layer

1091. . . Second conductive pattern

1092. . . Second board edge conductive area

1093. . . Third plate edge conductive zone

20. . . Circuit board

2011. . . Fifth side wall

2012. . . Sixth side wall

2013. . . Seventh side wall

2014. . . Eighth side wall

2015. . . Ninth side wall

2016. . . Tenth side wall

1 is a top plan view of a circuit substrate provided by an embodiment of the present technical solution.

2 is a schematic cross-sectional view of a circuit substrate provided by an embodiment of the present technical solution.

FIG. 3 is a top plan view showing a through hole formed on the circuit substrate of FIG. 1 according to an embodiment of the present invention.

4 is a schematic cross-sectional view showing a through hole formed on the circuit substrate of FIG. 2 according to an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing a copper-clad layer formed on the circuit substrate of FIG. 4 according to an embodiment of the present technical solution.

FIG. 6 is a schematic cross-sectional view showing a photoresist layer formed on the circuit substrate of FIG. 5 according to an embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing a patterned photoresist layer formed on the circuit substrate of FIG. 6 after the partial copper layer is exposed by the embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view showing a copper plating layer formed on the circuit substrate of FIG. 7 according to an embodiment of the present technical solution.

FIG. 9 is a schematic cross-sectional view showing the photoresist layer on the circuit substrate of FIG. 8 after the embodiment of the present invention is removed.

FIG. 10 is a cross-sectional view showing the etching on the circuit substrate of FIG. 9 provided by the embodiment of the present technical solution.

11 is a top plan view of a circuit board provided by the present technical solution.

FIG. 12 is a schematic cross-sectional view of a circuit board provided by the technical solution.

The circuit board provided by the technical solution and the manufacturing method thereof will be further described in detail below with reference to the accompanying drawings and embodiments.

The manufacturing method of the circuit board provided by the embodiment of the technical solution includes the following steps:

In the first step, referring to FIG. 1-2, a circuit substrate 10 is provided.

The circuit substrate 10 may be a two-layer circuit substrate or a multilayer circuit substrate. In the present embodiment, a four-layer circuit substrate 10 will be described as an example.

The circuit substrate 10 includes a first conductive layer 101, a first insulating layer 102, a first conductive wiring layer 103, a second insulating layer 104, a second conductive wiring layer 105, a third insulating layer 106, and a second layer which are sequentially laminated. Conductive layer 107. The first conductive layer 101 and the second conductive layer 107 are respectively located on the outermost sides of the circuit substrate 10 and are copper foil layers on which the conductive lines are not formed. The first conductive layer 101 and the second conductive layer 107 have substantially the same thickness.

The circuit board 10 is substantially rectangular and includes a product portion 110 and a waste portion 120. The waste portion 120 surrounds the product portion 110. The boundary between the scrap portion 120 and the product portion 110 is defined as a boundary line 121.

The product portion 110 includes at least one first plate edge to be plated region 1011 and at least one second plate edge to be plated region 1071. The at least one first board edge to be plated region 1011 is located on the first conductive layer 101, and the at least one second board edge to be plated region 1071 is located on the second conductive layer 107, the first board edge to be plated The region 1011 corresponds to the position of the second plate edge to be plated region 1071, and the first plate edge to be plated region 1011 and the corresponding second plate edge to be plated region 1071 have substantially the same shape. In this embodiment, the number of the first plate edge to be plated region 1011 and the second plate edge to be plated is one; the first plate edge to be plated region 1011 and the second plate edge to be plated The area 1071 is rectangular. The first plate edge to be plated region 1011 is adjacent to the boundary line 121 and has a first side 1012 that coincides with the boundary line 121. The second plate edge to be plated region 1071 is adjacent to the boundary line 121 and slightly Exceeding the boundary line 121, having a second side 1013 on the scrap portion 120 parallel to the boundary line 121.

Of course, in this step, the product portion 110 and the waste portion 120 of the circuit substrate 10 are not separated, so the boundary line 121 is a virtual line. In addition, the circuit board 10 is not limited to the shape in the embodiment; the product part 110 and the waste part 120 are not limited to the shape in the embodiment; the first board edge to be plated area 1011 and the The second plate edge to be plated region 1071 is also not limited to the shape in this embodiment. Moreover, the circuit substrate 10 has at least one conductive hole or communication hole (not shown), and the conductive hole or the communication hole functions to electrically connect or electrically connect the respective conductive layers and the conductive circuit layer in a subsequent step.

In the second step, referring to FIG. 3-4, at least one trapezoidal through hole 131 is formed in the scrap portion 120 of the circuit substrate 10.

The number of the through holes 131 is the same as the number of the first plate side to be plated regions 1011. In this embodiment, the number of the through holes 131 is one.

The through hole 131 is formed in the scrap portion 120 and is located on one side of the first plate side to be plated region 1011. The through hole 131 has a first opening 1311 formed on the first conductive layer 101 side and a second opening 1312 formed on the second conductive layer 107 side. The first opening 1311 is opposite to the second opening 1312 and is rectangular. The sides of the first opening 1311 are parallel to the sides of the second opening 1312. The dimensions of the length and width of the first opening 1311 are correspondingly larger than the length and width of the second opening 1312. The through hole 131 has a first side wall 1315, a second side wall 1316, a third side wall 1317 and a fourth side wall 1318 which are all connected in a trapezoidal shape. The first sidewall 1315 has a first bottom edge 1313 and a second bottom edge 1314. The first bottom edge 1313 of the first sidewall 1315 is a long side of the first opening 1311, and the second The bottom edge 1314 is a long side of the second opening 1312, wherein the first bottom edge 1313 coincides with the first edge 1012, and the second bottom edge 1314 coincides with the second edge 1013. . The length of the first side 1012 is defined as L1, the length of the second side 1013 is defined as L2, the length of the first bottom edge 1313 is defined as L3, and the length of the second bottom edge 1314 is defined as L4. Then L3>L4>L1, and L3>L4>L2. In the present embodiment, L1=L2. Because the size of the first opening 1311 is larger than the size of the second opening 1312, the first sidewall 1315, the second sidewall 1316, the third sidewall 1317, and the fourth sidewall 1318 are all trapezoidal and are opposite to each other. The central axis of the through hole 131 is inclined, that is, both are inclined with respect to the plane on which the circuit board 10 is placed.

The manner of forming the through hole 131 is preferably a milling cutter. The selected tool is a tool that is inclined by less than 90 degrees with the product to be formed to form a through hole 131 each having a trapezoidal shape. Of course, the through holes 131 may be formed in other ways, such as laser cutting or the like.

In addition, the through hole 131 may also be a through hole having three side walls or a through hole having more than four side walls. In this case, only one side wall needs to be inclined with respect to the central axis of the through hole 131, and the side wall is A bottom edge may coincide with the first side 1012 and a length greater than the first side 1012; or may be a truncated-shaped through hole or the like.

In the third step, referring to FIG. 5, the first conductive layer 101, the second conductive layer 107, the first sidewall 1315, the second sidewall 1316, the third sidewall 1317, and the fourth sidewall 1318 are formed on the surface of the circuit substrate 10, respectively. The first copper layer 141, the second copper layer 142, the third copper layer 143, the fourth copper layer (not shown), the fifth copper layer 144, and the sixth copper layer (not shown).

Forming the first copper layer 141, the second copper layer 142, the third copper layer 143, the fourth copper layer, the fifth copper layer 144, and the sixth copper layer may be electroless copper plating or Sputtered copper, etc. Since the through hole 131 penetrates the first conductive layer 101 and the second conductive layer 107, the first conductive layer 101 and the second conductive layer 107 are electrically connected to each other after the sidewall is filled with copper. Because of the simultaneous plating, the thickness of each of the copper-clad layers is substantially the same.

In the fourth step, referring to FIG. 6, a liquid photoresist is applied to the circuit substrate 10 and the liquid photoresist is cured to form a photoresist layer 151.

Specifically, a photoresist is formed on the surfaces of the first copper sink layer 141, the second copper sink layer 142, the third copper sink layer 143, the fourth copper sink layer, the fifth copper sink layer 144, and the sixth copper sink layer, respectively. Layer 151.

Preferably, the liquid photoresist is immersed, that is, the photoresist layer is formed by immersing the circuit substrate 10 in a liquid photoresist. The reason why the immersion liquid photoresist is selected is that the ordinary dry film photoresist can only cover both sides of the circuit board, and cannot completely cover the respective side walls of the through hole 131, and the immersed liquid photoresist can flow and can pass through. The through holes 131 thus cover the photoresist on each of the side walls.

In the fifth step, referring to FIG. 7, the liquid photoresist is exposed and developed to form a patterned photoresist layer, thereby exposing a portion of the copper layer.

After exposing and developing the liquid photoresist to form a patterned photoresist layer, the copper layer of the portion not covered by the photoresist layer is exposed, and the exposed copper layer includes the first copper exposed region 161 and the second The copper exposed area 162, the third copper exposed area 163, the fourth copper exposed area 164, and the fifth copper exposed area 165. The first copper exposed region 161 is located on the first copper sink layer 141, and the first copper exposed region 161 has a pattern, and the pattern is patterned with an outer conductive layer of the circuit board formed in the subsequent step. the same. The second copper exposed region 162 is also located in the first copper-clad layer 141, which is the same as the position, shape and size of the first plate edge to be plated region 1011 of the product portion 110. The third copper exposed region 163 is located in the third copper sink layer 143, and is connected to the second copper exposed region 162. The third copper exposed region 163 is also rectangular and the second The copper exposed area 162 is co-edge. The fourth copper exposed region 164 is located at the second copper sink layer 142, which is the same as the position, shape and size of the second plate edge to be plated region 1071 of the product portion 110, and the third The copper exposed regions 163 are connected and co-edge. The fifth copper exposed region 165 is also located on the second copper sink layer 142, and the fifth copper exposed region 165 also has a pattern, and the pattern is electrically conductive with the other outer layer of the circuit board formed in the subsequent step. The pattern of the circuit layers is the same.

The forming of the first copper exposed region 161 and the fifth copper exposed region 165 serves to form the conductive layer pattern by forming the first conductive layer 101 and the second conductive layer 107 in a subsequent step. Simultaneously forming the first copper exposure region 161, the second copper exposure region 162, the third copper exposure region 163, the fourth copper exposure region 164, and the fifth copper exposure region 165 can save board manufacturing costs. Of course, the first copper exposed region 161 and the fifth copper exposed region 165 may not be formed in this step, and the first conductive layer may be separately subjected to dry film, exposure, development, and etching in a subsequent step. The layer 101 and the second conductive layer 107 are formed to form a conductive line pattern.

In the sixth step, referring to Figure 8, electroplating is performed to form a copper plating layer on the copper layer exposed from the patterned photoresist layer.

Specifically, a first copper plating layer 171 is formed on the first copper exposed region 161, and a second copper plating layer 172 is formed on the second copper exposed region 162 in the third copper exposed region. A third copper plating layer 173 is formed on the 163, a fourth copper plating layer 174 is formed on the fourth copper exposed region 164, and a fifth copper plating layer 175 is formed on the fifth copper exposed region 165. Since the plating is performed at the same time, the thickness of each of the copper plating layers is substantially the same. The sum of the thicknesses of the first conductive layer 101 and the copper-clad layer is smaller than the thickness of the copper-plated layer; preferably, the thickness of the copper-plated layer is smaller than the thickness of the photoresist layer.

Of course, the first copper plating layer 171 having the same shape and shape as the conductive line pattern to be formed may be formed on the first conductive layer 101 by selective sputtering or the like without forming the copper layer. The second conductive layer 107 forms a fifth copper plating layer 175 having the same shape as the conductive circuit pattern to be formed, and a second copper plating layer 172 is formed on the first plate side of the first conductive layer 101 to be plated, and the second conductive layer is formed on the first conductive layer 101. The second plate side of the layer 107 is to be plated to form a fourth copper plating layer 174, and the third side of the first side wall 1315 is formed with a third plating plate connecting the second copper plating layer 172 and the fourth copper plating layer 174. Copper layer 173.

In a seventh step, referring to FIG. 9, the photoresist layer is removed to expose the copper layer covered by the photoresist layer.

The circuit board 10 after removing the photoresist layer has a copper surface on both sides, but the thickness of the copper surface is not the same at this time. The copper layer corresponding to the first copper exposed region 161 includes a first conductive layer 101, a first copper sink layer 141, and a first copper plating layer 171. The copper layer corresponding to the location of the second copper exposed region 162 includes a first conductive layer 101, a first copper sink layer 141, and a second copper plating layer 172. The copper layer corresponding to the location of the third copper exposed region 163 includes a third copper layer 143 and a third copper plating layer 173. The copper layer corresponding to the location of the fourth copper exposed region 164 includes a second conductive layer 107, a second copper sink layer 142, and a fourth copper plating layer 174. The copper layer corresponding to the location of the fifth copper exposed region 165 includes a second conductive layer 107, a second copper sink layer 142, and a fifth copper plating layer 175. The other positions of the first side wall 1315, the second side wall 1316, the third side wall 1317 and the fourth side wall 1318 form a third copper sink layer 143, a fourth copper sink layer, and a fifth sink, respectively. Copper layer 144 and sixth copper layer. The first conductive layer 101 side of the circuit substrate 10 includes a first conductive layer 101 and a first copper sink layer 141 except for the first copper exposed region 161 and the second copper exposed region 162. The second conductive layer 107 side of the circuit substrate 10 includes a second conductive layer 107 and a second copper sink layer 142 except for the fourth copper exposed region 164 and the fifth copper exposed region 165. That is, the copper layer of the first copper exposed region 161, the second copper exposed region 162, the third copper exposed region 163, the fourth copper exposed region 164, and the fifth copper exposed region 165 is located at a position other than the other copper layer. The location is thick.

In the eighth step, referring to FIG. 10, the etching time is etched and controlled so that the first copper exposed region 161, the second copper exposed region 162, the third copper exposed region 163, and the fourth copper exposed region 164 are to be etched. And removing the copper layer in the region other than the fifth copper exposed region 165, and the first copper exposed region 161, the second copper exposed region 162, the third copper exposed region 163, the fourth copper exposed region 164, and the first The copper layer at the location of the 165 copper exposed area is thinned.

Therefore, a third conductive circuit layer 108 is formed on the first insulating layer 102 side, and the third conductive circuit layer 108 includes a first conductive portion corresponding to the position of the first copper exposed region 161 of the product portion 110. a first plate edge conductive region 1082 corresponding to the position of the first plate edge to be plated region 1011 of the product portion 110, and a fourth conductive circuit layer 109 formed on the third insulating layer 106 side. The fourth conductive circuit layer 109 includes a second conductive pattern 1091 corresponding to the position of the fifth copper exposed region 165 of the product portion 110 and a position corresponding to the position of the product portion 110 to be plated to be plated 1071. a second board edge conductive region 1092; a third board edge conductive region 1093 formed on the first sidewall 1315 of the through hole 131, the third board edge conductive region 1093, the first board edge conductive region 1082 and the second The board edge conductive regions 1092 are all rectangular, and the third board edge conductive regions 1093 are respectively connected to the first board edge conductive region 1082 and the second board edge conductive region 1092 and are adjacent to each other.

In the ninth step, referring to FIG. 11-12, the product portion 110 is separated from the scrap portion 120 to form the product portion to form the circuit board 20.

The direction of the specific fishing type is as shown by the arrow in FIG. 11 , and travels toward the product portion 110 along one end of the second bottom edge 1314 of the first sidewall 1315 to the first bottom edge 1313 of the first sidewall 1315 . One end, that is, the direction indicated by the arrow A, thereby forming the fifth side wall 2011 of the circuit board 20, the fifth side wall 2011 is triangular and the circuit board 20 is vertical; then travels along the boundary line 121 to the The other end of the first bottom side 1313 of the first side wall 1315, that is, the direction indicated by arrows B and C, thereby forming the sixth side wall 2012 and the seventh side wall 2013 of the circuit board 20, the sixth side wall 2012 and the The seven side walls 2013 are all square and are perpendicular to the circuit board 20, and the sixth side wall 2012 and the seventh side wall 2013 are also perpendicular to the fifth side wall 2011; until then, the boundary line 121 is advanced to the The other end of the first bottom side 1313 of the first side wall 1315, that is, the direction indicated by the arrows D and E, thereby forming the eighth side wall 2014 and the ninth side wall 2015 of the circuit board 20, the eighth side wall 2014 and the ninth side wall 2015 is square and is perpendicular to the circuit board 20, and the eighth sidewall 201 4 and the ninth side wall 2015 are also obtusely angled with the fifth side wall 2011; finally, the other end of the first bottom side 1313 of the first side wall 1315 travels to the second bottom side 1314 of the first side wall 1315. One end, that is, the direction indicated by the arrow F, thereby forming the tenth side wall 2016 of the circuit board 20, the tenth side wall 2016 is also triangular and the circuit board 20 is perpendicular, the tenth side wall 2016 is also The eighth side wall 2014 and the ninth side wall 2015 are obtuse angles; since the product portion 110 at the position of the through hole 131 is separated from the scrap portion 120, there is no need to follow the fishing type, that is, the circuit board 20 The first side wall 1315 of the through hole 131 is retained. The seventh sidewall 2013, the sixth sidewall 2012, the fifth sidewall 2011, the first sidewall 1315, the tenth sidewall 2016, the ninth sidewall 2015, and the eighth sidewall 2014 are sequentially connected.

The method of separating the waste portion 120 may be a punching, fishing, or laser cutting. This embodiment is a fishing type.

The circuit board 20 includes a third conductive circuit layer 108, a first insulating layer 102, a first conductive circuit layer 103, a second insulating layer 104, a second conductive circuit layer 105, a third insulating layer 106, and a plurality of layers. Four conductive circuit layers 109. The third conductive circuit layer 108 includes a first conductive pattern 1081 in the board and a first board edge conductive region 1082 in the board edge. The fourth conductive circuit layer 109 includes a second conductive pattern 1091 in the board and a second board edge conductive region 1092 in the board edge. The circuit board further includes a sixth side wall 2012, a fifth side wall 2011, a first side wall 1315, an eighth side wall 2014, and the seventh side wall 2013 which are sequentially connected. The fifth sidewall 2011 and the eighth sidewall 2014 are triangular and the circuit board 20 is perpendicular. The sixth side wall 2012 and the seventh side wall 2013 are both square and are perpendicular to the circuit board 20. The first sidewall 1315 is trapezoidal, and the first sidewall 1315 is inclined with respect to the circuit board 20. The first sidewall 1315 includes a first bottom edge 1313 and a second bottom edge 1314. The first sidewall 1315 is formed with the third board edge conductive region 1093. The third board edge conductive region 1093 is formed. The first board edge conductive region 1082 and the second board edge conductive region 1092 are both rectangular, and the third board edge conductive region 1093 and the first board edge conductive region 1082 and the second board edge conductive region 1092 are respectively Connected and shared. Defining the length of the side of the third board edge conductive region 1093 shared with the first board edge conductive region 1082 and the second board edge conductive region 1092 is L1, and defining the length of the first bottom edge 1313 to be L3. The length of the second bottom edge 1314 is defined as L4, then L3>L4>L1.

The circuit board 20 can be a flexible circuit board, a rigid circuit board, or a rigid-flex circuit board.

In addition, before the product portion 110 is separated from the waste portion 120, steps such as solder resist, gold plating, and the like may be included.

The circuit board provided by the technical solution and the manufacturing method thereof, a trapezoidal through hole 131 is formed on the circuit substrate 10, so that the through hole 131 has an inclined first side wall 1315, and is further developed by liquid photoresist and exposure. And forming a third board edge conductive region 1093 on the first sidewall 1315, and forming a first board edge conductive region 1082 connected to the third board edge conductive region 1093 on the board edge of the circuit substrate 10 and The second board edge conductive region 1092, and then the product portion 110 is separated from the waste portion 120, and the first sidewall 1315 of the through hole 131 is retained when separated, that is, the circuit substrate 10 is formed during the first molding. There is no copper plating on the edge of the product part 110, so there is no phenomenon such as drawing and burrs of copper. Although the second molding is performed by electroplating copper, the product part 110 due to the position of the through hole 131 has been associated with the scrap. The portion 120 is phase separated, so that the separated portion is not further cut, that is, the second molding does not contact the third board edge conductive region 1093 on the first sidewall and the third panel edge conductive region 1093. Connected first board edge guide The region 1082 and the second board edge conductive region 1092, so that the phenomenon of drawing and burrs of copper does not occur; and the circuit of the outer layer of the circuit board follows the third board edge conductive region 1093, the first board edge conductive region 1082 and The second board edge conductive regions 1092 are formed together, and the processes of electroless copper plating, copper plating, dry film exposure and development etching required for the circuit are not separately required, thereby saving the manufacturing cost of the circuit board.

However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.

20. . . Circuit board

102. . . First insulating layer

106. . . Third insulating layer

110. . . Product department

1315. . . First side wall

108. . . Third conductive circuit layer

1081. . . First conductive pattern

1082. . . First board edge conductive area

109. . . Fourth conductive circuit layer

1091. . . Second conductive pattern

1092. . . Second board edge conductive area

1093. . . Third plate edge conductive zone

Claims (10)

A method for manufacturing a circuit board, comprising the steps of:
Providing a circuit substrate including a first conductive layer and a second conductive layer on outermost sides of the circuit substrate; the circuit substrate includes a product part and a waste part, and the waste part and the product are defined a junction of the portion is a boundary line; the product portion includes at least one first plate edge to be plated region and at least one second plate edge to be plated region, wherein the at least one first plate edge to be plated region is located in the first conductive layer The at least one second board edge to be plated area is located in the second conductive layer, and the first board edge to be plated area and the second board side to be plated area corresponding to each other;
Forming at least one through hole in the waste portion of the circuit substrate, the through hole having a first sidewall, the first sidewall being inclined with respect to the circuit substrate;
Forming a second copper plating layer on the first plate side of the first conductive layer to be plated, forming a fourth copper plating layer on the second plate side of the second conductive layer to be plated, and the first Forming a third copper plating layer connecting the second copper plating layer and the fourth copper plating layer on the sidewall;
Etching and controlling the etching time to remove the first conductive layer and the second conductive layer of the circuit substrate where the copper plating layer is not formed, thereby forming the first board edge conductive at a position corresponding to the first board edge to be plated region a second board edge conductive region is formed at a position corresponding to the second board edge to be plated region, and a third board edge conductive region is formed on the first sidewall of the through hole, and the third board edge conductive region is respectively Connecting the first board edge conductive region and the second board edge conductive region; and separating the product portion from the scrap portion to form the product portion to form a circuit board, the side wall of the circuit board including The first side wall. The method of manufacturing the circuit board of claim 1, wherein the first board edge to be plated region has a first side that coincides with the boundary line, and the second board edge to be plated area has a a second side of the waste portion and parallel to the boundary line, the first side wall has a first bottom edge and a second bottom edge, and the first bottom edge coincides with the first side, The second bottom edge coincides with the second side, defining a length of the first side as L1, defining a length of the second side as L2, and defining a length of the first bottom side as L3, defining The length of the second bottom side is L4, then L3>L4>L1, and L3>L4>L2. The method of manufacturing the circuit board of claim 1, wherein a second copper plating layer is formed on the first plate side of the first conductive layer to be plated, and a second plate is formed on the second conductive layer. Forming a fourth copper plating layer adjacent to the plating region, and forming a third copper plating layer connecting the second copper plating layer and the fourth copper plating layer in an intermediate portion of the first sidewall comprises the steps of:
Forming a first copper layer, a second copper layer, and a third copper layer on the first conductive layer, the second conductive layer, and the first sidewall surface of the circuit substrate;
Forming a patterned photoresist layer on the first copper sink layer, the second sink copper layer, and the third sink copper layer, wherein the copper sink layer not covered by the photoresist layer includes a second copper exposed region a third copper exposed area and a fourth copper exposed area; the second copper exposed area is located in the first copper sinking layer, the second copper exposed area and the first part of the product part The position, shape and size of the plate to be plated are the same; the fourth copper exposed area is located in the second copper layer, and the fourth copper exposed area and the second side of the product part are The electroplating zone has the same position, shape and size; the third copper exposed zone is located at the third copper sinking layer and the second copper exposed zone is respectively opposite to the second copper exposed zone and the fourth sinking Copper exposed areas are connected;
Forming a second copper plating layer on the exposed portion of the first copper sink, forming a fourth copper plating layer on the exposed portion of the fourth copper sink, and plating forming the connection in the exposed portion of the third copper sink a second copper plating layer and a third copper plating layer of the fourth copper plating layer; and removing the photoresist layer. The method of manufacturing the circuit board of claim 1, wherein the first conductive layer and the second conductive layer of the circuit substrate where the copper plating layer region is not formed is removed, and the first board is further removed The first conductive layer and the second copper plating layer to be electroplated are integrally thinned, and the second conductive layer and the fourth copper plating layer of the second plate to be plated are integrally thinned, and the first sidewall is The third copper plating layer in the middle area is thinned. The method of manufacturing the circuit board of claim 1, wherein a second copper plating layer is formed on the first plate side of the first conductive layer to be plated, and a second plate is formed on the second conductive layer. Forming a fourth copper plating layer on the side to be plated, and forming a third copper plating layer connecting the second copper plating layer and the fourth copper plating layer on the intermediate portion of the first sidewall; a conductive layer forms a first copper plating layer, and a second copper plating layer is formed on the second conductive layer, and etching time is controlled to control the first conductive layer and the second conductive region of the circuit substrate where the copper plating layer region is not formed. At the same time as the layer is removed, a first conductive line pattern is formed in a region corresponding to the first copper plating layer, and a second conductive line pattern is formed in a region corresponding to the fifth copper plating layer. The method of manufacturing the circuit board of claim 5, wherein the first conductive layer and the second conductive layer of the circuit substrate where the copper plating layer region is not formed is removed, and the first plating is further performed The copper layer and the corresponding first conductive layer are integrally thinned, and the fifth copper plating layer and the corresponding second conductive layer are integrally thinned to be in a region corresponding to the first copper plating layer. Forming a first conductive line pattern, and forming a second conductive line pattern in a region corresponding to the fifth copper plating layer. The manufacturing method of the circuit board of claim 1, wherein the through hole has a first opening and a second opening, the first opening is formed on the first conductive layer side, and the second opening Formed on the second conductive layer side, the first opening is opposite to the second opening and the size of the first opening is larger than the size of the second opening. The method of manufacturing the circuit board according to Item 1, wherein the through hole is formed by milling, and the cutter is formed by using a tool having a tilt of less than 90 degrees with the product to be molded. A circuit board comprising a third conductive circuit layer and a fourth conductive circuit layer respectively located on two sides of the circuit board, the third conductive circuit layer comprising a first conductive pattern and a first board edge conductive region, The fourth conductive circuit layer includes a second conductive pattern and a second board edge conductive region, the circuit board further has a first sidewall, the first sidewall is inclined with respect to the circuit board, and the first sidewall is formed with the The third board edge conductive region, the third board edge conductive region, the first board edge conductive region and the second board edge conductive region are connected. The circuit board of claim 9, wherein the first sidewall comprises an opposite first bottom edge and a second bottom edge, and the third board edge conductive region and the first board edge conductive region are defined The common side is a first side, the first side is coincident with the first bottom edge, the length of the first side is defined as L1, and the length of the first bottom side is defined as L3, and the second is defined. The length of the bottom edge is L4, then L3>L4>L1.