TW201436185A - Solid-state image sensing device, manufacturing method, and electronic device - Google Patents

Abstract

This disclosure relates to a solid-state image sensing device, a manufacturing method and an electronic device wherein the degradation of image quality caused by occurrence of white points can be suppressed by use of a simpler structure. A pixel comprises: a photoelectric conversion part that performs a photoelectric conversion to generate a charge a floating diffusion part that converts the charge generated by the photoelectric conversion part to a signal a transfer transistor that transfers the charge from the photoelectric conversion part to the floating diffusion part and a side wall that is formed on a side surface of a gate electrode constituting the transfer transistor, said side surface facing the floating diffusion part. A gap region, which is a predetermined interval, equal to or greater than the width of the side wall, between the gate electrode constituting the transfer transistor and the floating diffusion part, is formed. This technique can be applied to, for example, a back-illuminated CMOS sensor.

Description

Solid-state imaging device, method of manufacturing the same, and electronic device

The present disclosure relates to a solid-state imaging device, a manufacturing method, and an electronic device, and more particularly to a solid-state imaging device, a manufacturing method, and an electronic device which are capable of suppressing deterioration of image quality due to generation of white spots with a simpler structure.

Conventionally, in an electronic device having an imaging function such as a digital still camera or a digital video camera, for example, a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor) image sensor is used. Solid-state imaging element.

In general, a solid-state imaging device includes a pixel array portion in which a plurality of pixels are arranged in an array, and a peripheral circuit that performs control processing for driving each pixel of the pixel array portion and Signal processing of signals output by respective pixels of the pixel array section.

The pixel has a PD (Photodiode) which generates a charge corresponding to the amount of light received by photoelectric conversion, and an FD (Floating Diffusion) portion for use in the photodiode The generated charge is converted into a pixel signal. Further, a transfer transistor that is responsible for the transfer of the charge generated in the photodiode to the FD portion is disposed between the PD and the FD portion. The pixel is designed in such a manner that a voltage of, for example, -1 V is applied to the gate electrode of the transfer transistor during storage of the charge in the PD, whereby the charge does not freely flow from the PD to the FD portion.

In addition, since the FD portion is always applied with substantially the same voltage as the pixel power source, When a voltage of -1 V or less is applied to the gate electrode of the transfer transistor, the voltage difference between the gate electrode and the FD portion of the transfer transistor becomes large, thereby generating a strong electric field. Such a strong electric field affects the pixel signal output from the pixel, for example, it appears as a white point in an image constructed by the pixel signal, and thus the image quality deteriorates.

Therefore, as a countermeasure for suppressing generation of a strong electric field, for example, after forming a gate electrode of a transfer transistor, a sidewall is formed on a side surface thereof, whereby an end portion of the gate electrode of the transfer transistor and the FD portion are formed. An offset corresponding to the sidewall is set between. By this offset, the electric field generated at the end of the gate electrode of the transfer transistor can be lowered, and the strong electric field can be alleviated.

On the other hand, in the camera market in recent years, in order to determine the subject even in the dark, the demand for solid-state imaging devices having excellent S/N (Signal/Noise) performance has increased, for example, in surveillance cameras. Demands such as industrial cameras or business cameras for radio stations are particularly high. In order to develop a solid-state imaging device that can image with higher image quality in a dark place, in recent years, there has been a tendency to increase the signal amount of a pixel signal output from a pixel by setting a pixel power supply to a high voltage. Designed to achieve high S/N.

However, it is conceivable that since the power supply voltage is designed to be a high voltage (for example, 2.7 V or more), when the transfer transistor is turned off, the voltage difference between the gate electrode and the FD portion of the transfer transistor may become too high. Therefore, even if a side wall is formed, a strong electric field is generated at the end portion of the gate electrode of the transfer transistor, and it is difficult to suppress the generation of white spots.

Further, for example, Patent Document 1 discloses a technique in which a gate electrode of a transfer transistor has a tapered portion at a boundary portion between a transfer transistor and an FD portion, thereby mitigating a gate of a transfer transistor. The electric field between the pole electrode and the FD portion.

However, in the technique disclosed in Patent Document 1, in order to form the tapered portion, the gate electrode of the transfer transistor must be dug into the lower portion by several 10 nm or more. Therefore, there is a weakening ability to cope with the process deviation and a dark current is deteriorated, or the interface under the gate electrode of the transmitting transistor is transmitted. The situation in which the energy level is increased. Further, not only the characteristic deterioration such as white point deterioration due to such a situation is feared, but also the cost increases due to an increase in the number of steps.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2008-227263

As described above, the conventional solid-state imaging device has a situation in which a white point is generated in an image due to a strong electric field generated between the gate electrode and the FD portion of the transfer transistor, resulting in deterioration of image quality. Further, in the technique disclosed in Patent Document 1, it is conceivable that since the gate electrode of the transfer transistor has a tapered portion at the lower portion, it is difficult to match the process conditions, and the number of steps is increased, thereby causing an increase in cost. .

The present disclosure has been made in view of such a situation, and it is possible to suppress deterioration of image quality due to generation of white spots with a simpler structure.

A solid-state imaging device according to an aspect of the present disclosure includes: a photoelectric conversion portion that performs photoelectric conversion to generate a charge; a floating diffusion portion that converts a charge generated by the photoelectric conversion portion into a signal; and a transfer portion that charges a charge from the photoelectric The conversion portion is transferred to the floating diffusion portion; and the side wall is formed on a side surface of the floating diffusion portion side of the electrode constituting the transmission portion; and the side wall is formed between the electrode constituting the transmission portion and the floating diffusion portion A gap area of a particular interval above the width.

A manufacturing method according to an aspect of the present disclosure is a method of manufacturing a solid-state imaging device, comprising: a photoelectric conversion portion that performs photoelectric conversion to generate a charge; and a floating diffusion portion that converts a charge generated by the photoelectric conversion portion into a signal; a transfer portion that transfers charges from the photoelectric conversion portion to the floating diffusion portion; and a sidewall formed on a side of the floating diffusion portion of the electrode constituting the transfer portion; and the manufacturing method includes The step of forming the floating diffusion portion so as to provide a gap region at a specific interval between the electrode constituting the transfer portion and the floating diffusion portion.

An electronic apparatus according to an aspect of the present disclosure includes a solid-state imaging element including: a photoelectric conversion portion that performs photoelectric conversion to generate a charge; and a floating diffusion portion that converts a charge generated by the photoelectric conversion portion into a signal; a portion for transferring electric charge from the photoelectric conversion portion to the floating diffusion portion, and a side wall formed on a side surface of the floating diffusion portion of the electrode constituting the transfer portion; and the electrode constituting the transfer portion to the floating diffusion A gap region which is a specific interval equal to or larger than the width of the side wall is formed between the portions.

In one aspect of the present disclosure, a gap region provided with a specific interval is formed between a gate electrode constituting a transfer transistor and a floating diffusion portion.

According to an aspect of the present disclosure, it is possible to more easily suppress deterioration of image quality caused by generation of white spots.

11‧‧‧ pixels

12‧‧‧PD

13‧‧‧Transfer transistor

14‧‧‧FD Department

15‧‧‧Amplifying the transistor

16‧‧‧Selecting a crystal

17‧‧‧Reset the transistor

21‧‧‧矽 substrate

22‧‧‧gate electrode

23‧‧‧ side wall

24‧‧‧Narrow N-type area

31‧‧‧ pixels

31A‧‧ ‧ pixels

31B‧‧ ‧ pixels

31C‧‧ ‧ pixels

31D‧‧ ‧ pixels

32‧‧‧PD

33‧‧‧Transfer transistor

34‧‧‧FD Department

35‧‧‧Amplifying the transistor

36‧‧‧Selecting a crystal

37‧‧‧Reset the transistor

38‧‧‧Gap area

41‧‧‧矽 substrate

42‧‧‧gate electrode

43‧‧‧ side wall

44‧‧‧Narrow N-type area

45‧‧‧N-type area

45a‧‧‧N-type area

51‧‧‧Additional N-type area

51a‧‧‧Additional N-type area

51b‧‧‧Additional N-type area

61‧‧‧Sidewall

62‧‧‧Gate electrode

101‧‧‧ Solid-state imaging components

102‧‧‧Pixel Array Department

103‧‧‧Vertical drive department

104‧‧‧Processing Department

105‧‧‧ horizontal drive department

106‧‧‧Output Department

107‧‧‧Drive Control Department

201‧‧‧ camera device

202‧‧‧Optical system

203‧‧‧Photographic components

204‧‧‧Signal Processing Circuit

205‧‧‧ monitor

206‧‧‧ memory

D‧‧‧Distance

VDD‧‧ ‧ pixel power supply

VSL‧‧‧ vertical signal line

1A-C are diagrams showing a prior pixel configuration.

Fig. 2 is a view showing a method of manufacturing a prior pixel.

Fig. 3 is a diagram showing the relationship between the number of white dots and the pixel power supply.

4A and 4B are views showing a configuration example of a first embodiment in which a pixel of the present technology is applied.

Fig. 5 is a graph showing the relationship between the electric field strength and the distance between the potential barrier and the gap region.

6A to 6C are views showing a configuration example of a second embodiment of a pixel.

7A to 7C are views showing a configuration example of the third to fifth embodiments of the pixel.

Fig. 8 is a view for explaining the first manufacturing method.

Fig. 9 is a view for explaining the second manufacturing method.

10A and B are views showing other manufacturing methods.

Fig. 11 is a block diagram showing a configuration example of an embodiment of a solid-state imaging device.

FIG. 12 is a block diagram showing a configuration example of an image pickup apparatus mounted in an electronic device.

Hereinafter, a specific embodiment in which the present technology is applied will be described in detail with reference to the drawings.

First, a conventional solid-state image sensor will be described with reference to Figs. 1 to 3 .

A schematic configuration of a pixel is shown in A of FIG. 1, and a circuit diagram equivalent to the pixel shown in FIG. 1A is shown in FIG. 1B, and a cross-sectional structure of the pixel is shown in FIG.

As shown in FIG. 1A and FIG. 1B, the pixel 11 is composed of a PD 12, a transfer transistor 13, an FD portion 14, an amplifying transistor 15, a selection transistor 16, and a reset transistor 17. In the pixel 11, the charge generated in the PD 12 by photoelectric conversion is transferred to the FD portion 14 via the transfer transistor 13, and converted into a pixel signal by amplifying the transistor 15, and then output via the selection transistor 16. To the vertical signal line VSL.

Further, as shown in FIG. 1C, the pixel 11 is formed on the germanium substrate 21, and the gate electrode 22 of the transfer transistor 13 is formed on the surface of the germanium substrate 21 via an insulating film (not shown). A side wall 23 is formed on a side surface of the electrode 22 on the FD portion 14 side. Further, the FD portion 14 is composed of a thicker N-type region 24 formed by injecting an N-type impurity into the germanium substrate 21.

As described above, the pixel 11 is designed in such a manner that a voltage of, for example, -1 V is applied to the gate electrode 22 of the transfer transistor 13 during storage of the charge in the PD 12, whereby the charge is not freely from the PD 12 It flows out to the FD unit 14. Since the FD portion 14 is always applied with a voltage substantially the same as the pixel power source VDD, the gate electrode 22 and the FD portion of the transfer transistor 13 are caused by applying a voltage of -1 V or less to the gate electrode 22 of the transfer transistor 13. The voltage difference between 14 becomes large, thereby generating a strong electric field.

If such a strong electric field is generated, there is a fear that current leakage occurs in the portion indicated by the × mark in C of FIG. Thereby, the pixel signal output from the pixel 11 is affected to appear as a white point in the image, thereby causing deterioration in image quality.

A method of manufacturing the pixel 11 will be described with reference to Fig. 2 .

First, the PD 12 and the gate electrode 22 of the transfer transistor 13 are formed. Thereafter, the side wall 23 is formed on the side of the gate electrode 22 on the opposite side to which the PD 12 is formed. Then, the sidewalls 23 are self-aligned to inject N-type impurities to form a thicker N-type region 24, whereby the FD portion 14 is formed. By doing so, the end portion of the gate electrode 22 of the transfer transistor 13 and the FD portion 14 are shifted corresponding to the region where the sidewall 23 is to be formed, so that the electric field generated at the end portion of the gate electrode 22 of the transfer transistor 13 is lowered. .

However, as described above, when the power supply voltage is designed to be a high voltage (for example, 2.7 V or more), a strong electric field is generated even in the configuration in which the sidewall 23 is formed with an offset, resulting in generation in an image. White dot. Such a number of white spots (hereinafter referred to as FD white spots as appropriate) due to a strong electric field has characteristics depending on the voltage of the pixel power source.

The relationship between the voltage of the pixel power source and the number of FD white points is shown in FIG.

In FIG. 3, the horizontal axis represents the voltage of the pixel power supply, and the vertical axis represents the value obtained by normalizing the number of FD white dots by the number of pixel power supplies of 2.5V. FIG. 3 shows a case where the number of FD white points increases as the voltage of the pixel power source is increased.

Further, as described above, the technique disclosed in Patent Document 1 has a structure in which the gate electrode of the transfer transistor has a tapered portion at the lower portion, and thus it is difficult to match the process conditions.

Therefore, the industry has a simple structure that is easy to match the process conditions, and it is possible to suppress the pixel structure of the FD white point even if the pixel power supply is designed to be 2.7 V or more.

In this regard, specific embodiments in which the present technology is applied will be described below.

Fig. 4 is a view showing a configuration example of a first embodiment of a pixel to which the present technique is applied. A plan view of a pixel is shown in A of FIG. 4, and a cross-sectional structure of a pixel is shown in FIG.

As shown in FIG. 4, the pixel 31 includes a PD 32, a transfer transistor 33, an FD unit 34, an amplifying transistor 35, a selection transistor 36, and a reset transistor 37. Further, in the pixel 31, a gap region 38 is provided between the transfer transistor 33 and the FD portion 34.

The PD 32 is photoelectrically converted by light, generates a charge corresponding to the amount of light thereof, and is stored. The transfer transistor 33 transfers the charge generated by the PD 32 to the FD portion 34, which temporarily stores the charge and converts the charge into a signal. The amplification transistor 35 amplifies the charge stored in the FD portion 34, and outputs a signal corresponding to the level of the charge to the vertical signal line via the selection transistor 36. The reset transistor 37 discharges the charge stored in the FD portion 34 to the pixel power source VDD to be reset.

Further, as shown in FIG. 4B, the pixel 31 is formed on the germanium substrate 41, and the gate electrode 42 of the transfer transistor 33 is formed on the surface of the germanium substrate 41 via an insulating film (not shown). Further, a side wall 43 is formed on the side surface of the gate electrode 42 of the transfer transistor 33 on the FD portion 34 side.

The FD portion 34 is composed of a thick N-type region 44 formed by ion-implanting an N-type impurity to the germanium substrate 41, and an N-type region 45 is formed at a portion deeper than the thicker N-type region 44. The N-type region 45 is used to transfer charge from the PD 32 to the transfer transistor 33.

Further, in the pixel 31, a thick region N constituting the FD portion 34 is formed by providing a distance D from the end portion of the gate electrode 42 of the transfer transistor 33, and a gap region 38 is provided. The distance D in the gap region 38 is set to a specific interval of at least the width of the side wall 43, for example, 100 nm. Further, the order of formation of the gate electrode 42, formation of the side wall 43, and formation of the FD portion 34 is not limited, and may be formed in any order.

Thus, in the pixel 31, by providing the gap region 38 of the distance D so as to be wider than the width of the side wall 43, a strong electric field can be suppressed from being generated between the gate electrode 42 and the FD portion 34 of the transfer transistor 33. . In particular, by setting the distance D in the gap region 38 to 100 nm or more, the FD white point due to the strong electric field can hardly occur.

Therefore, in the pixel 31, even if the pixel power source is set to a high voltage (for example, 2.7 V or more), the FD white point can be avoided, so that when a high S/N solid-state image sensor is developed, the selection range of the pixel power source can be expanded. .

Further, if the gate electrode 42 of the transfer transistor 33 is widened between the FD portion 34, then It is feared that transmission deterioration occurs when charges are transferred from the gate electrode 42 of the transmission transistor 33 to the FD portion 14 due to the potential barrier therebetween.

The relationship between the electric field intensity generated at the end of the gate electrode 42 of the transfer transistor 33 and the distance D between the potential barrier and the gap region 38 between the PD 32 and the FD portion 34 is shown in FIG.

The horizontal axis of Fig. 5 indicates the distance D of the gap region 38, the vertical axis on the left side indicates the electric field intensity generated at the end portion of the gate electrode 42 of the transfer transistor 33, and the vertical axis on the right side indicates the relationship between the PD 32 and the FD portion 34. Potential barrier.

As shown in FIG. 5, when the distance D of the gap region 38, that is, the distance D from the end of the gate electrode 42 of the transfer transistor 33 to the FD portion 14 is 100 nm or more, the gate electrode 42 of the transistor 33 is transferred. The electric field strength at the end is reduced. Then, if the distance D of the gap region 38 is further increased, the electric field intensity of the end portion of the gate electrode 42 of the transmission transistor 33 gradually converges.

On the other hand, as shown in FIG. 5, when the distance D of the gap region 38 is 200 nm or more, a potential barrier is generated between the PD 32 and the FD portion 34, and transmission deterioration occurs. This transmission degradation affects the pixel signal output from the pixel, for example, appears as a black dot in the image constructed by the pixel signal, resulting in deterioration of image quality.

Therefore, charge transfer of the gate electrode 42 to the FD portion 14 of the transfer transistor 33 can be improved, for example, by additionally forming an N-type region due to the gap region 38.

In other words, Fig. 6 is a view showing a configuration example of the second embodiment of the pixel 31.

In the pixel 31A shown in FIG. 6, the same components as those of the pixel 31 of FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. In other words, the pixel 31A is considered to be different from the pixel 31 in that an additional N-type region 51 is formed in the vicinity of the surface of the ruthenium substrate 41 from the gap region 38 and the FD portion 34.

The additional N-type region 51 is formed by, for example, injecting a concentration lower than the N-type impurity concentration injected into the FD portion 34 by a concentration of two or more digits in a region having a depth of about 0.1 μm from the surface of the ruthenium substrate 41. N type impurity. Additional N-type region by forming such impurity concentration In the field 51, the additional N-type region 51 functions as a transfer assisting unit that assists the transfer of charges from the transfer transistor 33 to the FD unit 34. Further, the step of implanting the N-type impurity to form the N-type impurity is to form the side wall 43, and then the end portion of the side wall 43 and the end portion of the additional N-type region 51 are aligned.

Therefore, as shown in FIG. 6B, by providing the additional N-type region 51, the transfer gradient in the gap region 38 is enhanced. The shape of the potential with respect to the X direction of the pixel 31A (the direction along the cross section of A of Fig. 6) is shown in Fig. 6B.

Further, the distribution of the N-type impurities in the FD portion 34 and the additional N-type region 51 is shown in C of FIG. In C of Fig. 6, the horizontal axis represents the depth from the surface of the ruthenium substrate 41, and the vertical axis represents the concentration of the N-type impurity. As described above, the concentration of the N-type impurity implanted into the additional N-type region 51 is lower than the N-type impurity concentration injected into the FD portion 34 by two or more digits, and the N-type region 51 is formed near the surface of the ruthenium substrate 41. The concentration of impurities becomes the highest. Charge transfer via the additional N-type region 51 is performed at a depth at which the concentration of the N-type impurity becomes the highest.

In this manner, the transfer gradient is enhanced by the addition of the N-type region 51 from the transfer transistor 33 to the potential of the FD portion 34, and then further enhanced by the thicker N-type region 44 of the FD portion 34. Thus, by forming the potential distribution of the stage structure, it is possible to efficiently transfer the charge to the FD portion 34.

Therefore, the pixel 31A is the same as the pixel 31, and even if the pixel voltage is set to a high voltage of 2.7 V or higher, the generation of the FD white point can be suppressed, and the charge transfer from the transfer transistor 33 to the FD portion 34 can be favorably performed. . Further, the process conditions for manufacturing the pixel 31A can be designed in such a manner that the suppression of the FD white point and the improvement of the charge transfer can be simultaneously achieved. Thereby, the pixel 31A can avoid the generation of the FD white point and the black point, thereby further improving the image quality.

Next, Fig. 7 is a view showing a configuration example of the third to fifth embodiments of the pixel 31. In the pixels 31B to 31D shown in FIG. 7, the same components as those of the pixel 31A of FIG. 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

A pixel 31B of the third embodiment is shown in A of Fig. 7 . Pixel 31B is considered as with Figure 6 The pixel 31A is different in configuration in that the end portion of the additional N-type region 51a coincides with the end portion of the gate electrode 42 of the transfer transistor 33. That is, in the pixel 31B, the N-type impurity is implanted by self-alignment of the gate electrode 42 after the gate electrode 42 of the transfer transistor 33 is formed and before the sidewall 43 is formed, thereby forming the additional N-type region 51a. By forming the additional N-type region 51a in this manner, the pixel 31B can further improve the charge transfer efficiency as compared with the pixel 31A.

The pixel 31C of the fourth embodiment is shown in Fig. 7B. The pixel 31C is considered to be different from the pixel 31A of FIG. 6 in that it is formed in such a manner that the end portion of the additional N-type region 51b is more toward the gate electrode 42 of the transfer transistor 33 than the end portion of the side wall 43. The side protrudes and is closer to the FD portion 34 side than the end portion of the gate electrode 42 of the transfer transistor 33. That is, in the pixel 31C, after the gate electrode 42 of the transfer transistor 33 is formed and before the sidewall 43 is formed, a space is formed between the end portion of the gate electrode 42 of the transfer transistor 33 and injected with a mask. The N-type impurity forms an additional N-type region 51b. By appropriately adjusting the interval between the end portion of the additional N-type region 51b and the end portion of the gate electrode 42 of the transfer transistor 33, the balance between the electric field intensity and the transfer efficiency can be adjusted, and the optimum characteristics can be obtained. Adjust the interval.

The pixel 31D of the fifth embodiment is shown in Fig. 7C. The pixel 31D is different from the pixel 31A of FIG. 6 in that an N-type region 45a for transferring charges from the PD 32 to the FD portion 34 is formed to the periphery of the transfer transistor 33. In other words, the pixel 31D is configured such that the N-type region 45a is not connected to the FD portion 34. Further, although the additional N-type region 51 is formed in the pixel 31D in the same manner as the pixel 31A, the additional N-type region 51a may be formed as the pixel 31B or the additional N-type region 51b may be formed as the pixel 31C. The structure of the additional N-type region 51 is not formed as in the pixel 31.

A first manufacturing method of the pixel 31 will be described with reference to Fig. 8 .

First, in the first step, after the gate electrode 42 of the transfer transistor 33 is formed on the surface of the germanium substrate 41, the side surface 43 is formed from the side of the gate electrode 42 across the distance D. Side wall material 61. The distance D is set to 100 nm or more as described above, for example.

Then, in the second step, the side wall member 61 is self-aligned to inject a relatively concentrated N-type impurity to form a thicker N-type region 44, whereby the FD portion 34 is formed.

Then, in the third step, the side wall member 61 is etched to form the side wall 43, whereby the gap region 38 of the distance D is provided.

By the above steps, the pixel 31 in which the gap region 38 of the distance D is provided between the end portion of the gate electrode 42 of the transfer transistor 33 and the FD portion 34 can be manufactured. Further, in this manufacturing method, the step of reducing the amount of the pixel 31 can be reduced by injecting the N-type impurity so as to share the side wall member 61 with the other mask.

A second manufacturing method of the pixel 31 will be described with reference to Fig. 9 .

First, in the first step, the gate electrode material 62 serving as the gate electrode 42 of the transfer transistor 33 is formed on the surface of the germanium substrate 41. The gate electrode material 62 is formed so as to extend along the distance D from the side where the end portion of the gate electrode 42 is formed to the side where the FD portion 34 is formed. The distance D is set to 100 nm or more as described above, for example.

Then, in the second step, the gate electrode material 62 is self-aligned to inject a relatively concentrated N-type impurity to form a thick N-type region 44, whereby the FD portion 34 is formed.

Then, in the third step, the gate electrode material 62 is etched to form the gate electrode 42 so that the end portion of the gate electrode 42 is formed from the position where the FD portion 34 is separated from the distance D, thereby forming the gate electrode 42. The gap region 38 of D. Thereafter, the side wall 43 is formed.

By the above steps, the pixel 31 in which the gap region 38 of the distance D is provided between the end portion of the gate electrode 42 of the transfer transistor 33 and the FD portion 34 can be manufactured. Further, in this manufacturing method, the step of reducing the size of the pixel 31 can be reduced by injecting the N-type impurity so as to share the gate electrode material 62 with the other mask.

Furthermore, although the method of manufacturing the pixel 31 of FIG. 4 has been described with reference to FIGS. 8 and 9, the same manufacturing method can be applied to the pixel 31A of FIG. 6 and the pixels 31B to 31D of FIG.

Further, in addition to injecting impurities by self-aligning the side wall member 61 or the gate electrode member 62, for example, the FD portion 34 may be formed by providing a gap region 38 of the distance D by shielding of the gate electrode 42 of the transfer transistor 33. .

Next, another manufacturing method of the pixel 31 will be described with reference to FIG.

For example, as shown in FIG. 10A, after the gate electrode 42 of the transfer transistor 33 is formed, when the N-type impurity forming the FD portion 34 is implanted, the ruthenium substrate 41 is tilted with respect to the injection direction thereof. Thereby, the FD portion 34 can be formed by the shielding of the gate electrode 42 and the distance D from the gate electrode 42 correspondingly. Thereafter, the side wall 43 is formed.

Further, as shown in FIG. 10B, after the gate electrode 42 of the transfer transistor 33 is formed and the sidewall 43 is formed, when the N-type impurity forming the FD portion 34 is implanted, the 矽 substrate 41 is tilted with respect to the implantation direction thereof. . Thereby, the FD portion 34 can be formed by the shielding of the gate electrode 42 and the distance D from the gate electrode 42 correspondingly.

Furthermore, although the method of manufacturing the pixel 31 of FIG. 4 has been described with reference to FIG. 10, the same manufacturing method can be applied to the pixel 31A of FIG. 6 and the pixels 31B to 31D of FIG.

Next, a solid-state image sensor having the pixel 31 will be described.

As shown in FIG. 11, the solid-state imaging device 101 includes a pixel array unit 102, a vertical drive unit 103, a line processing unit 104, a horizontal drive unit 105, an output unit 106, and a drive control unit 107.

In the pixel array unit 102, the pixels 31 of the above various configuration examples are arranged in an array, and are connected to the vertical driving unit 103 via a plurality of horizontal signal lines corresponding to the number of columns of the pixels 31, and via the line corresponding to the pixels 31. A plurality of vertical signal lines are connected to the line processing unit 104. The vertical drive unit 103 sequentially supplies a drive signal for driving (transmitting, selecting, resetting, etc.) each of the plurality of pixels 31 of the pixel array unit 102 via a horizontal signal line.

The line processing unit 104 performs CDS (Correlated Double Sampling) processing on the pixel signals output from the respective pixels 32 via the vertical signal lines, thereby extracting images. The signal level of the prime signal is obtained, and pixel data corresponding to the amount of received light of the pixel 31 is obtained. The horizontal drive unit 105 sequentially supplies, to each of the plurality of pixels 31 included in the pixel array unit 102, a drive signal for outputting the pixel data obtained from each pixel 31 by the self-processing unit 104 to the line processing unit 104.

The self-processing unit 104 supplies the pixel data to the output unit 106 in accordance with the timing of the drive signal of the horizontal drive unit 105. The output unit 106 amplifies the pixel data, for example, and outputs the pixel data to the image processing circuit of the subsequent stage. The drive control unit 107 controls the driving of each block inside the solid-state image sensor 101. For example, the drive control unit 107 generates a clock signal that follows the drive period of each block and supplies it to each block.

Then, the solid-state imaging device 101 configured as described above can be applied to various electronic devices such as an imaging system such as a digital still camera or a digital video camera, a mobile phone having an imaging function, or another device having an imaging function.

FIG. 12 is a block diagram showing a configuration example of an image pickup apparatus mounted in an electronic device.

As shown in FIG. 12, the imaging device 201 includes an optical system 202, an imaging device 203, a signal processing circuit 204, a monitor 205, and a memory 206, and can capture still images and moving images.

The optical system 202 is configured by one or a plurality of lenses, and guides image light (incident light) from the subject to the imaging element 203, and forms an image on the light receiving surface (sensor portion) of the imaging element 203.

As the imaging element 203, the solid-state imaging element 101 having the pixels 31 of the above various configuration examples can be applied. In the imaging element 203, electrons are stored and fixed for a period of time based on an image formed on the light receiving surface via the optical system 202. Then, a signal corresponding to the electrons stored in the image pickup element 203 is supplied to the signal processing circuit 204.

The signal processing circuit 204 performs various signal processing on the pixel signals output from the image pickup element 203. The image (image material) obtained by performing signal processing by the signal processing circuit 204 is supplied to the monitor 205 for display, or is supplied to the memory 206 to be memorized (recorded).

In the imaging device 201 configured as described above, by applying the solid-state imaging device 101 having the pixel 31 having the above-described configuration, even if the pixel power source is set to a high voltage, it is possible to obtain a better image quality in which generation of white spots is suppressed. The image.

Further, the germanium substrate constituting the solid-state image sensor 101 may be any one of an Nsub substrate and a Psub substrate. Further, as the solid-state imaging device 101, any of a front side CMOS sensor, a back side illumination type CMOS sensor, and a CCD can be used.

Furthermore, the present technology can also adopt the following configuration.

(1)

A solid-state imaging device comprising: a photoelectric conversion portion that performs photoelectric conversion to generate electric charges; a floating diffusion portion that converts charges generated by the photoelectric conversion portion into a signal; and a transfer portion that transfers charges from the photoelectric conversion portion to The floating diffusion portion and the side wall are formed on a side surface of the floating diffusion portion of the electrode constituting the transmission portion, and are formed to be equal to or larger than a width of the side wall between the electrode constituting the transmission portion and the floating diffusion portion. The gap area for a specific interval.

(2)

The solid-state imaging device according to the above (1), wherein a transfer assisting portion that assists charge transfer from the transfer portion to the floating diffusion portion is provided in the gap region.

(3)

The solid-state imaging device according to the above aspect (1), wherein the transfer assisting portion is formed such that an end portion on the transfer portion side and a side surface on the floating diffusion portion side of an electrode constituting the transfer portion are formed The ends of the side walls are identical.

(4)

The solid-state imaging device according to the above (1) or (2), wherein the transfer assisting portion is formed such that an end portion on the transfer portion side coincides with an end portion of an electrode constituting the transfer portion.

(5)

The solid-state imaging device according to the above aspect (1), wherein the transfer assisting portion is formed such that an end portion on the transfer portion side is formed on a side of the floating diffusion portion side of an electrode constituting the transfer portion. The end portion of the side wall protrudes further toward the conveying portion side, and is closer to the floating diffusion portion side than the end portion of the electrode constituting the conveying portion.

In addition, this embodiment is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the invention.

31‧‧‧ pixels

32‧‧‧PD

33‧‧‧Transfer transistor

34‧‧‧FD Department

35‧‧‧Amplifying the transistor

36‧‧‧Selecting a crystal

37‧‧‧Reset the transistor

38‧‧‧Gap area

41‧‧‧矽 substrate

42‧‧‧gate electrode

43‧‧‧ side wall

44‧‧‧Narrow N-type area

45‧‧‧N-type area

D‧‧‧Distance

VDD‧‧ ‧ pixel power supply

Claims (7)

A solid-state imaging device comprising: a photoelectric conversion portion that performs photoelectric conversion to generate electric charges; a floating diffusion portion that converts charges generated by the photoelectric conversion portion into a signal; and a transfer portion that transfers charges from the photoelectric conversion portion to The floating diffusion portion and the side wall are formed on a side surface of the floating diffusion portion of the electrode constituting the transmission portion, and are formed to be equal to or larger than a width of the side wall between the electrode constituting the transmission portion and the floating diffusion portion. The gap area for a specific interval. The solid-state imaging device according to claim 1, wherein a transfer assisting portion that assists in charge transfer from the transfer portion to the floating diffusion portion is provided in the gap region. The solid-state imaging device according to claim 2, wherein the transfer assisting portion is formed such that an end portion on the transfer portion side coincides with an end portion of the side wall. The solid-state imaging device according to claim 2, wherein the transfer assisting portion is formed such that an end portion on the transfer portion side coincides with an end portion of an electrode constituting the transfer portion. The solid-state imaging device according to claim 2, wherein the transfer assisting portion is formed such that an end portion on the transfer portion side protrudes toward the transfer portion side from an end portion of the side wall, and is more constituting an electrode of the transfer portion The end portion is further on the side of the floating diffusion portion. A manufacturing method, which is a method of manufacturing a solid-state imaging element, the solid-state imaging element The device includes: a photoelectric conversion portion that performs photoelectric conversion to generate a charge; a floating diffusion portion that converts a charge generated by the photoelectric conversion portion into a signal; and a transfer portion that transfers charge from the photoelectric conversion portion to the floating diffusion portion; And a side wall formed on a side surface of the floating diffusion portion of the electrode constituting the transfer portion; and the manufacturing method includes the step of forming the floating diffusion portion in such a manner as to form an electrode of the transfer portion to the floating diffusion portion Between the gap areas that are set to a specific interval. An electronic apparatus comprising: a solid-state imaging element comprising: a photoelectric conversion portion that performs photoelectric conversion to generate electric charge; a floating diffusion portion that converts a charge generated by the photoelectric conversion portion into a signal; and a transfer portion that The electric charge is transferred from the photoelectric conversion unit to the floating diffusion unit; and the side wall is formed on a side surface of the electrode constituting the transfer unit on the side of the floating diffusion unit; and between the electrode constituting the transfer unit and the floating diffusion unit, A gap region which is a specific interval equal to or larger than the width of the side wall is formed.