JP2013059010A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device with a suppressed amount of leakage current occurring in a storage portion.SOLUTION: A solid-state imaging device includes a plurality of pixel portions disposed on a semiconductor substrate 70, a plurality of storage portions, and a vertical scanning circuit 6. In the semiconductor substrate 70, a first-conductivity-type well 61 is formed. Each of the plurality of storage portions has a writing transistor 31 formed in the well 61. The well 61 and a second-conductivity-type diffusion region 72 that is a source or a drain of the writing transistor 31 are bonded. The vertical scanning circuit 6 applies, to the well 61, a predetermined voltage for reducing the electric field intensity of the bonded portion between the well 61 and the diffusion region 72 during the storage period for storing pixel signals in the storage portions.

Description

  The present invention relates to a solid-state imaging device used for a digital camera or the like, and more particularly to image quality improvement of a MOS image sensor.

  A conventional CCD (Charge Coupled Device) image sensor shutter system is a global shutter system in which the signal charge of a photodiode is simultaneously transferred to a transfer region in all pixels and then sequentially read out. Therefore, the CCD image sensor can obtain images at the same time for all pixels.

  On the other hand, a shutter system of a MOS image sensor using a MOS (Metal Oxide Semiconductor) type transistor is a rolling shutter system that reads a signal from a photodiode by row scanning.

  In conventional MOS image sensors, a rolling shutter is generally used, and this is one of the main differences from a CCD image sensor based on a global shutter. In this rolling shutter type solid-state imaging device, the shooting time differs depending on the row of the screen. Therefore, since the time from the transfer of the pixel signal to the reading is different between the first row and the last row in the block, a phenomenon occurs in which the image is distorted when a moving object is photographed.

  To deal with such a problem, the solid-state imaging device disclosed in Patent Document 1 enables a global shutter operation by providing a memory unit.

  FIG. 6 is a block diagram of the solid-state imaging device of Patent Document 1. As illustrated in FIG. 6, the solid-state imaging device 200 includes a pixel cell 201 that converts an optical signal into an electric signal, a pixel unit 202 in which the pixel cells 201 are two-dimensionally arranged, and a vertical direction (row) of the pixel unit 202. A vertical scanning unit 203 that selects a pixel, a noise suppression unit 231 that suppresses noise of a pixel signal from a selected row, and a memory unit 222 that two-dimensionally arranges memory cells 221 that accumulate output signals of the noise suppression unit 231; , A memory vertical scanning unit 223 that selects the vertical direction (memory row) of the memory unit 222, a horizontal selection unit 205 that selects a signal of the selected memory row, and a horizontal that sequentially selects the horizontal selection unit 205 in the horizontal direction. The scanning unit 206 and an output amplifier 212 are included.

  FIG. 7 is a circuit diagram of the noise suppression unit 231, the memory unit 222, and the horizontal selection unit 205 included in the solid-state imaging device 200 illustrated in FIG. 6. The memory cell 221 includes a memory capacitor C31 that accumulates the output signal of the noise suppression unit 231, a memory write transistor M31 that writes to the memory capacitor C31, a memory amplifier A31 that amplifies the signal accumulated in the memory capacitor C31, It comprises a memory read transistor M32 for reading the output of the memory amplifier A31. Hereinafter, the memory unit is also referred to as a storage unit.

JP 2008-072188 A

  However, in the solid-state imaging device described in Patent Document 1, since the time for storing the signal charge in the storage unit is as long as several hundreds msec at the maximum, even a slight leak current generated in the storage unit cannot be ignored. , Noise will be mixed in the output.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a solid-state imaging device in which the amount of leakage current generated in a storage unit in the solid-state imaging device is suppressed.

  In order to achieve the above object, a solid-state imaging device according to one embodiment of the present invention includes a plurality of pixel portions that are arranged in a matrix on a semiconductor substrate and output pixel signals that are signals corresponding to the amount of incident light. A column signal line provided for each column of the pixel unit, a plurality of storage units provided for each column signal line for storing pixel signals transferred from the column signal line, and a voltage applying unit for applying a voltage A first conductivity type well is formed in the semiconductor substrate, each of the plurality of memory portions is formed in the well, and each of the plurality of pixel portions is connected to the column signal line via the column signal line. A second transistor having a first transistor for reading out the pixel signal and a storage capacitor for storing the pixel signal, the source or drain of the first transistor being different from the first conductivity type. The diffusion area of the mold Subsequently, the well and the diffusion region are joined, and the voltage application unit determines the electric field strength of the junction between the well and the diffusion region during a storage period for storing a pixel signal in the storage unit. A predetermined voltage to be reduced is applied to the well.

  That is, the solid-state imaging device includes a plurality of pixel units disposed on a semiconductor substrate, a plurality of storage units, and a voltage application unit. A first conductivity type well is formed in the semiconductor substrate. Each of the plurality of storage units includes a first transistor formed in the well. The well and the diffusion region of the second conductivity type that is the source or drain of the first transistor are joined. The voltage application unit applies a predetermined voltage to the well to reduce the electric field strength at the junction between the well and the diffusion region during a storage period for storing a pixel signal in the storage unit.

  Thereby, the electric field strength at the junction between the well and the diffusion region of the first transistor is reduced. As a result, it is possible to suppress the amount of leakage current generated in the storage unit including the first transistor.

  Preferably, the voltage application unit applies the predetermined voltage for applying a reverse bias to the junction between the well and the diffusion region during the storage period.

  Preferably, the voltage application unit applies a ground voltage or a power supply voltage to the well during a reading period for reading a pixel signal from the storage unit.

  Preferably, the plurality of storage units are divided into a plurality of blocks, the wells are electrically separated for each block, and the voltage application unit is separated into the separated wells corresponding to the blocks, One of the predetermined voltage, ground voltage and power supply voltage is applied according to the operation period of the block.

  Preferably, the plurality of storage units are arranged in a matrix, each of the divided blocks is set in units of rows of the plurality of storage units, and the solid-state imaging device includes rows of the plurality of storage units. A process of reading out pixel signals is performed in units.

  Preferably, a first insulating separation portion and a second insulating separation portion are formed in the semiconductor substrate, and each of the plurality of storage portions includes at least two transistors including the first transistor, Each of the at least two transistors is electrically isolated by the first insulation isolation unit, and the plurality of blocks correspond to a plurality of wells in which the well is electrically isolated by the second insulation isolation unit, respectively. In the semiconductor substrate, the lower end of the second insulating isolation part is deeper than the lower end of the first insulating isolation part, and the lower end of the second insulating isolation part is separated in the semiconductor substrate. Further, it is at a position deeper than the lower end of the well.

  According to the solid-state imaging device according to the present invention, it is possible to suppress the amount of leakage current generated in the storage unit.

It is a figure which shows schematic structure of the camera and solid-state imaging device which concern on embodiment of this invention. It is a circuit diagram which shows an example of the pixel structure in the solid-state imaging device concerning embodiment of this invention. It is a circuit diagram corresponding to a part of the inside of the memory circuit in the solid-state imaging device according to the embodiment of the present invention. 3 is a schematic cross-sectional view of a plurality of transistors included in a memory circuit. FIG. It is a timing chart which shows the time change of the main signal in the solid-state imaging device concerning an embodiment of the invention. It is a figure which shows schematic structure of the memory circuit in the solid-state imaging device concerning embodiment of this invention. It is a block diagram of the conventional solid-state imaging device. It is a circuit diagram of the noise suppression part, memory part, and horizontal selection part which are contained in the conventional solid-state imaging device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same components are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof may be omitted.

  It should be noted that the dimensions, materials, shapes, relative arrangements, and the like of the constituent elements exemplified in the embodiments are appropriately changed depending on the configuration of the apparatus to which the present invention is applied and various conditions. It is not limited to those examples. Moreover, the dimension of each component in each figure may differ from an actual dimension.

  The solid-state imaging device according to the present embodiment is arranged in a matrix on a semiconductor substrate, and is provided for each of a plurality of pixel units that output pixel signals that are signals corresponding to the amount of incident light, and for each column of the plurality of pixel units. A column signal line, a plurality of storage units that are provided for each of the column signal lines and that store pixel signals transferred from the column signal line, and a voltage application unit that applies a voltage. A well of a first conductivity type is formed, and each of the plurality of storage portions is formed in the well, and a first signal for reading out the pixel signal from each of the plurality of pixel portions via the column signal line. A diffusion region of a second conductivity type different from the first conductivity type, which is a source or drain of the first transistor, and has a storage capacity for storing the pixel signal; Connected, and the well and the expansion. The voltage application unit applies a predetermined voltage for reducing the electric field strength at the junction between the well and the diffusion region during a storage period for storing a pixel signal in the storage unit. Apply to.

  With such a configuration, it is possible to provide a solid-state imaging device in which the amount of leakage current generated in the memory unit in the solid-state imaging device is suppressed.

  Embodiments of the present invention will be described.

  FIG. 1 is a diagram illustrating a schematic configuration of an imaging device (camera) and a solid-state imaging device according to an embodiment of the present invention. In addition, the arrow in FIG. 1 shows the transmission direction of various signals.

  The camera 1000 in FIG. 1 includes a solid-state imaging device 400, a lens 410, a mechanical shutter 411, a DSP (digital signal processing circuit) 420, an image display device 430, and an image memory 440.

  The mechanical shutter 411 is a lens shutter or a focal plane shutter. When the mechanical shutter 411 is a focal plane shutter, the mechanical shutter 411 includes two curtains, a front curtain and a rear curtain. Moreover, the straight arrow in this figure shows the transmission direction of various signals.

  Light enters the camera 1000 from the outside through the lens 410. The incident light is converted into an output signal by the solid-state imaging device 400, and the output signal is output from the output interface 428 via the output line 4.

  The output signal thus output is processed by the DSP 420 and output as a video signal to the image memory 440, and the video signal is recorded in the image memory 440. Further, the video signal is output to the image display device 430, and an image is displayed on the image display device 430.

  The DSP 420 includes an image processing circuit 421 and a camera system control unit 422. The image processing circuit 421 generates a video signal by performing processing such as noise removal on the output signal of the solid-state imaging device 400.

  The camera system control unit 422 controls pixel scanning timing and gain in the solid-state imaging device 400. For example, the DSP 420 performs correction related to a characteristic difference between pixels shared within the pixels of the solid-state imaging device 400.

  A communication timing control unit (timing generator) 450 receives a master clock CLK0 and data DATA input via an external terminal, and generates various internal clocks. Then, the communication timing control unit 450 controls a horizontal scanning circuit 5, a vertical scanning circuit 6, a noise removal circuit 3, an output interface 428, and the like, which will be described later, using the generated internal clock.

  In the present embodiment, an analog / digital signal processing unit (AD conversion unit) may be provided between a storage circuit 2 and an output interface 428 described later.

  Further, as shown in FIG. 1, the solid-state imaging device 400 includes a pixel circuit 1, a storage circuit 2, a noise removal circuit 3, an output line 4, a horizontal scanning circuit 5, and a vertical scanning circuit 6. Here, the storage circuit 2 for storing signals is installed outside the pixel circuit 1, but the configuration is not limited to this. For example, the memory circuit 2 may be provided in the pixel circuit 1.

  The pixel circuit 1 outputs a reference signal and an output signal. The memory circuit 2 holds a reference signal and an output signal. The noise removal circuit 3 outputs the difference between the reference signal held in the storage circuit 2 and the output signal. This difference is output to the output line 4 in synchronization with the output of the horizontal scanning circuit 5. The vertical scanning circuit 6 applies a pulse (voltage) to the pixel circuit 1 and the storage circuit 2. That is, the vertical scanning circuit 6 is a voltage application unit that applies a voltage.

  FIG. 2 is a circuit diagram showing an example of a pixel configuration in the solid-state imaging device 400 according to the embodiment of the present invention.

  A portion surrounded by a broken line in FIG. 2 is a pixel portion 2a which is a pixel unit. A plurality of pixel portions 2a are arranged in a matrix on a semiconductor substrate 70 described later. Each pixel unit 2a outputs a pixel signal that is a signal corresponding to the amount of incident light.

  The pixel unit 2 a includes a photodiode 10, a transfer MOS transistor 11, a reset MOS transistor 12, and an output MOS transistor 13.

  In the pixel unit 2 a, the anode of the photodiode 10 is grounded, and the cathode is connected to the drain of the transfer MOS transistor 11. The source of the transfer MOS transistor 11 is connected to the source of the reset MOS transistor 12 and the gate of the output MOS transistor 13, and the gate is connected to the terminal 23. This region forms a diffusion capacitance called floating diffusion (hereinafter referred to as FD).

  The drain of the reset MOS transistor 12 is connected to the power supply, and the gate is connected to the terminal 22. The drain of the output MOS transistor 13 is connected to the power supply, and the source is connected to the drain of the row selection MOS transistor 14.

  The current source 20 is connected to the column signal line 21 (see FIGS. 1 and 2). The column signal line 21 is provided for each column of the plurality of pixel units 2a. In the row selection MOS transistor 14, the gate is connected to the terminal 24. When the row selection MOS transistor 14 is conductive, the output MOS transistor 13 and the current source 20 form a source follower.

  Next, the internal configuration of the memory circuit 2 will be described with reference to FIGS. 3A and 3B. The storage circuit 2 includes a plurality of storage units arranged in a matrix. The plurality of storage units include storage units 3a and 3b. That is, a plurality of storage units including the storage units 3a and 3b are arranged in a matrix. The storage units 3 a and 3 b are provided for each column signal line 21. The storage units 3a and 3b store pixel signals transferred from the column signal line 21.

  FIG. 3A is a circuit diagram corresponding to a part of the inside of the memory circuit 2 in the solid-state imaging device 400 according to the embodiment of the present invention. Specifically, FIG. 3A is a circuit diagram of the storage units 3a and 3b.

  FIG. 3B is a schematic cross-sectional view of a plurality of transistors included in the memory circuit 2.

  In FIG. 3A, the column signal line 21 is the column signal line 21 of FIG. The storage circuit 2 includes storage units 3 a and 3 b, a current source 35, and a read column signal line 34.

  The storage unit 3 a includes a write transistor 31, a read transistor 33, and a storage transistor 32. In addition, the storage unit 3 b includes a write transistor 36, a read transistor 38, and a storage transistor 37.

  The write transistors 31, 36, the read transistors 33, 38, and the storage transistors 32, 37 are n-type field effect transistors.

Each of the writing transistors 31 and 36 is a first transistor for reading out the pixel signal from each of the plurality of pixel portions 2 a via the column signal line 21.
Note that the write transistors 31 and 36, the read transistors 33 and 38, and the storage transistors 32 and 37 may be p-type field effect transistors.

  As shown in FIG. 3B, p-type wells 61 and 62 are formed in the semiconductor substrate 70. The conductivity type of the wells 61 and 62 may be n-type.

  In the wells 61 and 62, storage portions 3a and 3b are formed, respectively. That is, each storage unit is formed in a well. Further, well contacts 63 and 64 are formed on the semiconductor substrate 70. Contact plugs 63a and 64a are electrically connected to the well contacts 63 and 64, respectively.

  The well contact 63 is used for applying a voltage to the well 61 via the contact plug 63a. The well contact 64 is used to apply a voltage to the well 62 through the contact plug 64a.

  In the well 61, a write transistor 31, a storage transistor 32, and a read transistor 33 (not shown) are formed. In the well 62, a write transistor 36, a storage transistor 37, and a read transistor 38 (not shown) are formed.

  The write transistor 31 includes n-type diffusion regions 71 and 72 and a gate electrode 73. Each of the diffusion regions 71 and 72 is a source or a drain of the write transistor 31. When the conductivity type of the wells 61 and 62 is n-type, the conductivity type of the diffusion regions 71 and 72 may be p-type. Each of diffusion regions 71 and 72 and well 61 are joined.

  Note that the configuration of the write transistor 36 and the storage transistors 32 and 37 is the same as that of the write transistor 31. Hereinafter, the gate electrode 73 of the writing transistor 31 is also simply referred to as the gate of the writing transistor 31.

  Although details will be described later, each of the storage transistors 32 and 37 stores the pixel signal. The storage transistors 32 and 37 correspond to the storage capacity in the present invention. The source or drain of the write transistor 31 is connected to the gate of the storage transistor 32 as the storage capacitor. That is, the diffusion region of the second conductivity type (n-type) different from the first conductivity type, which is the source or drain of the write transistor 31, is connected to the storage capacitor.

  In the storage transistor 32, the read transistor 33 and the current source 35 form a source follower. In the storage transistor 37, the read transistor 38 and the current source 35 form a source follower.

  The gates of the write transistors 31 and 36 are connected to terminals 40 and 42, respectively. The gates of the read transistors 33 and 38 are connected to terminals 41 and 43, respectively.

  The well 61 corresponding to the write transistor 31 is electrically connected to the terminal 50 via the well contact 63 and the contact plug 63a. The well 62 corresponding to the write transistor 36 is electrically connected to the terminal 51 via the well contact 64 and the contact plug 64a.

  That is, in the storage unit 3 a, the well 61 corresponding to the read transistor 33 and the storage transistor 32 is electrically connected to the terminal 50. In the memory unit 3 b, the well 62 corresponding to the read transistor 38 and the memory transistor 37 is electrically connected to the terminal 51.

  As shown in FIG. 3B, a first insulation separation part 60 and a second insulation separation part 65 are formed in the semiconductor substrate 70. Details of the first insulation separation unit 60 and the second insulation separation unit 65 will be described later.

  Although details will be described later, each of the storage transistors 32 and 37 stores the pixel signal.

  Next, a signal output operation from the pixel circuit 1 to the memory circuit 2 will be described. Light incident on the pixel portion 2a is photoelectrically converted by the photodiode 10, and the charge generated by the conversion is accumulated in the photodiode 10 for a predetermined period. First, in order to read the reference signal, the reset MOS transistor is turned on and the FD is reset. The reference signal is transmitted to the column signal line 21 by turning on the row selection MOS transistor 14. A reference signal transmitted through the column signal line 21 is input to the memory circuit 2 in FIG.

  The write transistor 31 is turned on in a state where the reference signal is input from the column signal line 21 to the memory circuit 2. When the write transistor 31 is turned on, the reference signal of the column signal line 21 is guided to the gate of the storage transistor 32 and held in the gate capacitance of the storage transistor 32. When reading this reference signal, the read transistor 33 is turned on, and a signal corresponding to the reference signal accumulated in the gate capacitance of the storage transistor 32 is output from the read column signal line 34.

  Subsequently, after the reset operation, the transfer MOS transistor 11 is turned on to transfer the charge accumulated in the photodiode 10 to the FD. In the FD, the transferred charge is converted into a voltage signal, and the voltage signal is applied to the gate of the output MOS transistor 13. At this time, the output signal is transmitted to the column signal line 21 by turning on the row selection MOS transistor 14. The output signal is input to the memory circuit 2 in FIG. 1 via the column signal line 21.

  With the output signal being input from the column signal line 21 to the memory circuit 2, the write transistor 36 is turned on. When the write transistor 36 is turned on, the output signal of the column signal line 21 is guided to the gate of the storage transistor 37 and held in the gate capacitance of the storage transistor 37. When reading this output signal, the read transistor 38 is turned on, and a signal corresponding to the output signal accumulated in the gate capacitance of the memory transistor 37 is output from the read column signal line 34.

  The reference signal and the output signal output from the read column signal line 34 are output from the output line 4 after an arbitrary column is selected by the horizontal scanning circuit 5 and a difference calculation is performed by the noise removal circuit 3. Since the driving frequency of the horizontal scanning circuit 5 is limited and an output signal for all pixels cannot be instantaneously sent to the output line 4, the gate capacity of the storage transistor 37 is a signal for a period of several hundred msec at maximum. Need to accumulate.

  Hereinafter, the period for accumulating signals in the gate capacitance of the storage transistor is also referred to as an accumulation period or a storage period.

  If a leak current occurs in a node (source or drain) connected to the gate capacitance, for example, a node connected to the gate electrode of the storage transistor 37 within the storage period, the signal stored in the gate capacitance of the storage transistor 37 Therefore, it is necessary to suppress the leakage current at this node.

  FIG. 4 is a timing chart showing temporal changes of main signals in the solid-state imaging device 400 according to the embodiment of the present invention.

  FIG. 4 shows control signals applied from the vertical scanning circuit 6 to the terminals 22, 23, 24, 40, 41, 42, 43, 50, 51 in FIGS. 2 and 3A. The control signal is represented by a name with S added to the sign of the applied terminal. For example, a signal applied to the terminal 22 is represented as a signal S22.

  The signal S40 is a signal input to the gate of the write transistor 31 applied to the terminal 40. The signal S42 is a signal input to the gate of the write transistor 36 applied to the terminal 42. The signal S41 is a signal input to the gate of the read transistor 33 applied to the terminal 41. The signal S43 is a signal input to the gate of the read transistor 38 applied to the terminal 43.

  The signal S50 is a signal input to the well 61 corresponding to the write transistor 31 applied to the terminal 50. The signal S51 is a signal input to the well 62 corresponding to the write transistor 36 applied to the terminal 51.

  Next, the operation of the memory circuit 2 of the solid-state imaging device 400 according to the present embodiment will be described with reference to FIGS. 3A and 4. In the following description, the binary high voltage state and low voltage state of a signal or signal line are also referred to as “H level” and “L level”, respectively.

  The reference signal Vref is output from the pixel unit 2a to the column signal line 21 at time points t3 to t4 in FIG. At this time, when the signal S40 and the signal S41 are at the H level, the vertical scanning circuit 6 applies an H level pulse signal to the gates of the writing transistor 31 and the reading transistor 33 so that the writing transistor 31 and the reading transistor 33 are turned on. Conduct.

  When the write transistor 31 is turned on, the reference signal Vref of the column signal line 21 is guided to the gate of the storage transistor 32 and held in the gate capacitance of the storage transistor 32. At this time, since the read transistor 33 is also conductive, the source follower including the storage transistor 32, the read transistor 33, and the current source 35 also operates. Therefore, an output signal corresponding to the reference signal Vref accumulated in the gate capacitance of the storage transistor 32 is output to the read column signal line 34 at a time point t9 described later.

  Thus, when the write transistor 31 is turned on, the read transistor 33 is also turned on, so that the storage transistor 32 and the read transistor 33 operate as a source follower, that is, an amplifier, together with the current source 35. Therefore, the output signal corresponding to the electrical signal accumulated in the gate capacitance of the storage transistor 32 can be amplified and output to the read column signal line 34 efficiently.

  Further, when an electrical signal (pixel signal) is held in the storage unit 3a, the storage transistor 32 and the read transistor 33 are turned on in the same manner as when the electrical signal held in the storage unit 3a is read. That is, when the electrical signal (pixel signal) is held in the storage unit 3a, the state is the same as the state when the electrical signal held in the storage unit 3a is read out, so that the held signal value is accurately held. Can be read.

  From time t7 to t8, the output signal V1 is output from the pixel unit 2a to the column signal line 21. At this time, when the signal S42 and the signal S43 are at the H level, the vertical scanning circuit 6 applies an H level pulse signal to the gates of the writing transistor 36 and the reading transistor 38 so that the writing transistor 36 and the reading transistor 38 are turned on. Conduct.

  When the write transistor 36 is turned on, the output signal V 1 of the column signal line 21 is guided to the gate of the storage transistor 37 and held in the gate capacitance of the storage transistor 37. At this time, since the read transistor 38 is also conductive, the source follower including the storage transistor 37, the read transistor 38, and the current source 35 also operates. Therefore, a signal corresponding to the output signal V1 accumulated in the gate capacitance of the storage transistor 37 is output to the read column signal line 34 at a time point t10 described later.

  Thus, when the write transistor 36 is turned on, the read transistor 38 is also turned on, so that the storage transistor 37 and the read transistor 38 operate as a source follower, that is, an amplifier, together with the current source 35. Therefore, an output signal corresponding to the electric signal accumulated in the gate capacitance of the storage transistor 37 can be amplified and output to the read column signal line 34 efficiently.

  Further, when an electrical signal (pixel signal) is held in the storage unit 3b, the storage transistor 37 and the read transistor 38 are brought into a conductive state as in the case of reading the electrical signal held in the storage unit 3b. That is, when the electrical signal is held in the storage unit 3b, the state is the same as the state when the electrical signal held in the storage unit 3b is read, so that the held signal value can be accurately held and read. .

  At time t9, the signal S41 becomes H level, the read transistor 33 is turned on, and an output signal corresponding to the reference signal Vref is output to the read column signal line 34.

  At time t10, the signal S43 becomes H level, the read transistor 38 is turned on, and an output signal corresponding to the output signal V1 is output to the read column signal line 34.

  Here, the reference signal Vref is accumulated in the above-described gate capacitance during the period from time t3 to time t9, and the output signal V1 is accumulated during the period from time t7 to time t10. As described above, this accumulation period is several hundred msec at the maximum because the driving frequency of the horizontal scanning circuit 5 is limited.

  In the case where a leakage current occurs in the accumulation period in a node (source or drain) connected to the gate capacitance, for example, a node connected to the gate electrode of the storage transistor 37 during this long storage period, the storage transistor 37 Noise is mixed in the signal accumulated in the gate capacitance. Therefore, it is necessary to suppress leakage current at a node connected to the gate electrode of the storage transistor 37.

  Examples of the leakage current include junction leakage current, GIDL (Gate Induced Drain Leakage), interface leakage, and the like. In particular, when a fine transistor is used for the memory, it is necessary to increase the impurity concentration of the well in order to prevent punch-through. In this case, the electric field strength at the pn junction between the source or drain of the writing transistor and the well increases, and the junction leakage current generated due to the electric field strength at the pn junction increases.

  In order to reduce the electric field strength at the pn junction between the source or drain of the writing transistor and the well, the following processing is performed.

  Specifically, the vertical scanning circuit 6 applies a predetermined voltage to the well (for example, well 61) in which the write transistor (for example, write transistor 31) is formed using the terminals 50 and 51 and the like during the accumulation period. Apply. In other words, the vertical scanning circuit 6 as the voltage application unit reduces the electric field strength at the junction between the well and the diffusion region during the storage period (accumulation period) for storing the pixel signal in the storage unit. A predetermined voltage to be applied is applied to the well.

  Here, for example, it is assumed that the conductivity type of the well is n-type and the conductivity type of the diffusion region is p-type. In this case, the predetermined voltage is an H level voltage in order to apply a reverse bias to the junction between the well and the diffusion region.

  As a result, the electric field strength at the pn junction in the write transistor to which a voltage is applied can be reduced. Thereby, the amount of leakage current generated at the pn junction can be suppressed. That is, the amount of leakage current generated in the memory portion including the writing transistor can be suppressed.

  For example, the vertical scanning circuit 6 sets the signal S50 to H level during the period from time t3 to time t9, and sets the signal S51 to H level during the period from time t7 to time t10.

  In order to avoid the influence on the read operation due to the voltage application to the well, as shown in FIG. 4, a time lag may be provided at the application start time of the signals S50 and S51 from the application pulse application end time. The write pulse is the H level portion of the signals S40 and S42.

  At the end of voltage application to the well, noise due to coupling or the like is mixed into the accumulated signal, but the noise is reduced by reducing the junction capacitance of the pn junction between the source or drain of the writing transistor and the well. be able to. Similarly, noise can be reduced by calculating a difference from a reference signal driven by a well voltage.

  Here, the voltages of the signals S50 and S51 applied to the terminals 50 and 51, respectively, are preferably voltages at which a reverse bias is applied to the pn junction between the source or drain and the well. When a forward bias is applied to the pn junction, a current flows, and the accumulated signal is destroyed.

  Therefore, in the present embodiment, the vertical scanning circuit 6 applies a reverse bias to the junction (pn junction) between the source or drain of the write transistor 31 and the well 61 during the accumulation period. The vertical scanning circuit 6 applies a reverse bias to the junction (pn junction) between the source or drain of the write transistor 36 and the well 62 during the accumulation period.

  Specifically, the vertical scanning circuit 6 supplies to the terminal 50 a signal S50 having a voltage for applying a reverse bias to the junction between the source or drain of the writing transistor 31 and the well 61 during the accumulation period. To do.

  In addition, the vertical scanning circuit 6 supplies a signal S51 having a voltage for applying a reverse bias to the junction between the source or drain of the writing transistor 36 and the well 62 during the accumulation period.

  That is, the vertical scanning circuit 6 serving as the voltage application unit applies the predetermined voltage for applying a reverse bias to the junction between the well 61 and the diffusion region during the storage period (accumulation period). 61 is applied. The diffusion region is, for example, the diffusion region 71 or the diffusion region 72. The predetermined voltage for applying a reverse bias to the junction is a predetermined voltage for reducing the electric field strength at the junction between the well and the diffusion region as described above.

  Thereby, the amount of leak current generated at the junction between the well 61 and the diffusion region can be suppressed. That is, the amount of leakage current generated in the memory portion including the write transistor having the source or drain as the diffusion region can be suppressed.

  Further, it is assumed that a predetermined voltage is applied to the well in which the memory portion is formed during the signal reading period. The readout period is a period during which processing for reading out pixel signals from the storage unit is performed. In this case, problems such as fluctuations in the on-state currents of the read transistor and the storage transistor included in the storage unit occur.

  Therefore, it is preferable that the ground voltage is applied to the well in which the memory portion is formed during the reading period. Note that in the case where the conductivity type of the well is n-type, it is preferable that a power supply voltage is applied to the well during the reading period.

  Specifically, the vertical scanning circuit 6 as the voltage application unit uses the terminals 50 and 51 and the like to supply a ground voltage or a power supply voltage to the well during a reading period for reading a pixel signal from the storage unit. Apply. That is, the ground voltage or the power supply voltage is applied to the well in which the memory portion is formed during the reading period.

  Note that the ground voltage is applied to the p-type well during the readout period as described above. On the other hand, a power supply voltage is applied to the n-type well during the read period.

  Here, it is assumed that the storage unit is the storage unit 3a. In this case, the vertical scanning circuit 6 applies a ground voltage to the well 61 in which the storage unit 3a is formed during a readout period for reading out pixel signals from the storage unit 3a. That is, the ground voltage is applied to the well 61 during the readout period.

  Thus, fluctuations in on-state currents of the read transistor and the storage transistor included in the storage unit can be prevented.

  FIG. 5 is a diagram showing a schematic configuration of the memory circuit 2 in the solid-state imaging device 400 according to the embodiment of the present invention. As shown in FIG. 5, the plurality of storage units included in the storage circuit 2 are divided into a plurality of blocks BK. Thereby, the memory circuit 2 can adjust the voltage applied to the well corresponding to the transistor included in the memory unit for each block BK.

  Here, the structure of the well will be described in detail.

  A p-type well is formed in the semiconductor substrate 70. That is, a first conductivity type (p-type) well is formed in the semiconductor substrate 70. The well formed in the semiconductor substrate 70 may be n-type.

  Wells formed in the semiconductor substrate 70 are electrically separated for each block BK. That is, the well formed in the semiconductor substrate 70 is separated into a plurality of wells. Two of the separated wells are, for example, wells 61 and 62 in FIG. 3B.

  The well formed in the semiconductor substrate 70 is electrically and physically separated by, for example, the second insulating separation portion 65 of FIG. 3B. The separated wells 61 and 62 correspond to two adjacent blocks BK, respectively.

  For this reason, the voltage applied to the well can be easily adjusted according to the operation period of the block BK. Specifically, the vertical scanning circuit 6 applies the predetermined voltage described above to a well (for example, well 61) corresponding to the block BK in which a plurality of storage units corresponding to the block BK are in the accumulation period. Further, the vertical scanning circuit 6 applies a ground voltage to a well (for example, well 62) corresponding to the block BK in which a plurality of storage units corresponding to the block BK are in a reading period.

  When the conductivity type of the well is n-type, the vertical scanning circuit 6 applies a power supply voltage to the well corresponding to the block BK in which the plurality of storage units corresponding to the block BK are in the reading period.

  That is, the vertical scanning circuit 6 as a voltage application unit applies any one of the predetermined voltage, the ground voltage, and the power supply voltage to the separated well corresponding to each block BK according to the operation period of the block BK. To do. Thus, any one of the predetermined voltage, the ground voltage, and the power supply voltage is applied to the separated well corresponding to each block BK according to the operation period of the block. Thus, the vertical scanning circuit 6 switches the voltage applied to the well. That is, different voltages can be applied to wells corresponding to different blocks BK.

  When a voltage is applied to the whole well formed in the semiconductor substrate 70, it is difficult to drive the well at high speed because the capacity and resistance of the well are high. Therefore, as described above, the well formed in the semiconductor substrate 70 is electrically separated for each block BK, so that the capacity and resistance of the well can be minimized. As a result, each separated well can be driven at high speed.

  Further, as shown in FIG. 5, each of the divided blocks BK is set in units of rows of the plurality of storage units. Thereby, a further effect can be obtained compared with the configuration in which the block BK is set in units other than the row unit.

  Specifically, as described above, the vertical scanning circuit 6 of the solid-state imaging device 400 performs the pixel signal readout operation from the storage unit for each row of the plurality of storage units. That is, the solid-state imaging device 400 performs a process of reading pixel signals in units of rows of the plurality of storage units.

  Therefore, the block BK is set for each row of the plurality of storage units, that is, by dividing the block BK for each row, the voltage of the well corresponding to the storage unit storing the signal and the signal are read. It is possible to easily separate the voltage of the well of the storage portion.

  As described above, a predetermined voltage is applied to the well corresponding to the block BK during the accumulation period, and a ground voltage is applied to the well corresponding to the block BK during the reading period. In this case, the storage unit 3a and the storage unit 3b illustrated in FIG. 3A belong to (correspond to) different blocks BK. Therefore, the voltage applied to the well can be adjusted independently.

  The setting unit of the block BK is not limited to the row unit, and may be a plurality of adjacent storage unit units, for example.

  Here, even if a predetermined voltage is applied to the well during the accumulation period, the transistor in the memory portion corresponding to the well is not operating. Therefore, all the voltages applied to the wells corresponding to each of the write transistor, the read transistor, and the storage transistor included in the storage unit for each block BK may be set to be the same.

  Next, the electrical isolation structure of the well and the transistor will be described in detail with reference to FIG. 3B.

  Each of the write transistor 31, the read transistor 33, and the storage transistor 32 included in the storage unit 3 a is electrically separated by the first insulating separation unit 60. In addition, each of the write transistor 36, the read transistor 38, and the storage transistor 37 included in the storage unit 3 b is electrically separated by the first insulating separation unit 60. These transistors are formed in the well 61 or the well 62. That is, each of the plurality of storage units included in the storage circuit 2 includes at least two transistors, and each of the at least two transistors is electrically isolated by the first insulating separation unit 60.

  The first insulation isolation part 60 is formed using, for example, an element isolation technique called STI (Shallow Trench Isolation). In FIG. 3B, the read transistors 33 and 38 are not shown for convenience.

  As described above, the wells 61 and 62 in which the wells formed in the semiconductor substrate 70 are electrically and physically separated by the second insulating separation portion 65 are formed in the semiconductor substrate 70. Each of the wells 61 and 62 corresponds to two adjacent blocks BK.

  That is, the plurality of blocks BK in FIG. 5 are associated with a plurality of wells in which the wells formed in the semiconductor substrate 70 by the second insulating separation portion 65 are electrically separated.

  Here, in the semiconductor substrate 70, the second insulating separation portion 65 is formed to a position deeper than the first insulating separation portion 60. That is, in the semiconductor substrate 70, the lower end of the second insulating separation part 65 is deeper than the lower end of the first insulating separation part 60.

  In the semiconductor substrate 70, the second insulating separation portion 65 is formed to a position deeper than the wells 61 and 62. That is, in the semiconductor substrate 70, the lower end of the second insulating separation portion 65 is deeper than the lower ends of the separated wells 61 and 62.

  The second insulation isolation portion 65 is formed using, for example, an element isolation technique called DTI (Deep Trench Isolation).

  As described above, in the semiconductor substrate 70, the wells corresponding to the respective blocks BK can be electrically separated by the second insulating separation portion 65 formed to a deep position. Therefore, the voltage applied to the well can be adjusted independently for each block.

  In FIG. 3B, as an example, the well 61 and the well 62 are electrically separated. In this case, the occupied area of the separation part can be made smaller than that of the separation structure using the diffusion layer. Therefore, an increase in chip cost can be suppressed.

  As described above, in the storage circuit 2 of the solid-state imaging device 400 according to the present embodiment, the storage transistors 32 and 37 both serve as a storage capacitor (storage capacitor) and serve as an amplifier (amplification transistor). Take on. Therefore, the circuit area can be reduced and the junction leakage current can be suppressed as compared with the solid-state imaging device according to the prior art that has the storage capacitor and the amplifier independently.

  The present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the gist of the present invention.

  For example, each transistor used in the present invention may be either p-type or n-type.

  Further, the storage capacity is not limited to the transistor, and may be constituted by other elements.

  In addition, the solid-state imaging device according to the present invention includes other embodiments realized by combining arbitrary components in the above-described embodiments, and other embodiments that do not depart from the gist of the present invention. Modifications obtained by applying various modifications conceived by a trader and various devices including the solid-state imaging device according to the present invention are also included in the present invention. For example, a movie camera provided with the solid-state imaging device according to the present invention is also included in the present invention.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The solid-state imaging device of the present invention can be used for surveillance cameras, network cameras, vehicle-mounted cameras, digital cameras, mobile phones, and the like, and can improve the image quality of captured images of these devices.

DESCRIPTION OF SYMBOLS 1 Pixel circuit 2a Pixel part 2 Storage circuit 3a, 3b Storage part 3 Noise removal circuit 5 Horizontal scanning circuit 6 Vertical scanning circuit 20, 35 Current source 21 Column signal line 31, 36 Write transistor 32, 37 Storage transistor 33, 38 Read transistor 34 readout column signal line 60 first insulation separation unit 65 second insulation separation unit 70 semiconductor substrate 200, 400 solid-state imaging device 1000 camera

Claims (6)

A plurality of pixel units arranged in a matrix on a semiconductor substrate and outputting a pixel signal that is a signal corresponding to the amount of incident light;
A column signal line provided for each column of the plurality of pixel portions;
A plurality of storage units that are provided for each of the column signal lines and store pixel signals transferred from the column signal lines;
A voltage application unit for applying a voltage,
A first conductivity type well is formed in the semiconductor substrate,
Each of the plurality of storage units is
A first transistor formed in the well for reading the pixel signal from each of the plurality of pixel portions via the column signal line;
A storage capacity for storing the pixel signal;
A diffusion region of a second conductivity type different from the first conductivity type, which is a source or drain of the first transistor, is connected to the storage capacitor;
The well and the diffusion region are joined,
The voltage application unit applies a predetermined voltage to the well for reducing the electric field strength at the junction between the well and the diffusion region during a storage period for storing a pixel signal in the storage unit. . 2. The solid-state imaging device according to claim 1, wherein the voltage applying unit applies the predetermined voltage for applying a reverse bias to a junction between the well and the diffusion region during the storage period. The solid-state imaging device according to claim 1, wherein the voltage application unit applies a ground voltage or a power supply voltage to the well during a reading period for reading a pixel signal from the storage unit. The plurality of storage units are divided into a plurality of blocks,
The well is electrically separated for each block;
The voltage application unit applies any one of the predetermined voltage, ground voltage, and power supply voltage to the separated well corresponding to each block according to the operation period of the block. The solid-state imaging device according to item 1. The plurality of storage units are arranged in a matrix,
Each of the divided blocks is set in units of rows of the plurality of storage units,
The solid-state imaging device according to claim 4, wherein the solid-state imaging device performs a process of reading out pixel signals in units of rows of the plurality of storage units. In the semiconductor substrate, a first insulation separation part and a second insulation separation part are formed,
Each of the plurality of storage units includes at least two transistors including the first transistor,
Each of the at least two transistors is electrically separated by the first isolation portion;
The plurality of blocks are respectively associated with a plurality of wells in which the wells are electrically separated by the second insulating separation part,
In the semiconductor substrate, the lower end of the second insulating isolation part is deeper than the lower end of the first insulating isolation part,
6. The solid-state imaging device according to claim 1, wherein a lower end of the second insulating separation portion is located deeper than a lower end of the separated well in the semiconductor substrate.

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